6 #include <device/pci_def.h>
12 static int is_cpu_pre_c0(void)
17 #define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
18 (((BUS) & 0xFF) << 16) | \
19 (((DEV) & 0x1f) << 11) | \
20 (((FN) & 0x07) << 8) | \
23 #define PCI_DEV(BUS, DEV, FN) ( \
24 (((BUS) & 0xFF) << 16) | \
25 (((DEV) & 0x1f) << 11) | \
28 #define PCI_ID(VENDOR_ID, DEVICE_ID) \
29 ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
31 typedef unsigned device_t;
33 unsigned char pci_register[256*5*3*256];
35 static uint8_t pci_read_config8(device_t dev, unsigned where)
39 return pci_register[addr];
42 static uint16_t pci_read_config16(device_t dev, unsigned where)
46 return pci_register[addr] | (pci_register[addr + 1] << 8);
49 static uint32_t pci_read_config32(device_t dev, unsigned where)
54 value = pci_register[addr] |
55 (pci_register[addr + 1] << 8) |
56 (pci_register[addr + 2] << 16) |
57 (pci_register[addr + 3] << 24);
60 print_debug("pcir32(");
61 print_debug_hex32(addr);
63 print_debug_hex32(value);
70 static void pci_write_config8(device_t dev, unsigned where, uint8_t value)
74 pci_register[addr] = value;
77 static void pci_write_config16(device_t dev, unsigned where, uint16_t value)
81 pci_register[addr] = value & 0xff;
82 pci_register[addr + 1] = (value >> 8) & 0xff;
85 static void pci_write_config32(device_t dev, unsigned where, uint32_t value)
89 pci_register[addr] = value & 0xff;
90 pci_register[addr + 1] = (value >> 8) & 0xff;
91 pci_register[addr + 2] = (value >> 16) & 0xff;
92 pci_register[addr + 3] = (value >> 24) & 0xff;
95 print_debug("pciw32(");
96 print_debug_hex32(addr);
98 print_debug_hex32(value);
103 #define PCI_DEV_INVALID (0xffffffffU)
104 static device_t pci_locate_device(unsigned pci_id, device_t dev)
106 for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
108 id = pci_read_config32(dev, 0);
113 return PCI_DEV_INVALID;
119 static void uart_tx_byte(unsigned char data)
121 write(STDOUT_FILENO, &data, 1);
123 static void hlt(void)
127 #include "console/console.c"
129 unsigned long log2(unsigned long x)
131 // assume 8 bits per byte.
132 unsigned long i = 1 << (sizeof(x)*8 - 1);
133 unsigned long pow = sizeof(x) * 8 - 1;
136 static const char errmsg[] = " called with invalid parameter of 0\n";
137 write(STDERR_FILENO, __func__, sizeof(__func__) - 1);
138 write(STDERR_FILENO, errmsg, sizeof(errmsg) - 1);
141 for(; i > x; i >>= 1, pow--)
147 typedef struct msr_struct
153 static inline msr_t rdmsr(unsigned index)
161 static inline void wrmsr(unsigned index, msr_t msr)
167 #define SIO_BASE 0x2e
169 static void hard_reset(void)
171 /* FIXME implement the hard reset case... */
175 static void memreset_setup(void)
180 static void memreset(int controllers, const struct mem_controller *ctrl)
185 static inline void activate_spd_rom(const struct mem_controller *ctrl)
191 static uint8_t spd_mt4lsdt464a[256] =
193 0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70,
194 0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01,
195 0x01, 0x00, 0x0E, 0x75, 0x54, 0x00, 0x00, 0x0F, 0x0E, 0x0F,
197 0x25, 0x08, 0x15, 0x08, 0x15, 0x08, 0x00, 0x12, 0x01, 0x4E,
198 0x9C, 0xE4, 0xB7, 0x46, 0x2C, 0xFF, 0x01, 0x02, 0x03, 0x04,
199 0x05, 0x06, 0x07, 0x08, 0x09, 0x01, 0x02, 0x03, 0x04, 0x05,
200 0x06, 0x07, 0x08, 0x09, 0x00,
203 static uint8_t spd_micron_512MB_DDR333[256] =
205 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60,
206 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
207 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
208 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
209 0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00,
210 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
211 0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
212 0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31,
213 0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43,
214 0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00,
215 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
216 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
217 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
218 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
219 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
220 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
221 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
222 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
223 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
224 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
225 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
226 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
227 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
228 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
229 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
230 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
233 static uint8_t spd_micron_256MB_DDR333[256] =
235 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60,
236 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
237 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
238 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
239 0x00, 0x3c, 0x48, 0x30, 0x23, 0x50, 0x00, 0x00, 0x00, 0x00,
240 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
241 0x00, 0x00, 0x00, 0x58, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
242 0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36,
243 0x34, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, 0x31,
244 0x20, 0x01, 0x00, 0x03, 0x19, 0x17, 0x05, 0xb2, 0xf4, 0x00,
245 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
246 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
247 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
248 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
249 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
250 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
251 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
252 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
253 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
254 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
255 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
256 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
257 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
258 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
259 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
260 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
264 static uint8_t spd_data[MAX_DIMMS*256];
266 static unsigned spd_count, spd_fail_count;
267 static int spd_read_byte(unsigned device, unsigned address)
271 if ((device < DIMM0) || (device >= (DIMM0 + MAX_DIMMS))) {
275 device -= DIMM0; /* 0x50 */
280 else if (spd_data[(device << 8) | 2] != 7) {
284 result = spd_data[(device << 8) | address];
288 print_debug("spd_read_byte(");
289 print_debug_hex32(device);
291 print_debug_hex32(address);
292 print_debug(") -> ");
293 print_debug_hex32(result);
296 if (spd_count >= spd_fail_count) {
302 /* no specific code here. this should go away completely */
303 static void coherent_ht_mainboard(unsigned cpus)
308 #include "../../../lib/generic_sdram.c"
312 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
313 static void raminit_main(void)
316 * GPIO28 of 8111 will control H0_MEMRESET_L
317 * GPIO29 of 8111 will control H1_MEMRESET_L
319 static const struct mem_controller cpu[] = {
323 .f0 = PCI_DEV(0, 0x18, 0),
324 .f1 = PCI_DEV(0, 0x18, 1),
325 .f2 = PCI_DEV(0, 0x18, 2),
326 .f3 = PCI_DEV(0, 0x18, 3),
327 .channel0 = { DIMM0+0, DIMM0+2, DIMM0+4, DIMM0+6 },
328 .channel1 = { DIMM0+1, DIMM0+3, DIMM0+5, DIMM0+7 },
334 .f0 = PCI_DEV(0, 0x19, 0),
335 .f1 = PCI_DEV(0, 0x19, 1),
336 .f2 = PCI_DEV(0, 0x19, 2),
337 .f3 = PCI_DEV(0, 0x19, 3),
338 .channel0 = { DIMM0+8, DIMM0+10, DIMM0+12, DIMM0+14 },
339 .channel1 = { DIMM0+9, DIMM0+11, DIMM0+13, DIMM0+15 },
345 sdram_initialize(ARRAY_SIZE(cpu), cpu);
349 static void reset_tests(void)
351 /* Clear the results of any previous tests */
352 memset(pci_register, 0, sizeof(pci_register));
353 memset(spd_data, 0, sizeof(spd_data));
355 spd_fail_count = UINT_MAX;
357 pci_write_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP,
359 NBCAP_MP| NBCAP_BIG_MP |
360 /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */
361 (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) |
364 pci_write_config32(PCI_DEV(0, 0x19, 3), NORTHBRIDGE_CAP,
366 NBCAP_MP| NBCAP_BIG_MP |
367 /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */
368 (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) |
372 pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP);
376 static void test1(void)
380 memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
381 memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
383 memcpy(&spd_data[2*256], spd_micron_512MB_DDR333, 256);
384 memcpy(&spd_data[3*256], spd_micron_512MB_DDR333, 256);
386 memcpy(&spd_data[8*256], spd_micron_512MB_DDR333, 256);
387 memcpy(&spd_data[9*256], spd_micron_512MB_DDR333, 256);
388 memcpy(&spd_data[10*256], spd_micron_512MB_DDR333, 256);
389 memcpy(&spd_data[11*256], spd_micron_512MB_DDR333, 256);
395 print_debug("spd_count: ");
396 print_debug_hex32(spd_count);
403 static void do_test2(int i)
406 memcpy(&tmp_buf, &end_buf, sizeof(end_buf));
407 if (setjmp(end_buf) != 0) {
413 print_debug("\nSPD will fail after: ");
414 print_debug_hex32(spd_fail_count);
415 print_debug(" accesses.\n");
417 memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
418 memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
423 memcpy(&end_buf, &tmp_buf, sizeof(end_buf));
426 static void test2(void)
429 for(i = 0; i < 0x48; i++) {
435 int main(int argc, char **argv)
437 if (setjmp(end_buf) != 0) {