2 * This file is part of the coreboot project.
4 * Copyright (C) 2002 Linux Networx
5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
6 * Copyright (C) 2004 YingHai Lu
7 * Copyright (C) 2008 Advanced Micro Devices, Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <cpu/x86/mem.h>
24 #include <cpu/x86/cache.h>
25 #include <cpu/x86/mtrr.h>
26 #include <cpu/x86/tsc.h>
32 #ifndef QRANK_DIMM_SUPPORT
33 #define QRANK_DIMM_SUPPORT 0
36 static inline void print_raminit(const char *strval, uint32_t val)
38 #if CONFIG_USE_PRINTK_IN_CAR
39 printk_debug("%s%08x\r\n", strval, val);
41 print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
45 #define RAM_TIMING_DEBUG 0
47 static inline void print_tx(const char *strval, uint32_t val)
49 #if RAM_TIMING_DEBUG == 1
50 print_raminit(strval, val);
55 static inline void print_t(const char *strval)
57 #if RAM_TIMING_DEBUG == 1
64 #if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
65 # error "CONFIG_LB_MEM_TOPK must be a power of 2"
68 #include "amdk8_f_pci.c"
71 // for PCI_ADDR(0, 0x18, 2, 0x98) index, and PCI_ADDR(0x, 0x18, 2, 0x9c) data
74 [29: 0] DctOffset (Dram Controller Offset)
75 [30:30] DctAccessWrite (Dram Controller Read/Write Select)
78 [31:31] DctAccessDone (Dram Controller Access Done)
79 0 = Access in progress
80 1 = No access is progress
83 [31: 0] DctOffsetData (Dram Controller Offset Data)
86 - Write the register num to DctOffset with DctAccessWrite = 0
87 - poll the DctAccessDone until it = 1
88 - Read the data from DctOffsetData
90 - Write the data to DctOffsetData
91 - Write register num to DctOffset with DctAccessWrite = 1
92 - poll the DctAccessDone untio it = 1
97 static void setup_resource_map(const unsigned int *register_values, int max)
100 for(i = 0; i < max; i += 3) {
104 dev = register_values[i] & ~0xff;
105 where = register_values[i] & 0xff;
106 reg = pci_read_config32(dev, where);
107 reg &= register_values[i+1];
108 reg |= register_values[i+2];
109 pci_write_config32(dev, where, reg);
113 static int controller_present(const struct mem_controller *ctrl)
115 return pci_read_config32(ctrl->f0, 0) == 0x11001022;
118 static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
120 static const unsigned int register_values[] = {
122 /* Careful set limit registers before base registers which contain the enables */
123 /* DRAM Limit i Registers
132 * [ 2: 0] Destination Node ID
142 * [10: 8] Interleave select
143 * specifies the values of A[14:12] to use with interleave enable.
145 * [31:16] DRAM Limit Address i Bits 39-24
146 * This field defines the upper address bits of a 40 bit address
147 * that define the end of the DRAM region.
149 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
150 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
151 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
152 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
153 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
154 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
155 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
156 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
157 /* DRAM Base i Registers
166 * [ 0: 0] Read Enable
169 * [ 1: 1] Write Enable
170 * 0 = Writes Disabled
173 * [10: 8] Interleave Enable
174 * 000 = No interleave
175 * 001 = Interleave on A[12] (2 nodes)
177 * 011 = Interleave on A[12] and A[14] (4 nodes)
181 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
183 * [13:16] DRAM Base Address i Bits 39-24
184 * This field defines the upper address bits of a 40-bit address
185 * that define the start of the DRAM region.
187 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
188 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
189 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
190 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
191 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
192 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
193 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
194 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
196 /* DRAM CS Base Address i Registers
205 * [ 0: 0] Chip-Select Bank Enable
209 * [ 2: 2] Memory Test Failed
211 * [13: 5] Base Address (21-13)
212 * An optimization used when all DIMM are the same size...
214 * [28:19] Base Address (36-27)
215 * This field defines the top 11 addresses bit of a 40-bit
216 * address that define the memory address space. These
217 * bits decode 32-MByte blocks of memory.
220 PCI_ADDR(0, 0x18, 2, 0x40), 0xe007c018, 0x00000000,
221 PCI_ADDR(0, 0x18, 2, 0x44), 0xe007c018, 0x00000000,
222 PCI_ADDR(0, 0x18, 2, 0x48), 0xe007c018, 0x00000000,
223 PCI_ADDR(0, 0x18, 2, 0x4C), 0xe007c018, 0x00000000,
224 PCI_ADDR(0, 0x18, 2, 0x50), 0xe007c018, 0x00000000,
225 PCI_ADDR(0, 0x18, 2, 0x54), 0xe007c018, 0x00000000,
226 PCI_ADDR(0, 0x18, 2, 0x58), 0xe007c018, 0x00000000,
227 PCI_ADDR(0, 0x18, 2, 0x5C), 0xe007c018, 0x00000000,
228 /* DRAM CS Mask Address i Registers
233 * Select bits to exclude from comparison with the DRAM Base address register.
235 * [13: 5] Address Mask (21-13)
236 * Address to be excluded from the optimized case
238 * [28:19] Address Mask (36-27)
239 * The bits with an address mask of 1 are excluded from address comparison
243 PCI_ADDR(0, 0x18, 2, 0x60), 0xe007c01f, 0x00000000,
244 PCI_ADDR(0, 0x18, 2, 0x64), 0xe007c01f, 0x00000000,
245 PCI_ADDR(0, 0x18, 2, 0x68), 0xe007c01f, 0x00000000,
246 PCI_ADDR(0, 0x18, 2, 0x6C), 0xe007c01f, 0x00000000,
248 /* DRAM Control Register
250 * [ 3: 0] RdPtrInit ( Read Pointer Initial Value)
251 * 0x03-0x00: reserved
252 * [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO)
255 * 010 = 1.5 Memory Clocks
256 * 011 = 2 Memory Clocks
257 * 100 = 2.5 Memory Clocks
258 * 101 = 3 Memory Clocks
259 * 110 = 3.5 Memory Clocks
262 * [16:16] AltVidC3MemClkTriEn (AltVID Memory Clock Tristate Enable)
263 * Enables the DDR memory clocks to be tristated when alternate VID mode is enabled. This bit has no effect if the DisNbClkRamp bit (F3, 0x88) is set
264 * [17:17] DllTempAdjTime (DLL Temperature Adjust Cycle Time)
267 * [18:18] DqsRcvEnTrain (DQS Receiver Enable Training Mode)
268 * 0 = Normal DQS Receiver enable operation
269 * 1 = DQS receiver enable training mode
272 PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6<<4)|(6<<0),
274 /* DRAM Initialization Register
276 * [15: 0] MrsAddress (Address for MRS/EMRS Commands)
277 * this field specifies the dsata driven on the DRAM address pins 15-0 for MRS and EMRS commands
278 * [18:16] MrsBank (Bank Address for MRS/EMRS Commands)
279 * this files specifies the data driven on the DRAM bank pins for the MRS and EMRS commands
281 * [24:24] SendPchgAll (Send Precharge All Command)
282 * Setting this bit causes the DRAM controller to send a precharge all command. This bit is cleared by the hardware after the command completes
283 * [25:25] SendAutoRefresh (Send Auto Refresh Command)
284 * Setting this bit causes the DRAM controller to send an auto refresh command. This bit is cleared by the hardware after the command completes
285 * [26:26] SendMrsCmd (Send MRS/EMRS Command)
286 * Setting this bit causes the DRAM controller to send the MRS or EMRS command defined by the MrsAddress and MrsBank fields. This bit is cleared by the hardware adter the commmand completes
287 * [27:27] DeassertMemRstX (De-assert Memory Reset)
288 * Setting this bit causes the DRAM controller to de-assert the memory reset pin. This bit cannot be used to assert the memory reset pin
289 * [28:28] AssertCke (Assert CKE)
290 * setting this bit causes the DRAM controller to assert the CKE pins. This bit cannot be used to de-assert the CKE pins
292 * [31:31] EnDramInit (Enable DRAM Initialization)
293 * Setting this bit puts the DRAM controller in a BIOS controlled DRAM initialization mode. BIOS must clear this bit aster DRAM initialization is complete.
295 // PCI_ADDR(0, 0x18, 2, 0x7C), 0x60f80000, 0,
298 /* DRAM Bank Address Mapping Register
300 * Specify the memory module size
320 PCI_ADDR(0, 0x18, 2, 0x80), 0xffff0000, 0x00000000,
321 /* DRAM Timing Low Register
323 * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid)
333 * [ 5: 4] Trcd (Ras#-active to Cas# read/write delay)
339 * [ 9: 8] Trp (Row Precharge Time, Precharge-to-Active or Auto-Refresh)
345 * [11:11] Trtp (Read to Precharge Time, read Cas# to precharge time)
346 * 0 = 2 clocks for Burst Length of 32 Bytes
347 * 4 clocks for Burst Length of 64 Bytes
348 * 1 = 3 clocks for Burst Length of 32 Bytes
349 * 5 clocks for Burst Length of 64 Bytes
350 * [15:12] Tras (Minimum Ras# Active Time)
353 * 0010 = 5 bus clocks
355 * 1111 = 18 bus clocks
356 * [19:16] Trc (Row Cycle Time, Ras#-active to Ras#-active or auto refresh of the same bank)
357 * 0000 = 11 bus clocks
358 * 0010 = 12 bus clocks
360 * 1110 = 25 bus clocks
361 * 1111 = 26 bus clocks
362 * [21:20] Twr (Write Recovery Time, From the last data to precharge, writes can go back-to-back)
367 * [23:22] Trrd (Active-to-active (Ras#-to-Ras#) Delay of different banks)
372 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A, BIOS should set it to reduce the power consumption)
373 * Bit F(1207) M2 Package S1g1 Package
375 * 1 N/A MA0_CLK1 MA0_CLK1
378 * 4 MA1_CLK MA1_CLK0 N/A
379 * 5 MA0_CLK MA0_CLK0 MA0_CLK0
381 * 7 N/A MA0_CLK2 MA0_CLK2
383 PCI_ADDR(0, 0x18, 2, 0x88), 0x000004c8, 0xff000002 /* 0x03623125 */ ,
384 /* DRAM Timing High Register
387 * [ 6: 4] TrwtTO (Read-to-Write Turnaround for Data, DQS Contention)
397 * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay, minium write-to-read delay when both access the same chip select)
402 * [11:10] Twrrd (Write to Read DIMM Termination Turnaround, minimum write-to-read delay when accessing two different DIMMs)
407 * [13:12] Twrwr (Write to Write Timing)
408 * 00 = 1 bus clocks ( 0 idle cycle on the bus)
409 * 01 = 2 bus clocks ( 1 idle cycle on the bus)
410 * 10 = 3 bus clocks ( 2 idle cycles on the bus)
412 * [15:14] Trdrd ( Read to Read Timing)
413 * 00 = 2 bus clocks ( 1 idle cycle on the bus)
414 * 01 = 3 bus clocks ( 2 idle cycles on the bus)
415 * 10 = 4 bus clocks ( 3 idle cycles on the bus)
416 * 11 = 5 bus clocks ( 4 idel cycles on the bus)
417 * [17:16] Tref (Refresh Rate)
418 * 00 = Undefined behavior
420 * 10 = Refresh interval of 7.8 microseconds
421 * 11 = Refresh interval of 3.9 microseconds
423 * [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0, based on DRAM density and speed)
424 * 000 = 75 ns (all speeds, 256Mbit)
425 * 001 = 105 ns (all speeds, 512Mbit)
426 * 010 = 127.5 ns (all speeds, 1Gbit)
427 * 011 = 195 ns (all speeds, 2Gbit)
428 * 100 = 327.5 ns (all speeds, 4Gbit)
432 * [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1, based on DRAM density and speed)
433 * [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2, based on DRAM density and speed)
434 * [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3, based on DRAM density and speed)
436 PCI_ADDR(0, 0x18, 2, 0x8c), 0x000c008f, (2 << 16)|(1 << 8),
437 /* DRAM Config Low Register
439 * [ 0: 0] InitDram (Initialize DRAM)
440 * 1 = write 1 cause DRAM controller to execute the DRAM initialization, when done it read to 0
441 * [ 1: 1] ExitSelfRef ( Exit Self Refresh Command )
442 * 1 = write 1 causes the DRAM controller to bring the DRAMs out fo self refresh mode
444 * [ 5: 4] DramTerm (DRAM Termination)
445 * 00 = On die termination disabled
450 * [ 7: 7] DramDrvWeak ( DRAM Drivers Weak Mode)
451 * 0 = Normal drive strength mode.
452 * 1 = Weak drive strength mode
453 * [ 8: 8] ParEn (Parity Enable)
454 * 1 = Enable address parity computation output, PAR, and enables the parity error input, ERR
455 * [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable)
456 * 1 = Enable high temperature ( two times normal ) self refresh rate
457 * [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes)
460 * [11:11] Width128 ( Width of DRAM interface)
461 * 0 = the controller DRAM interface is 64-bits wide
462 * 1 = the controller DRAM interface is 128-bits wide
463 * [12:12] X4Dimm (DIMM 0 is x4)
464 * [13:13] X4Dimm (DIMM 1 is x4)
465 * [14:14] X4Dimm (DIMM 2 is x4)
466 * [15:15] X4Dimm (DIMM 3 is x4)
468 * 1 = x4 DIMM present
469 * [16:16] UnBuffDimm ( Unbuffered DIMMs)
471 * 1 = Unbuffered DIMMs
473 * [19:19] DimmEccEn ( DIMM ECC Enable )
474 1 = ECC checking is being enabled for all DIMMs on the DRAM controller ( Through F3 0x44[EccEn])
477 PCI_ADDR(0, 0x18, 2, 0x90), 0xfff6004c, 0x00000010,
478 /* DRAM Config High Register
480 * [ 0: 2] MemClkFreq ( Memory Clock Frequency)
486 * [ 3: 3] MemClkFreqVal (Memory Clock Freqency Valid)
487 * 1 = BIOS need to set the bit when setting up MemClkFreq to the proper value
488 * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency)
493 * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8 registered DIMMs are present in the system
494 * 0 = DM pins function as data mask pins
495 * 1 = DM pins function as read DQS pins
497 * [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit is set, the DRAM controller is disabled, and interface in low power state
498 * 0 = Enabled (default)
500 * [15:15] PowerDownEn ( Power Down Mode Enable )
501 * 0 = Disabled (default)
503 * [16:16] PowerDown ( Power Down Mode )
504 * 0 = Channel CKE Control
505 * 1 = Chip Select CKE Control
506 * [17:17] FourRankSODimm (Four Rank SO-DIMM)
507 * 1 = this bit is set by BIOS to indicate that a four rank SO-DIMM is present
508 * [18:18] FourRankRDimm (Four Rank Registered DIMM)
509 * 1 = this bit is set by BIOS to indicate that a four rank registered DIMM is present
511 * [20:20] SlowAccessMode (Slow Access Mode (2T Mode))
512 * 0 = DRAM address and control signals are driven for one MEMCLK cycle
513 * 1 = One additional MEMCLK of setup time is provided on all DRAM address and control signals except CS, CKE, and ODT; i.e., these signals are drivern for two MEMCLK cycles rather than one
515 * [22:22] BankSwizzleMode ( Bank Swizzle Mode),
516 * 0 = Disabled (default)
519 * [27:24] DcqBypassMax ( DRAM Controller Queue Bypass Maximum)
520 * 0000 = No bypass; the oldest request is never bypassed
521 * 0001 = The oldest request may be bypassed no more than 1 time
523 * 1111 = The oldest request may be bypassed no more than 15 times
524 * [31:28] FourActWindow ( Four Bank Activate Window) , not more than 4 banks in a 8 bank device are activated
525 * 0000 = No tFAW window restriction
526 * 0001 = 8 MEMCLK cycles
527 * 0010 = 9 MEMCLK cycles
529 * 1101 = 20 MEMCLK cycles
532 PCI_ADDR(0, 0x18, 2, 0x94), 0x00a82f00,0x00008000,
533 /* DRAM Delay Line Register
535 * [ 0: 0] MemClrStatus (Memory Clear Status) : ---------Readonly
536 * when set, this bit indicates that the memory clear function is complete. Only clear by reset. BIOS should not write or read the DRAM until this bit is set by hardware
537 * [ 1: 1] DisableJitter ( Disable Jitter)
538 * When set the DDR compensation circuit will not change the values unless the change is more than one step from the current value
539 * [ 3: 2] RdWrQByp ( Read/Write Queue Bypass Count)
544 * [ 4: 4] Mode64BitMux (Mismatched DIMM Support Enable)
545 * 1 When bit enables support for mismatched DIMMs when using 128-bit DRAM interface, the Width128 no effect, only for M2 and s1g1
546 * [ 5: 5] DCC_EN ( Dynamica Idle Cycle Counter Enable)
547 * When set to 1, indicates that each entry in the page tables dynamically adjusts the idle cycle limit based on page Conflict/Page Miss (PC/PM) traffic
548 * [ 8: 6] ILD_lmt ( Idle Cycle Limit)
557 * [ 9: 9] DramEnabled ( DRAM Enabled)
558 * When Set, this bit indicates that the DRAM is enabled, this bit is set by hardware after DRAM initialization or on an exit from self refresh. The DRAM controller is intialized after the
559 * hardware-controlled initialization process ( initiated by the F2 0x90[DramInit]) completes or when the BIOS-controlled initialization process completes (F2 0x7c(EnDramInit] is
560 * written from 1 to 0)
562 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B, BIOS should set it to reduce the power consumption)
563 * Bit F(1207) M2 Package S1g1 Package
565 * 1 N/A MA0_CLK1 MA0_CLK1
568 * 4 MA1_CLK MA1_CLK0 N/A
569 * 5 MA0_CLK MA0_CLK0 MA0_CLK0
571 * 7 N/A MA0_CLK2 MA0_CLK2
573 PCI_ADDR(0, 0x18, 2, 0xa0), 0x00fffc00, 0xff000000,
575 /* DRAM Scrub Control Register
577 * [ 4: 0] DRAM Scrube Rate
579 * [12: 8] L2 Scrub Rate
581 * [20:16] Dcache Scrub
584 * 00000 = Do not scrub
606 * All Others = Reserved
608 PCI_ADDR(0, 0x18, 3, 0x58), 0xffe0e0e0, 0x00000000,
609 /* DRAM Scrub Address Low Register
611 * [ 0: 0] DRAM Scrubber Redirect Enable
613 * 1 = Scrubber Corrects errors found in normal operation
615 * [31: 6] DRAM Scrub Address 31-6
617 PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000,
618 /* DRAM Scrub Address High Register
620 * [ 7: 0] DRAM Scrubb Address 39-32
623 PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
625 // for PCI_ADDR(0, 0x18, 2, 0x98) index, and PCI_ADDR(0x, 0x18, 2, 0x9c) data
628 [29: 0] DctOffset (Dram Controller Offset)
629 [30:30] DctAccessWrite (Dram Controller Read/Write Select)
632 [31:31] DctAccessDone (Dram Controller Access Done)
633 0 = Access in progress
634 1 = No access is progress
637 [31: 0] DctOffsetData (Dram Controller Offset Data)
640 - Write the register num to DctOffset with DctAccessWrite = 0
641 - poll the DctAccessDone until it = 1
642 - Read the data from DctOffsetData
644 - Write the data to DctOffsetData
645 - Write register num to DctOffset with DctAccessWrite = 1
646 - poll the DctAccessDone untio it = 1
652 if (!controller_present(ctrl)) {
653 sysinfo->ctrl_present[ctrl->node_id] = 0;
656 sysinfo->ctrl_present[ctrl->node_id] = 1;
658 print_spew("setting up CPU");
659 print_spew_hex8(ctrl->node_id);
660 print_spew(" northbridge registers\r\n");
661 max = sizeof(register_values)/sizeof(register_values[0]);
662 for(i = 0; i < max; i += 3) {
666 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
667 where = register_values[i] & 0xff;
668 reg = pci_read_config32(dev, where);
669 reg &= register_values[i+1];
670 reg |= register_values[i+2];
671 pci_write_config32(dev, where, reg);
674 print_spew("done.\r\n");
677 static int is_dual_channel(const struct mem_controller *ctrl)
680 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
681 return dcl & DCL_Width128;
684 static int is_opteron(const struct mem_controller *ctrl)
686 /* Test to see if I am an Opteron.
687 * FIXME Testing dual channel capability is correct for now
688 * but a better test is probably required.
689 * m2 and s1g1 support dual channel too. but only support unbuffered dimm
691 #warning "FIXME implement a better test for opterons"
693 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
694 return !!(nbcap & NBCAP_128Bit);
697 static int is_registered(const struct mem_controller *ctrl)
699 /* Test to see if we are dealing with registered SDRAM.
700 * If we are not registered we are unbuffered.
701 * This function must be called after spd_handle_unbuffered_dimms.
704 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
705 return !(dcl & DCL_UnBuffDimm);
708 static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
710 /* Calculate the log base 2 size of a DIMM in bits */
717 value = spd_read_byte(device, SPD_ROW_NUM); /* rows */
718 if (value < 0) goto hw_err;
719 if ((value & 0xff) == 0) goto val_err; // max is 16 ?
720 sz->per_rank += value & 0xff;
721 sz->rows = value & 0xff;
723 value = spd_read_byte(device, SPD_COL_NUM); /* columns */
724 if (value < 0) goto hw_err;
725 if ((value & 0xff) == 0) goto val_err; //max is 11
726 sz->per_rank += value & 0xff;
727 sz->col = value & 0xff;
729 value = spd_read_byte(device, SPD_BANK_NUM); /* banks */
730 if (value < 0) goto hw_err;
731 if ((value & 0xff) == 0) goto val_err;
732 sz->bank = log2(value & 0xff); // convert 4 to 2, and 8 to 3
733 sz->per_rank += sz->bank;
735 /* Get the module data width and convert it to a power of two */
736 value = spd_read_byte(device, SPD_DATA_WIDTH);
737 if (value < 0) goto hw_err;
739 if ((value != 72) && (value != 64)) goto val_err;
740 sz->per_rank += log2(value) - 3; //64 bit So another 3 lines
742 /* How many ranks? */
743 value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK); /* number of physical banks */
744 if (value < 0) goto hw_err;
745 // value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT;
746 value &= SPD_MOD_ATTRIB_RANK_NUM_MASK;
747 value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4
749 rank == 1 only one rank or say one side
750 rank == 2 two side , and two ranks
751 rank == 4 two side , and four ranks total
752 Some one side two ranks, because of stacked
754 if ((value != 1) && (value != 2) && (value != 4 )) {
759 /* verify if per_rank is equal byte 31
760 it has the DIMM size as a multiple of 128MB.
762 value = spd_read_byte(device, SPD_RANK_SIZE);
763 if (value < 0) goto hw_err;
766 if(value <=4 ) value += 8; // add back to 1G to high
767 value += (27-5); // make 128MB to the real lines
768 if( value != (sz->per_rank)) {
769 print_err("Bad RANK Size --\r\n");
776 die("Bad SPD value\r\n");
777 /* If an hw_error occurs report that I have no memory */
788 static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size *sz, unsigned index, int is_Width128)
790 uint32_t base0, base1;
793 /* For each base register.
794 * Place the dimm size in 32 MB quantities in the bits 31 - 21.
795 * The initialize dimm size is in bits.
796 * Set the base enable bit0.
801 /* Make certain side1 of the dimm is at least 128MB */
802 if (sz->per_rank >= 27) {
803 base0 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
806 /* Make certain side2 of the dimm is at least 128MB */
807 if (sz->rank > 1) { // 2 ranks or 4 ranks
808 base1 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
811 /* Double the size if we are using dual channel memory */
813 base0 = (base0 << 1) | (base0 & 1);
814 base1 = (base1 << 1) | (base1 & 1);
817 /* Clear the reserved bits */
818 base0 &= ~0xe007fffe;
819 base1 &= ~0xe007fffe;
821 /* Set the appropriate DIMM base address register */
822 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
823 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
824 #if QRANK_DIMM_SUPPORT == 1
826 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
827 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
831 /* Enable the memory clocks for this DIMM by Clear the MemClkDis bit*/
835 #if CPU_SOCKET_TYPE == 0x10 /* L1 */
836 ClkDis0 = DTL_MemClkDis0;
837 #elif CPU_SOCKET_TYPE == 0x11 /* AM2 */
838 ClkDis0 = DTL_MemClkDis0_AM2;
839 #elif CPU_SOCKET_TYPE == 0x12 /* S1G1 */
840 ClkDis0 = DTL_MemClkDis0_S1g1;
843 dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
844 dword &= ~(ClkDis0 >> index);
845 #if QRANK_DIMM_SUPPORT == 1
847 dword &= ~(ClkDis0 >> (index+2));
850 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dword);
852 if (is_Width128) { //Channel B
853 dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
854 dword &= ~(ClkDis0 >> index);
855 #if QRANK_DIMM_SUPPORT == 1
857 dword &= ~(ClkDis0 >> (index+2));
860 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
866 /* row col bank for 64 bit
881 static void set_dimm_cs_map(const struct mem_controller *ctrl, struct dimm_size *sz, unsigned index)
883 static const uint8_t cs_map_aaa[24] = {
884 /* (bank=2, row=13, col=9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */
899 map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
900 map &= ~(0xf << (index * 4));
901 #if QRANK_DIMM_SUPPORT == 1
903 map &= ~(0xf << ( (index + 2) * 4));
907 /* Make certain side1 of the dimm is at least 128MB */
908 if (sz->per_rank >= 27) {
910 temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ];
911 map |= temp_map << (index*4);
912 #if QRANK_DIMM_SUPPORT == 1
914 map |= temp_map << ( (index + 2) * 4);
919 pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
923 static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask, struct mem_info *meminfo)
927 for(i = 0; i < DIMM_SOCKETS; i++) {
928 struct dimm_size *sz = &(meminfo->sz[i]);
929 if (!(dimm_mask & (1 << i))) {
932 spd_get_dimm_size(ctrl->channel0[i], sz);
933 if (sz->per_rank == 0) {
934 return -1; /* Report SPD error */
936 set_dimm_size(ctrl, sz, i, meminfo->is_Width128);
937 set_dimm_cs_map (ctrl, sz, i);
942 static void route_dram_accesses(const struct mem_controller *ctrl,
943 unsigned long base_k, unsigned long limit_k)
945 /* Route the addresses to the controller node */
950 unsigned limit_reg, base_reg;
953 node_id = ctrl->node_id;
954 index = (node_id << 3);
955 limit = (limit_k << 2);
958 limit |= ( 0 << 8) | (node_id << 0);
959 base = (base_k << 2);
961 base |= (0 << 8) | (1<<1) | (1<<0);
963 limit_reg = 0x44 + index;
964 base_reg = 0x40 + index;
965 for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device += PCI_DEV(0, 1, 0)) {
966 pci_write_config32(device, limit_reg, limit);
967 pci_write_config32(device, base_reg, base);
971 static void set_top_mem(unsigned tom_k, unsigned hole_startk)
973 /* Error if I don't have memory */
978 /* Report the amount of memory. */
979 print_debug("RAM: 0x");
980 print_debug_hex32(tom_k);
981 print_debug(" KB\r\n");
984 if(tom_k > (4*1024*1024)) {
985 /* Now set top of memory */
986 msr.lo = (tom_k & 0x003fffff) << 10;
987 msr.hi = (tom_k & 0xffc00000) >> 22;
988 wrmsr(TOP_MEM2, msr);
991 /* Leave a 64M hole between TOP_MEM and TOP_MEM2
992 * so I can see my rom chip and other I/O devices.
994 if (tom_k >= 0x003f0000) {
995 #if HW_MEM_HOLE_SIZEK != 0
996 if(hole_startk != 0) {
1002 msr.lo = (tom_k & 0x003fffff) << 10;
1003 msr.hi = (tom_k & 0xffc00000) >> 22;
1004 wrmsr(TOP_MEM, msr);
1007 static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, int is_Width128)
1011 static const uint8_t csbase_low_f0_shift[] = {
1012 /* 128MB */ (14 - (13-5)),
1013 /* 256MB */ (15 - (13-5)),
1014 /* 512MB */ (15 - (13-5)),
1015 /* 512MB */ (16 - (13-5)),
1016 /* 512MB */ (16 - (13-5)),
1017 /* 1GB */ (16 - (13-5)),
1018 /* 1GB */ (16 - (13-5)),
1019 /* 2GB */ (16 - (13-5)),
1020 /* 2GB */ (17 - (13-5)),
1021 /* 4GB */ (17 - (13-5)),
1022 /* 4GB */ (16 - (13-5)),
1023 /* 8GB */ (17 - (13-5)),
1026 /* cs_base_high is not changed */
1028 uint32_t csbase_inc;
1029 int chip_selects, index;
1031 unsigned common_size;
1032 unsigned common_cs_mode;
1033 uint32_t csbase, csmask;
1035 /* See if all of the memory chip selects are the same size
1036 * and if so count them.
1040 common_cs_mode = 0xff;
1041 for(index = 0; index < 8; index++) {
1046 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1048 /* Is it enabled? */
1053 size = (value >> 19) & 0x3ff;
1054 if (common_size == 0) {
1057 /* The size differed fail */
1058 if (common_size != size) {
1062 value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
1063 cs_mode =( value >> ((index>>1)*4)) & 0xf;
1064 if(common_cs_mode == 0xff) {
1065 common_cs_mode = cs_mode;
1067 /* The cs_mode differed fail */
1068 if(common_cs_mode != cs_mode) {
1073 /* Chip selects can only be interleaved when there is
1074 * more than one and their is a power of two of them.
1076 bits = log2(chip_selects);
1077 if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) { //chip_selects max = 8
1081 /* Find the bits of csbase that we need to interleave on */
1082 csbase_inc = 1 << (csbase_low_f0_shift[common_cs_mode]);
1088 /* Compute the initial values for csbase and csbask.
1089 * In csbase just set the enable bit and the base to zero.
1090 * In csmask set the mask bits for the size and page level interleave.
1093 csmask = (((common_size << bits) - 1) << 19);
1094 csmask |= 0x3fe0 & ~((csbase_inc << bits) - csbase_inc);
1095 for(index = 0; index < 8; index++) {
1098 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1099 /* Is it enabled? */
1103 pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
1104 if((index & 1) == 0) { //only have 4 CSMASK
1105 pci_write_config32(ctrl->f2, DRAM_CSMASK + ((index>>1) << 2), csmask);
1107 csbase += csbase_inc;
1110 print_debug("Interleaved\r\n");
1112 /* Return the memory size in K */
1113 return common_size << ((27-10) + bits);
1115 static unsigned long order_chip_selects(const struct mem_controller *ctrl)
1119 /* Remember which registers we have used in the high 8 bits of tom */
1122 /* Find the largest remaining canidate */
1123 unsigned index, canidate;
1124 uint32_t csbase, csmask;
1128 for(index = 0; index < 8; index++) {
1130 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1132 /* Is it enabled? */
1137 /* Is it greater? */
1138 if (value <= csbase) {
1142 /* Has it already been selected */
1143 if (tom & (1 << (index + 24))) {
1146 /* I have a new canidate */
1150 /* See if I have found a new canidate */
1155 /* Remember the dimm size */
1156 size = csbase >> 19;
1158 /* Remember I have used this register */
1159 tom |= (1 << (canidate + 24));
1161 /* Recompute the cs base register value */
1162 csbase = (tom << 19) | 1;
1164 /* Increment the top of memory */
1167 /* Compute the memory mask */
1168 csmask = ((size -1) << 19);
1169 csmask |= 0x3fe0; /* For now don't optimize */
1171 /* Write the new base register */
1172 pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
1173 /* Write the new mask register */
1174 if((canidate & 1) == 0) { //only have 4 CSMASK
1175 pci_write_config32(ctrl->f2, DRAM_CSMASK + ((canidate>>1) << 2), csmask);
1179 /* Return the memory size in K */
1180 return (tom & ~0xff000000) << (27-10);
1183 unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
1187 /* Find the last memory address used */
1189 for(node_id = 0; node_id < max_node_id; node_id++) {
1190 uint32_t limit, base;
1192 index = node_id << 3;
1193 base = pci_read_config32(ctrl->f1, 0x40 + index);
1194 /* Only look at the limit if the base is enabled */
1195 if ((base & 3) == 3) {
1196 limit = pci_read_config32(ctrl->f1, 0x44 + index);
1197 end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
1203 static void order_dimms(const struct mem_controller *ctrl, struct mem_info *meminfo)
1205 unsigned long tom_k, base_k;
1207 if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
1208 tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
1210 print_debug("Interleaving disabled\r\n");
1214 tom_k = order_chip_selects(ctrl);
1216 /* Compute the memory base address */
1217 base_k = memory_end_k(ctrl, ctrl->node_id);
1219 route_dram_accesses(ctrl, base_k, tom_k);
1220 set_top_mem(tom_k, 0);
1223 static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask, struct mem_info *meminfo)
1225 print_debug("disabling dimm");
1226 print_debug_hex8(index);
1227 print_debug("\r\n");
1228 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
1229 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
1230 #if QRANK_DIMM_SUPPORT == 1
1231 if(meminfo->sz[index].rank == 4) {
1232 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), 0);
1233 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), 0);
1237 dimm_mask &= ~(1 << index);
1241 static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long dimm_mask, struct mem_info *meminfo)
1244 uint32_t registered;
1247 for(i = 0; (i < DIMM_SOCKETS); i++) {
1249 if (!(dimm_mask & (1 << i))) {
1252 value = spd_read_byte(ctrl->channel0[i], SPD_DIMM_TYPE);
1256 /* Registered dimm ? */
1258 if ((value == SPD_DIMM_TYPE_RDIMM) || (value == SPD_DIMM_TYPE_mRDIMM)) {
1259 //check SPD_MOD_ATTRIB to verify it is SPD_MOD_ATTRIB_REGADC (0x11)?
1260 registered |= (1<<i);
1264 if (is_opteron(ctrl)) {
1266 if ( registered != (dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) {
1267 dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffed dimm
1268 // die("Mixed buffered and registered dimms not supported");
1270 //By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM
1272 die("Unbuffered Dimms not supported on Opteron");
1278 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1279 dcl &= ~DCL_UnBuffDimm;
1280 meminfo->is_registered = 1;
1282 dcl |= DCL_UnBuffDimm;
1283 meminfo->is_registered = 0;
1285 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1288 if (meminfo->is_registered) {
1289 print_debug("Registered\r\n");
1291 print_debug("Unbuffered\r\n");
1297 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
1302 for(i = 0; i < DIMM_SOCKETS; i++) {
1305 device = ctrl->channel0[i];
1307 byte = spd_read_byte(ctrl->channel0[i], SPD_MEM_TYPE); /* Type */
1308 if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
1309 dimm_mask |= (1 << i);
1312 device = ctrl->channel1[i];
1314 byte = spd_read_byte(ctrl->channel1[i], SPD_MEM_TYPE);
1315 if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
1316 dimm_mask |= (1 << (i + DIMM_SOCKETS));
1323 static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_mask, struct mem_info *meminfo)
1327 /* SPD addresses to verify are identical */
1328 static const uint8_t addresses[] = {
1329 2, /* Type should be DDR2 SDRAM */
1330 3, /* *Row addresses */
1331 4, /* *Column addresses */
1332 5, /* *Number of DIMM Ranks */
1333 6, /* *Module Data Width*/
1334 9, /* *Cycle time at highest CAS Latency CL=X */
1335 11, /* *DIMM Conf Type */
1336 13, /* *Pri SDRAM Width */
1337 17, /* *Logical Banks */
1338 18, /* *Supported CAS Latencies */
1339 20, /* *DIMM Type Info */
1340 21, /* *SDRAM Module Attributes */
1341 23, /* *Cycle time at CAS Latnecy (CLX - 1) */
1342 26, /* *Cycle time at CAS Latnecy (CLX - 2) */
1343 27, /* *tRP Row precharge time */
1344 28, /* *Minimum Row Active to Row Active Delay (tRRD) */
1345 29, /* *tRCD RAS to CAS */
1346 30, /* *tRAS Activate to Precharge */
1347 36, /* *Write recovery time (tWR) */
1348 37, /* *Internal write to read command delay (tRDP) */
1349 38, /* *Internal read to precharge commanfd delay (tRTP) */
1350 41, /* *Extension of Byte 41 tRC and Byte 42 tRFC */
1351 41, /* *Minimum Active to Active/Auto Refresh Time(Trc) */
1352 42, /* *Minimum Auto Refresh Command Time(Trfc) */
1354 /* If the dimms are not in pairs do not do dual channels */
1355 if ((dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
1356 ((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1357 goto single_channel;
1359 /* If the cpu is not capable of doing dual channels don't do dual channels */
1360 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1361 if (!(nbcap & NBCAP_128Bit)) {
1362 goto single_channel;
1364 for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
1365 unsigned device0, device1;
1368 /* If I don't have a dimm skip this one */
1369 if (!(dimm_mask & (1 << i))) {
1372 device0 = ctrl->channel0[i];
1373 device1 = ctrl->channel1[i];
1374 for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) {
1376 addr = addresses[j];
1377 value0 = spd_read_byte(device0, addr);
1381 value1 = spd_read_byte(device1, addr);
1385 if (value0 != value1) {
1386 goto single_channel;
1390 print_spew("Enabling dual channel memory\r\n");
1392 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1393 dcl &= ~DCL_BurstLength32; /* 32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses
1394 32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode */
1395 dcl |= DCL_Width128;
1396 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1397 meminfo->is_Width128 = 1;
1400 dimm_mask &= ~((1 << (DIMM_SOCKETS *2)) - (1 << DIMM_SOCKETS));
1401 meminfo->is_Width128 = 0;
1406 uint16_t cycle_time;
1407 uint8_t divisor; /* In 1/40 ns increments */
1412 uint8_t DcqByPassMax;
1413 uint32_t dch_memclk;
1417 static const struct mem_param speed[] = {
1419 .name = "200Mhz\r\n",
1420 .cycle_time = 0x500,
1421 .divisor = 200, // how many 1/40ns per clock
1422 .dch_memclk = DCH_MemClkFreq_200MHz, //0
1431 .name = "266Mhz\r\n",
1432 .cycle_time = 0x375,
1433 .divisor = 150, //????
1434 .dch_memclk = DCH_MemClkFreq_266MHz, //1
1442 .name = "333Mhz\r\n",
1443 .cycle_time = 0x300,
1445 .dch_memclk = DCH_MemClkFreq_333MHz, //2
1454 .name = "400Mhz\r\n",
1455 .cycle_time = 0x250,
1457 .dch_memclk = DCH_MemClkFreq_400MHz,//3
1465 .cycle_time = 0x000,
1469 static const struct mem_param *get_mem_param(unsigned min_cycle_time)
1472 const struct mem_param *param;
1473 for(param = &speed[0]; param->cycle_time ; param++) {
1474 if (min_cycle_time > (param+1)->cycle_time) {
1478 if (!param->cycle_time) {
1479 die("min_cycle_time to low");
1481 print_spew(param->name);
1482 #ifdef DRAM_MIN_CYCLE_TIME
1483 print_debug(param->name);
1488 static uint8_t get_exact_divisor(int i, uint8_t divisor)
1490 //input divisor could be 200(200), 150(266), 120(333), 100 (400)
1491 static const uint8_t dv_a[] = {
1492 /* 200 266 333 400 */
1493 /*4 */ 250, 250, 250, 250,
1494 /*5 */ 200, 200, 200, 100,
1495 /*6 */ 200, 166, 166, 100,
1496 /*7 */ 200, 171, 142, 100,
1498 /*8 */ 200, 150, 125, 100,
1499 /*9 */ 200, 156, 133, 100,
1500 /*10*/ 200, 160, 120, 100,
1501 /*11*/ 200, 163, 127, 100,
1503 /*12*/ 200, 150, 133, 100,
1504 /*13*/ 200, 153, 123, 100,
1505 /*14*/ 200, 157, 128, 100,
1506 /*15*/ 200, 160, 120, 100,
1513 msr = rdmsr(0xc0010042);
1514 fid_cur = msr.lo & 0x3f;
1518 if(index>12) return divisor;
1520 if(i>3) return divisor;
1522 return dv_a[index * 4+i];
1526 struct spd_set_memclk_result {
1527 const struct mem_param *param;
1531 static unsigned convert_to_linear(unsigned value)
1533 static const unsigned fraction[] = { 0x25, 0x33, 0x66, 0x75 };
1536 /* We need to convert value to more readable */
1537 if((value & 0xf) < 10) { //no .25, .33, .66, .75
1540 valuex = ((value & 0xf0) << 4) | fraction [(value & 0xf)-10];
1546 static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask, struct mem_info *meminfo)
1548 /* Compute the minimum cycle time for these dimms */
1549 struct spd_set_memclk_result result;
1550 unsigned min_cycle_time, min_latency, bios_cycle_time;
1554 static const uint8_t latency_indicies[] = { 25, 23, 9 };
1556 static const uint16_t min_cycle_times[] = { // use full speed to compare
1557 [NBCAP_MEMCLK_NOLIMIT] = 0x250, /*2.5ns */
1558 [NBCAP_MEMCLK_333MHZ] = 0x300, /* 3.0ns */
1559 [NBCAP_MEMCLK_266MHZ] = 0x375, /* 3.75ns */
1560 [NBCAP_MEMCLK_200MHZ] = 0x500, /* 5.0s */
1564 value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1565 min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
1566 bios_cycle_time = min_cycle_times[
1567 read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
1568 if (bios_cycle_time > min_cycle_time) {
1569 min_cycle_time = bios_cycle_time;
1573 print_tx("1 min_cycle_time:", min_cycle_time);
1575 /* Compute the least latency with the fastest clock supported
1576 * by both the memory controller and the dimms.
1578 for(i = 0; i < DIMM_SOCKETS; i++) {
1579 int new_cycle_time, new_latency;
1584 if (!(dimm_mask & (1 << i))) {
1588 /* First find the supported CAS latencies
1589 * Byte 18 for DDR SDRAM is interpreted:
1590 * bit 3 == CAS Latency = 3
1591 * bit 4 == CAS Latency = 4
1592 * bit 5 == CAS Latency = 5
1593 * bit 6 == CAS Latency = 6
1595 new_cycle_time = 0x500;
1598 latencies = spd_read_byte(ctrl->channel0[i], SPD_CAS_LAT);
1599 if (latencies <= 0) continue;
1602 print_tx("\tlatencies:", latencies);
1603 /* Compute the lowest cas latency supported */
1604 latency = log2(latencies) - 2;
1606 /* Loop through and find a fast clock with a low latency */
1607 for(index = 0; index < 3; index++, latency++) {
1609 if ((latency < 3) || (latency > 6) ||
1610 (!(latencies & (1 << latency)))) {
1613 value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
1617 print_tx("\tindex:", index);
1618 print_tx("\t\tlatency:", latency);
1619 print_tx("\t\tvalue1:", value);
1621 value = convert_to_linear(value);
1623 print_tx("\t\tvalue2:", value);
1625 /* Only increase the latency if we decreas the clock */
1626 if (value >= min_cycle_time ) {
1627 if(value < new_cycle_time) {
1628 new_cycle_time = value;
1629 new_latency = latency;
1630 } else if (value == new_cycle_time) {
1631 if(new_latency > latency) {
1632 new_latency = latency;
1636 print_tx("\t\tnew_cycle_time:", new_cycle_time);
1637 print_tx("\t\tnew_latency:", new_latency);
1640 if (new_latency > 6){
1643 /* Does min_latency need to be increased? */
1644 if (new_cycle_time > min_cycle_time) {
1645 min_cycle_time = new_cycle_time;
1647 /* Does min_cycle_time need to be increased? */
1648 if (new_latency > min_latency) {
1649 min_latency = new_latency;
1652 print_tx("2 min_cycle_time:", min_cycle_time);
1653 print_tx("2 min_latency:", min_latency);
1655 /* Make a second pass through the dimms and disable
1656 * any that cannot support the selected memclk and cas latency.
1659 print_tx("3 min_cycle_time:", min_cycle_time);
1660 print_tx("3 min_latency:", min_latency);
1662 for(i = 0; (i < DIMM_SOCKETS) && (ctrl->channel0[i]); i++) {
1667 if (!(dimm_mask & (1 << i))) {
1670 latencies = spd_read_byte(ctrl->channel0[i], SPD_CAS_LAT);
1671 if (latencies < 0) goto hw_error;
1672 if (latencies == 0) {
1676 /* Compute the lowest cas latency supported */
1677 latency = log2(latencies) -2;
1679 /* Walk through searching for the selected latency */
1680 for(index = 0; index < 3; index++, latency++) {
1681 if (!(latencies & (1 << latency))) {
1684 if (latency == min_latency)
1687 /* If I can't find the latency or my index is bad error */
1688 if ((latency != min_latency) || (index >= 3)) {
1692 /* Read the min_cycle_time for this latency */
1693 value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
1694 if (value < 0) goto hw_error;
1696 value = convert_to_linear(value);
1697 /* All is good if the selected clock speed
1698 * is what I need or slower.
1700 if (value <= min_cycle_time) {
1703 /* Otherwise I have an error, disable the dimm */
1705 dimm_mask = disable_dimm(ctrl, i, dimm_mask, meminfo);
1708 print_tx("4 min_cycle_time:", min_cycle_time);
1710 /* Now that I know the minimum cycle time lookup the memory parameters */
1711 result.param = get_mem_param(min_cycle_time);
1713 /* Update DRAM Config High with our selected memory speed */
1714 value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
1715 value &= ~(DCH_MemClkFreq_MASK << DCH_MemClkFreq_SHIFT);
1717 value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT;
1718 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
1720 print_debug(result.param->name);
1722 /* Update DRAM Timing Low with our selected cas latency */
1723 value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1724 value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
1725 value |= (min_latency - DTL_TCL_BASE) << DTL_TCL_SHIFT;
1726 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
1728 result.dimm_mask = dimm_mask;
1731 result.param = (const struct mem_param *)0;
1732 result.dimm_mask = -1;
1736 static unsigned convert_to_1_4(unsigned value)
1738 static const uint8_t fraction[] = { 0, 1, 2, 2, 3, 3, 0 };
1741 /* We need to convert value to more readable */
1742 valuex = fraction [value & 0x7];
1745 static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
1747 unsigned clocks, old_clocks;
1751 value = spd_read_byte(ctrl->channel0[i], SPD_TRC);
1752 if (value < 0) return -1;
1754 value2 = spd_read_byte(ctrl->channel0[i], SPD_TRC -1);
1756 value += convert_to_1_4(value2>>4);
1760 clocks = (value + param->divisor - 1)/param->divisor;
1762 if (clocks < DTL_TRC_MIN) {
1763 clocks = DTL_TRC_MIN;
1765 if (clocks > DTL_TRC_MAX) {
1769 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1770 old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
1771 if (old_clocks >= clocks) { //?? someone did it
1772 // clocks = old_clocks;
1775 dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
1776 dtl |= ((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
1777 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
1781 static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i, struct mem_info *meminfo)
1783 unsigned clocks, old_clocks;
1787 //get the cs_size --> logic dimm size
1788 value = spd_read_byte(ctrl->channel0[i], SPD_PRI_WIDTH);
1793 value = 6 - log2(value); //4-->4, 8-->3, 16-->2
1795 clocks = meminfo->sz[i].per_rank - 27 + 2 - value;
1797 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
1799 old_clocks = ((dth >> (DTH_TRFC0_SHIFT+i*3)) & DTH_TRFC_MASK);
1800 if (old_clocks >= clocks) { // some one did it?
1803 dth &= ~(DTH_TRFC_MASK << (DTH_TRFC0_SHIFT+i*3));
1804 dth |= clocks << (DTH_TRFC0_SHIFT+i*3);
1805 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
1809 static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct mem_param *param, int i,
1811 unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX )
1813 unsigned clocks, old_clocks;
1816 value = spd_read_byte(ctrl->channel0[i], SPD_TT); //already in 1/4 ns
1817 if (value < 0) return -1;
1819 clocks = (value + param->divisor -1)/param->divisor;
1820 if (clocks < TT_MIN) {
1823 if (clocks > TT_MAX) {
1826 dtl = pci_read_config32(ctrl->f2, TT_REG);
1828 old_clocks = ((dtl >> TT_SHIFT) & TT_MASK) + TT_BASE;
1829 if (old_clocks >= clocks) { //some one did it?
1830 // clocks = old_clocks;
1833 dtl &= ~(TT_MASK << TT_SHIFT);
1834 dtl |= ((clocks - TT_BASE) << TT_SHIFT);
1835 pci_write_config32(ctrl->f2, TT_REG, dtl);
1839 static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
1841 return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TRCD, DTL_TRCD_SHIFT, DTL_TRCD_MASK, DTL_TRCD_BASE, DTL_TRCD_MIN, DTL_TRCD_MAX);
1844 static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
1846 return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TRRD, DTL_TRRD_SHIFT, DTL_TRRD_MASK, DTL_TRRD_BASE, DTL_TRRD_MIN, DTL_TRRD_MAX);
1849 static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i)
1851 unsigned clocks, old_clocks;
1854 value = spd_read_byte(ctrl->channel0[i], SPD_TRAS); //in 1 ns
1855 if (value < 0) return -1;
1856 print_tx("update_dimm_Tras: 0 value=", value);
1858 value<<=2; //convert it to in 1/4ns
1861 print_tx("update_dimm_Tras: 1 value=", value);
1863 clocks = (value + param->divisor - 1)/param->divisor;
1864 print_tx("update_dimm_Tras: divisor=", param->divisor);
1865 print_tx("update_dimm_Tras: clocks=", clocks);
1866 if (clocks < DTL_TRAS_MIN) {
1867 clocks = DTL_TRAS_MIN;
1869 if (clocks > DTL_TRAS_MAX) {
1872 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1873 old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
1874 if (old_clocks >= clocks) { // someone did it?
1877 dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
1878 dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
1879 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
1883 static int update_dimm_Trp(const struct mem_controller *ctrl, const struct mem_param *param, int i)
1885 return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TRP, DTL_TRP_SHIFT, DTL_TRP_MASK, DTL_TRP_BASE, DTL_TRP_MIN, DTL_TRP_MAX);
1888 static int update_dimm_Trtp(const struct mem_controller *ctrl, const struct mem_param *param, int i, struct mem_info *meminfo)
1890 //need to figure if it is 32 byte burst or 64 bytes burst
1892 if(!meminfo->is_Width128) {
1894 dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1895 if((dword & DCL_BurstLength32)) offset = 0;
1897 return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TRTP, DTL_TRTP_SHIFT, DTL_TRTP_MASK, DTL_TRTP_BASE+offset, DTL_TRTP_MIN+offset, DTL_TRTP_MAX+offset);
1901 static int update_dimm_Twr(const struct mem_controller *ctrl, const struct mem_param *param, int i)
1903 return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TWR, DTL_TWR_SHIFT, DTL_TWR_MASK, DTL_TWR_BASE, DTL_TWR_MIN, DTL_TWR_MAX);
1907 static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i)
1909 uint32_t dth, dth_old;
1911 value = spd_read_byte(ctrl->channel0[i], SPD_TREF); // 0: 15.625us, 1: 3.9us 2: 7.8 us....
1912 if (value < 0) return -1;
1920 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
1923 dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
1924 dth |= (value << DTH_TREF_SHIFT);
1925 if(dth_old != dth) {
1926 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
1931 static void set_4RankRDimm(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
1933 #if QRANK_DIMM_SUPPRT == 1
1938 if(!(meminfo->is_registered)) return;
1942 for(i = 0; i < DIMM_SOCKETS; i++) {
1943 if (!(dimm_mask & (1 << i))) {
1947 if(meminfo->sz.rank == 4) {
1955 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
1956 dch |= DCH_FourRankRDimm;
1957 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
1963 static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, struct mem_info *meminfo)
1969 uint32_t mask_single_rank;
1970 uint32_t mask_page_1k;
1972 #if QRANK_DIMM_SUPPORT == 1
1976 long dimm_mask = meminfo->dimm_mask;
1981 mask_single_rank = 0;
1984 for(i = 0; i < DIMM_SOCKETS; i++) {
1986 if (!(dimm_mask & (1 << i))) {
1990 if(meminfo->sz[i].rank == 1) {
1991 mask_single_rank |= 1<<i;
1994 if(meminfo->sz[i].col==10) {
1995 mask_page_1k |= 1<<i;
1999 value = spd_read_byte(ctrl->channel0[i], SPD_PRI_WIDTH);
2001 #if QRANK_DIMM_SUPPORT == 1
2002 rank = meminfo->sz[i].rank;
2007 #if QRANK_DIMM_SUPPORT == 1
2009 mask_x4 |= 1<<(i+2);
2012 } else if(value==16) {
2014 #if QRANK_DIMM_SUPPORT == 1
2016 mask_x16 |= 1<<(i+2);
2023 meminfo->x4_mask= mask_x4;
2024 meminfo->x16_mask = mask_x16;
2026 meminfo->single_rank_mask = mask_single_rank;
2027 meminfo->page_1k_mask = mask_page_1k;
2034 static void set_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2037 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2038 dcl &= ~(DCL_X4Dimm_MASK<<DCL_X4Dimm_SHIFT);
2039 dcl |= ((meminfo->x4_mask) & 0xf) << (DCL_X4Dimm_SHIFT);
2040 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2043 static int count_ones(uint32_t dimm_mask)
2048 for(index = 0; index < DIMM_SOCKETS; index++, dimm_mask>>=1) {
2049 if (dimm_mask & 1) {
2057 static void set_DramTerm(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2063 if(param->divisor == 100) { //DDR2 800
2064 if(meminfo->is_Width128) {
2065 if(count_ones(meminfo->dimm_mask & 0x0f)==2) {
2073 #if DIMM_SUPPORT == 0x0204
2074 odt = 0x2; /* 150 ohms */
2077 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2078 dcl &= ~(DCL_DramTerm_MASK<<DCL_DramTerm_SHIFT);
2079 dcl |= (odt & DCL_DramTerm_MASK) << (DCL_DramTerm_SHIFT);
2080 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2084 static void set_ecc(const struct mem_controller *ctrl,const struct mem_param *param, long dimm_mask, struct mem_info *meminfo)
2089 uint32_t dcl, nbcap;
2090 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
2091 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2092 dcl &= ~DCL_DimmEccEn;
2093 if (nbcap & NBCAP_ECC) {
2094 dcl |= DCL_DimmEccEn;
2096 if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
2097 dcl &= ~DCL_DimmEccEn;
2099 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2101 meminfo->is_ecc = 1;
2102 if(!(dcl & DCL_DimmEccEn)) {
2103 meminfo->is_ecc = 0;
2104 return; // already disabled the ECC, so don't need to read SPD any more
2107 for(i = 0; i < DIMM_SOCKETS; i++) {
2109 if (!(dimm_mask & (1 << i))) {
2113 value = spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONF_TYPE);
2115 if(!(value & SPD_DIMM_CONF_TYPE_ECC)) {
2116 dcl &= ~DCL_DimmEccEn;
2117 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2118 meminfo->is_ecc = 0;
2125 static int update_dimm_Twtr(const struct mem_controller *ctrl, const struct mem_param *param, int i)
2128 return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_HIGH, SPD_TWTR, DTH_TWTR_SHIFT, DTH_TWTR_MASK, DTH_TWTR_BASE, DTH_TWTR_MIN, DTH_TWTR_MAX);
2132 static void set_TT(const struct mem_controller *ctrl, const struct mem_param *param, unsigned TT_REG,
2133 unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX, unsigned val, const char *str)
2137 if ((val < TT_MIN) || (val > TT_MAX)) {
2139 die(" Unknown\r\n");
2142 reg = pci_read_config32(ctrl->f2, TT_REG);
2143 reg &= ~(TT_MASK << TT_SHIFT);
2144 reg |= ((val - TT_BASE) << TT_SHIFT);
2145 pci_write_config32(ctrl->f2, TT_REG, reg);
2149 static void set_TrwtTO(const struct mem_controller *ctrl, const struct mem_param *param)
2151 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRWTTO_SHIFT, DTH_TRWTTO_MASK,DTH_TRWTTO_BASE, DTH_TRWTTO_MIN, DTH_TRWTTO_MAX, param->TrwtTO, "TrwtTO");
2154 static void set_Twrrd(const struct mem_controller *ctrl, const struct mem_param *param)
2156 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRRD_SHIFT, DTH_TWRRD_MASK,DTH_TWRRD_BASE, DTH_TWRRD_MIN, DTH_TWRRD_MAX, param->Twrrd, "Twrrd");
2159 static void set_Twrwr(const struct mem_controller *ctrl, const struct mem_param *param)
2161 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRWR_SHIFT, DTH_TWRWR_MASK,DTH_TWRWR_BASE, DTH_TWRWR_MIN, DTH_TWRWR_MAX, param->Twrwr, "Twrwr");
2164 static void set_Trdrd(const struct mem_controller *ctrl, const struct mem_param *param)
2166 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRDRD_SHIFT, DTH_TRDRD_MASK,DTH_TRDRD_BASE, DTH_TRDRD_MIN, DTH_TRDRD_MAX, param->Trdrd, "Trdrd");
2169 static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem_param *param)
2171 set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS
2174 static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2176 static const uint8_t faw_1k[] = {8, 10, 13, 14};
2177 static const uint8_t faw_2k[] = {10, 14, 17, 18};
2178 unsigned memclkfreq_index;
2182 memclkfreq_index = param->dch_memclk;
2184 if(meminfo->page_1k_mask != 0) { //1k page
2185 faw = faw_1k[memclkfreq_index];
2188 faw = faw_2k[memclkfreq_index];
2191 set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_FourActWindow_SHIFT, DCH_FourActWindow_MASK, DCH_FourActWindow_BASE, DCH_FourActWindow_MIN, DCH_FourActWindow_MAX, faw, "FourActWindow");
2196 static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
2202 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2203 dch &= ~(DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT);
2205 //FIXME: We need to use Max of DqsRcvEnDelay + 6ns here: After trainning and get that from index reg 0x10, 0x13, 0x16, 0x19, 0x30, 0x33, 0x36, 0x39
2209 dch |= ((async_lat - DCH_MaxAsyncLat_BASE) << DCH_MaxAsyncLat_SHIFT);
2210 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2213 static void set_SlowAccessMode(const struct mem_controller *ctrl)
2217 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2221 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2226 DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20
2227 DRAM_ADDR_TIMING_CTRL 04, 0x24
2229 static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *meminfo)
2233 unsigned SlowAccessMode = 0;
2235 long dimm_mask = meminfo->dimm_mask & 0x0f;
2237 #if DIMM_SUPPORT==0x0104 /* DDR2 and REG */
2240 dwordx = 0x002f0000;
2241 switch (meminfo->memclk_set) {
2242 case DCH_MemClkFreq_266MHz:
2243 if( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
2244 dwordx = 0x002f2700;
2247 case DCH_MemClkFreq_333MHz:
2248 if( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
2249 if ((meminfo->single_rank_mask & 0x03)!=0x03) { //any double rank there?
2250 dwordx = 0x002f2f00;
2254 case DCH_MemClkFreq_400MHz:
2255 dwordx = 0x002f3300;
2261 #if DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */
2263 dwordx = 0x002F2F00;
2265 switch (meminfo->memclk_set) {
2266 case DCH_MemClkFreq_200MHz: /* nothing to be set here */
2268 case DCH_MemClkFreq_266MHz:
2269 if ((meminfo->single_rank_mask == 0)
2270 && (meminfo->x4_mask == 0) && (meminfo->x16_mask))
2271 dwordx = 0x002C2C00; /* Double rank x8 */
2272 /* else SRx16, SRx8, DRx16 == 0x002F2F00 */
2274 case DCH_MemClkFreq_333MHz:
2275 if ((meminfo->single_rank_mask == 1)
2276 && (meminfo->x16_mask == 1)) /* SR x16 */
2277 dwordx = 0x00272700;
2278 else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
2279 && (meminfo->single_rank_mask == 0)) { /* DR x8 */
2281 dwordx = 0x00002800;
2282 } else { /* SR x8, DR x16 */
2283 dwordx = 0x002A2A00;
2286 case DCH_MemClkFreq_400MHz:
2287 if ((meminfo->single_rank_mask == 1)
2288 && (meminfo->x16_mask == 1)) /* SR x16 */
2289 dwordx = 0x00292900;
2290 else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
2291 && (meminfo->single_rank_mask == 0)) { /* DR x8 */
2293 dwordx = 0x00002A00;
2294 } else { /* SR x8, DR x16 */
2295 dwordx = 0x002A2A00;
2301 #if DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */
2302 /* for UNBUF DIMM */
2304 dwordx = 0x002f2f00;
2305 switch (meminfo->memclk_set) {
2306 case DCH_MemClkFreq_200MHz:
2307 if(dimm_mask == 0x03) {
2312 case DCH_MemClkFreq_266MHz:
2313 if(dimm_mask == 0x03) {
2316 if((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
2317 switch (meminfo->single_rank_mask) {
2319 dwordx = 0x00002f00; //x8 single Rank
2322 dwordx = 0x00342f00; //x8 double Rank
2325 dwordx = 0x00372f00; //x8 single Rank and double Rank mixed
2327 } else if((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
2328 dwordx = 0x00382f00; //x8 Double Rank and x16 single Rank mixed
2329 } else if((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
2330 dwordx = 0x00382f00; //x16 single Rank and x8 double Rank mixed
2335 if((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank
2336 dwordx = 0x002f2f00;
2338 dwordx = 0x002b2f00;
2342 case DCH_MemClkFreq_333MHz:
2343 dwordx = 0x00202220;
2344 if(dimm_mask == 0x03) {
2347 if((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
2348 switch (meminfo->single_rank_mask) {
2350 dwordx = 0x00302220; //x8 single Rank
2353 dwordx = 0x002b2220; //x8 double Rank
2356 dwordx = 0x002a2220; //x8 single Rank and double Rank mixed
2358 } else if((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
2359 dwordx = 0x002c2220; //x8 Double Rank and x16 single Rank mixed
2360 } else if((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
2361 dwordx = 0x002c2220; //x16 single Rank and x8 double Rank mixed
2365 case DCH_MemClkFreq_400MHz:
2366 dwordx = 0x00202520;
2368 if(dimm_mask == 0x03) {
2376 print_raminit("\tdimm_mask = ", meminfo->dimm_mask);
2377 print_raminit("\tx4_mask = ", meminfo->x4_mask);
2378 print_raminit("\tx16_mask = ", meminfo->x16_mask);
2379 print_raminit("\tsingle_rank_mask = ", meminfo->single_rank_mask);
2380 print_raminit("\tODC = ", dword);
2381 print_raminit("\tAddr Timing= ", dwordx);
2384 #if (DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
2385 if(SlowAccessMode) {
2386 set_SlowAccessMode(ctrl);
2390 /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */
2391 pci_write_config32_index_wait(ctrl->f2, 0x98, 0, dword);
2392 if(meminfo->is_Width128) {
2393 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword);
2396 /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */
2397 pci_write_config32_index_wait(ctrl->f2, 0x98, 4, dwordx);
2398 if(meminfo->is_Width128) {
2399 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx);
2405 static void set_RDqsEn(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2407 #if CPU_SOCKET_TYPE==0x10
2408 //only need to set for reg and x8
2411 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2414 if((!meminfo->x4_mask) && (!meminfo->x16_mask)) {
2418 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2423 static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param)
2426 /* AMD says to Hardcode this */
2427 dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
2428 dcm &= ~(DCM_ILD_lmt_MASK << DCM_ILD_lmt_SHIFT);
2429 dcm |= DCM_ILD_lmt_16 << DCM_ILD_lmt_SHIFT;
2431 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
2434 static void set_RdWrQByp(const struct mem_controller *ctrl, const struct mem_param *param)
2436 set_TT(ctrl, param, DRAM_CTRL_MISC, DCM_RdWrQByp_SHIFT, DCM_RdWrQByp_MASK,0, 0, 3, 2, "RdWrQByp");
2441 static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask, struct mem_info *meminfo)
2445 for(i = 0; i < DIMM_SOCKETS; i++) {
2447 if (!(dimm_mask & (1 << i))) {
2450 print_tx("dimm socket: ", i);
2451 /* DRAM Timing Low Register */
2452 print_t("\ttrc\r\n");
2453 if ((rc = update_dimm_Trc (ctrl, param, i)) <= 0) goto dimm_err;
2455 print_t("\ttrcd\r\n");
2456 if ((rc = update_dimm_Trcd(ctrl, param, i)) <= 0) goto dimm_err;
2458 print_t("\ttrrd\r\n");
2459 if ((rc = update_dimm_Trrd(ctrl, param, i)) <= 0) goto dimm_err;
2461 print_t("\ttras\r\n");
2462 if ((rc = update_dimm_Tras(ctrl, param, i)) <= 0) goto dimm_err;
2464 print_t("\ttrp\r\n");
2465 if ((rc = update_dimm_Trp (ctrl, param, i)) <= 0) goto dimm_err;
2467 print_t("\ttrtp\r\n");
2468 if ((rc = update_dimm_Trtp(ctrl, param, i, meminfo)) <= 0) goto dimm_err;
2470 print_t("\ttwr\r\n");
2471 if ((rc = update_dimm_Twr (ctrl, param, i)) <= 0) goto dimm_err;
2473 /* DRAM Timing High Register */
2474 print_t("\ttref\r\n");
2475 if ((rc = update_dimm_Tref(ctrl, param, i)) <= 0) goto dimm_err;
2477 print_t("\ttwtr\r\n");
2478 if ((rc = update_dimm_Twtr(ctrl, param, i)) <= 0) goto dimm_err;
2480 print_t("\ttrfc\r\n");
2481 if ((rc = update_dimm_Trfc(ctrl, param, i, meminfo)) <= 0) goto dimm_err;
2483 /* DRAM Config Low */
2490 dimm_mask = disable_dimm(ctrl, i, dimm_mask, meminfo);
2493 meminfo->dimm_mask = dimm_mask; // store final dimm_mask
2495 get_extra_dimm_mask(ctrl, meminfo); // will be used by RDqsEn and dimm_x4
2496 /* DRAM Timing Low Register */
2498 /* DRAM Timing High Register */
2499 set_TrwtTO(ctrl, param);
2500 set_Twrrd (ctrl, param);
2501 set_Twrwr (ctrl, param);
2502 set_Trdrd (ctrl, param);
2504 set_4RankRDimm(ctrl, param, meminfo);
2506 /* DRAM Config High */
2507 set_Tfaw(ctrl, param, meminfo);
2508 set_DcqBypassMax(ctrl, param);
2509 set_max_async_latency(ctrl, param);
2510 set_RDqsEn(ctrl, param, meminfo);
2512 /* DRAM Config Low */
2513 set_ecc(ctrl, param, dimm_mask, meminfo);
2514 set_dimm_x4(ctrl, param, meminfo);
2515 set_DramTerm(ctrl, param, meminfo);
2517 /* DRAM Control Misc */
2518 set_idle_cycle_limit(ctrl, param);
2519 set_RdWrQByp(ctrl, param);
2524 static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
2526 struct spd_set_memclk_result result;
2527 const struct mem_param *param;
2528 struct mem_param paramx;
2529 struct mem_info *meminfo;
2532 if (!sysinfo->ctrl_present[ctrl->node_id]) {
2536 meminfo = &sysinfo->meminfo[ctrl->node_id];
2538 print_debug_addr("sdram_set_spd_registers: paramx :", ¶mx);
2540 activate_spd_rom(ctrl);
2541 dimm_mask = spd_detect_dimms(ctrl);
2542 if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
2543 print_debug("No memory for this cpu\r\n");
2546 dimm_mask = spd_enable_2channels(ctrl, dimm_mask, meminfo);
2549 dimm_mask = spd_set_ram_size(ctrl , dimm_mask, meminfo);
2552 dimm_mask = spd_handle_unbuffered_dimms(ctrl, dimm_mask, meminfo);
2555 result = spd_set_memclk(ctrl, dimm_mask, meminfo);
2556 param = result.param;
2557 dimm_mask = result.dimm_mask;
2561 //store memclk set to sysinfo, incase we need rebuilt param again
2562 meminfo->memclk_set = param->dch_memclk;
2564 memcpy(¶mx, param, sizeof(paramx));
2566 paramx.divisor = get_exact_divisor(param->dch_memclk, paramx.divisor);
2568 dimm_mask = spd_set_dram_timing(ctrl, ¶mx , dimm_mask, meminfo); // dimm_mask will be stored to meminfo->dimm_mask
2572 order_dimms(ctrl, meminfo);
2576 /* Unrecoverable error reading SPD data */
2577 print_err("SPD error - reset\r\n");
2582 #define TIMEOUT_LOOPS 300000
2584 #include "raminit_f_dqs.c"
2586 #if HW_MEM_HOLE_SIZEK != 0
2587 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i)
2590 uint32_t carry_over;
2592 uint32_t base, limit;
2597 carry_over = (4*1024*1024) - hole_startk;
2599 for(ii=controllers - 1;ii>i;ii--) {
2600 base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
2601 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2604 limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
2605 limit += (carry_over << 2 );
2606 base += (carry_over << 2 );
2607 for(j = 0; j < controllers; j++) {
2608 pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit);
2609 pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base );
2612 limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
2613 limit += (carry_over << 2);
2614 for(j = 0; j < controllers; j++) {
2615 pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit);
2618 base = pci_read_config32(dev, 0x40 + (i << 3));
2619 basek = (base & 0xffff0000) >> 2;
2620 if(basek == hole_startk) {
2621 //don't need set memhole here, because hole off set will be 0, overflow
2622 //so need to change base reg instead, new basek will be 4*1024*1024
2624 base |= (4*1024*1024)<<2;
2625 for(j = 0; j < controllers; j++) {
2626 pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
2631 hoist = /* hole start address */
2632 ((hole_startk << 10) & 0xff000000) +
2633 /* hole address to memory controller address */
2634 (((basek + carry_over) >> 6) & 0x0000ff00) +
2637 pci_write_config32(dev, 0xf0, hoist);
2643 static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
2646 uint32_t hole_startk;
2649 hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
2651 #if HW_MEM_HOLE_SIZE_AUTO_INC == 1
2652 //We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some
2654 for(i=0; i<controllers; i++) {
2657 base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
2658 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2661 base_k = (base & 0xffff0000) >> 2;
2662 if(base_k == hole_startk) {
2663 hole_startk -= (base_k - basek_pri)>>1; // decrease mem hole startk to make sure it is on middle of previous node
2664 break; //only one hole
2669 //find node index that need do set hole
2670 for(i=0; i<controllers; i++) {
2671 uint32_t base, limit;
2672 unsigned base_k, limit_k;
2673 base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
2674 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2677 limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
2678 base_k = (base & 0xffff0000) >> 2;
2679 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
2680 if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
2682 hoist_memory(controllers, ctrl, hole_startk, i);
2683 end_k = memory_end_k(ctrl, controllers);
2684 set_top_mem(end_k, hole_startk);
2685 break; //only one hole
2693 static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo)
2698 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
2699 unsigned cpu_f0_f1[8];
2700 /* FIXME: How about 32 node machine later? */
2703 print_debug_addr("sdram_enable: tsc0[8]: ", &tsc0[0]);
2707 /* Error if I don't have memory */
2708 if (memory_end_k(ctrl, controllers) == 0) {
2709 die("No memory\r\n");
2712 /* Before enabling memory start the memory clocks */
2713 for(i = 0; i < controllers; i++) {
2715 if (!sysinfo->ctrl_present[ i ])
2717 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
2719 // if no memory installed, disabled the interface
2720 if(sysinfo->meminfo[i].dimm_mask==0x00){
2721 dch |= DCH_DisDramInterface;
2722 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
2726 dch |= DCH_MemClkFreqVal;
2727 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
2728 /* address timing and Output driver comp Control */
2729 set_misc_timing(ctrl+i, sysinfo->meminfo+i );
2733 /* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */
2734 memreset(controllers, ctrl);
2736 print_debug("prepare to InitDram:");
2737 for(i=0; i<10; i++) {
2738 print_debug_hex32(i);
2739 print_debug("\b\b\b\b\b\b\b\b");
2741 print_debug("\r\n");
2744 for(i = 0; i < controllers; i++) {
2746 if (!sysinfo->ctrl_present[ i ])
2748 /* Skip everything if I don't have any memory on this controller */
2749 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
2750 if (!(dch & DCH_MemClkFreqVal)) {
2755 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
2756 if (dcl & DCL_DimmEccEn) {
2758 print_spew("ECC enabled\r\n");
2759 mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
2761 if (dcl & DCL_Width128) {
2762 mnc |= MNC_CHIPKILL_EN;
2764 pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
2767 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
2768 cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i);
2770 //Rev F0/F1 workaround
2772 /* Set the DqsRcvEnTrain bit */
2773 dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
2774 dword |= DC_DqsRcvEnTrain;
2775 pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
2782 /* Set the DqsRcvEnTrain bit */
2783 dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
2784 dword |= DC_DqsRcvEnTrain;
2785 pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
2788 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
2789 dcl |= DCL_InitDram;
2790 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
2794 for(i = 0; i < controllers; i++) {
2795 uint32_t dcl, dch, dcm;
2796 if (!sysinfo->ctrl_present[ i ])
2798 /* Skip everything if I don't have any memory on this controller */
2799 if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
2801 print_debug("Initializing memory: ");
2804 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
2806 if ((loops & 1023) == 0) {
2809 } while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS));
2810 if (loops >= TIMEOUT_LOOPS) {
2811 print_debug(" failed\r\n");
2815 /* Wait until it is safe to touch memory */
2817 dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
2818 } while(((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ );
2820 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
2824 print_debug_dqs_tsc("\r\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
2825 print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2);
2827 if(tsc.lo<tsc0[i].lo) {
2830 tsc.lo -= tsc0[i].lo;
2831 tsc.hi -= tsc0[i].hi;
2833 tsc0[i].lo = tsc.lo;
2834 tsc0[i].hi = tsc.hi;
2836 print_debug_dqs_tsc(" dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
2839 print_debug(" done\r\n");
2842 #if HW_MEM_HOLE_SIZEK != 0
2843 // init hw mem hole here
2844 /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
2845 set_hw_mem_hole(controllers, ctrl);
2848 //store tom to sysinfo, and it will be used by dqs_timing
2852 msr = rdmsr(TOP_MEM);
2853 sysinfo->tom_k = ((msr.hi<<24) | (msr.lo>>8))>>2;
2856 msr = rdmsr(TOP_MEM2);
2857 sysinfo->tom2_k = ((msr.hi<<24)| (msr.lo>>8))>>2;
2860 for(i = 0; i < controllers; i++) {
2861 sysinfo->mem_trained[i] = 0;
2863 if (!sysinfo->ctrl_present[ i ])
2866 /* Skip everything if I don't have any memory on this controller */
2867 if(sysinfo->meminfo[i].dimm_mask==0x00)
2870 sysinfo->mem_trained[i] = 0x80; // mem need to be trained
2874 #if MEM_TRAIN_SEQ == 0
2875 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
2876 dqs_timing(controllers, ctrl, tsc0, sysinfo);
2878 dqs_timing(controllers, ctrl, sysinfo);
2882 #if MEM_TRAIN_SEQ == 2
2883 //need to enable mtrr, so dqs training could access the test address
2884 setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
2887 for(i = 0; i < controllers; i++) {
2888 /* Skip everything if I don't have any memory on this controller */
2889 if(sysinfo->mem_trained[i]!=0x80)
2892 dqs_timing(i, &ctrl[i], sysinfo, 1);
2894 #if MEM_TRAIN_SEQ == 1
2895 break; // only train the first node with ram
2899 #if MEM_TRAIN_SEQ == 2
2900 clear_mtrr_dqs(sysinfo->tom2_k);
2905 #if MEM_TRAIN_SEQ != 1
2906 wait_all_core0_mem_trained(sysinfo);
2910 static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr)
2914 struct mem_controller *ctrl;
2915 for(i=0;i<controllers; i++) {
2918 ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
2919 ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
2920 ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
2921 ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
2923 if(spd_addr == (void *)0) continue;
2925 for(j=0;j<DIMM_SOCKETS;j++) {
2926 ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
2927 ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];