2 * This file is part of the coreboot project.
4 * Copyright (C) 2002 Linux Networx
5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
6 * Copyright (C) 2004 YingHai Lu
7 * Copyright (C) 2008 Advanced Micro Devices, Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <cpu/x86/mem.h>
24 #include <cpu/x86/cache.h>
25 #include <cpu/x86/mtrr.h>
26 #include <cpu/x86/tsc.h>
33 #ifndef QRANK_DIMM_SUPPORT
34 #define QRANK_DIMM_SUPPORT 0
37 #if CONFIG_USE_PRINTK_IN_CAR
39 #error This file needs CONFIG_USE_PRINTK_IN_CAR
42 #define RAM_TIMING_DEBUG 0
44 #if RAM_TIMING_DEBUG == 1
45 #define printk_raminit printk_debug
47 #define printk_raminit(fmt, arg...)
51 #if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
52 # error "CONFIG_LB_MEM_TOPK must be a power of 2"
55 #include "amdk8_f_pci.c"
58 /* for PCI_ADDR(0, 0x18, 2, 0x98) index,
59 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
62 [29: 0] DctOffset (Dram Controller Offset)
63 [30:30] DctAccessWrite (Dram Controller Read/Write Select)
66 [31:31] DctAccessDone (Dram Controller Access Done)
67 0 = Access in progress
68 1 = No access is progress
71 [31: 0] DctOffsetData (Dram Controller Offset Data)
74 - Write the register num to DctOffset with
76 - poll the DctAccessDone until it = 1
77 - Read the data from DctOffsetData
79 - Write the data to DctOffsetData
80 - Write register num to DctOffset with DctAccessWrite = 1
81 - poll the DctAccessDone untio it = 1
85 static void setup_resource_map(const unsigned int *register_values, int max)
88 for (i = 0; i < max; i += 3) {
92 dev = register_values[i] & ~0xff;
93 where = register_values[i] & 0xff;
94 reg = pci_read_config32(dev, where);
95 reg &= register_values[i+1];
96 reg |= register_values[i+2];
97 pci_write_config32(dev, where, reg);
101 static int controller_present(const struct mem_controller *ctrl)
103 return pci_read_config32(ctrl->f0, 0) == 0x11001022;
106 static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
108 static const unsigned int register_values[] = {
110 /* Careful set limit registers before base registers which
111 contain the enables */
112 /* DRAM Limit i Registers
121 * [ 2: 0] Destination Node ID
131 * [10: 8] Interleave select
132 * specifies the values of A[14:12] to use with interleave enable.
134 * [31:16] DRAM Limit Address i Bits 39-24
135 * This field defines the upper address bits of a 40 bit address
136 * that define the end of the DRAM region.
138 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
139 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
140 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
141 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
142 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
143 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
144 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
145 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
146 /* DRAM Base i Registers
155 * [ 0: 0] Read Enable
158 * [ 1: 1] Write Enable
159 * 0 = Writes Disabled
162 * [10: 8] Interleave Enable
163 * 000 = No interleave
164 * 001 = Interleave on A[12] (2 nodes)
166 * 011 = Interleave on A[12] and A[14] (4 nodes)
170 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
172 * [13:16] DRAM Base Address i Bits 39-24
173 * This field defines the upper address bits of a 40-bit address
174 * that define the start of the DRAM region.
176 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
177 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
178 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
179 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
180 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
181 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
182 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
183 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
185 /* DRAM CS Base Address i Registers
194 * [ 0: 0] Chip-Select Bank Enable
198 * [ 2: 2] Memory Test Failed
200 * [13: 5] Base Address (21-13)
201 * An optimization used when all DIMM are the same size...
203 * [28:19] Base Address (36-27)
204 * This field defines the top 11 addresses bit of a 40-bit
205 * address that define the memory address space. These
206 * bits decode 32-MByte blocks of memory.
209 PCI_ADDR(0, 0x18, 2, 0x40), 0xe007c018, 0x00000000,
210 PCI_ADDR(0, 0x18, 2, 0x44), 0xe007c018, 0x00000000,
211 PCI_ADDR(0, 0x18, 2, 0x48), 0xe007c018, 0x00000000,
212 PCI_ADDR(0, 0x18, 2, 0x4C), 0xe007c018, 0x00000000,
213 PCI_ADDR(0, 0x18, 2, 0x50), 0xe007c018, 0x00000000,
214 PCI_ADDR(0, 0x18, 2, 0x54), 0xe007c018, 0x00000000,
215 PCI_ADDR(0, 0x18, 2, 0x58), 0xe007c018, 0x00000000,
216 PCI_ADDR(0, 0x18, 2, 0x5C), 0xe007c018, 0x00000000,
217 /* DRAM CS Mask Address i Registers
222 * Select bits to exclude from comparison with the DRAM Base address register.
224 * [13: 5] Address Mask (21-13)
225 * Address to be excluded from the optimized case
227 * [28:19] Address Mask (36-27)
228 * The bits with an address mask of 1 are excluded from address comparison
232 PCI_ADDR(0, 0x18, 2, 0x60), 0xe007c01f, 0x00000000,
233 PCI_ADDR(0, 0x18, 2, 0x64), 0xe007c01f, 0x00000000,
234 PCI_ADDR(0, 0x18, 2, 0x68), 0xe007c01f, 0x00000000,
235 PCI_ADDR(0, 0x18, 2, 0x6C), 0xe007c01f, 0x00000000,
237 /* DRAM Control Register
239 * [ 3: 0] RdPtrInit ( Read Pointer Initial Value)
240 * 0x03-0x00: reserved
241 * [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO)
244 * 010 = 1.5 Memory Clocks
245 * 011 = 2 Memory Clocks
246 * 100 = 2.5 Memory Clocks
247 * 101 = 3 Memory Clocks
248 * 110 = 3.5 Memory Clocks
251 * [16:16] AltVidC3MemClkTriEn (AltVID Memory Clock Tristate Enable)
252 * Enables the DDR memory clocks to be tristated when alternate VID
253 * mode is enabled. This bit has no effect if the DisNbClkRamp bit
255 * [17:17] DllTempAdjTime (DLL Temperature Adjust Cycle Time)
258 * [18:18] DqsRcvEnTrain (DQS Receiver Enable Training Mode)
259 * 0 = Normal DQS Receiver enable operation
260 * 1 = DQS receiver enable training mode
263 PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6<<4)|(6<<0),
265 /* DRAM Initialization Register
267 * [15: 0] MrsAddress (Address for MRS/EMRS Commands)
268 * this field specifies the dsata driven on the DRAM address pins
269 * 15-0 for MRS and EMRS commands
270 * [18:16] MrsBank (Bank Address for MRS/EMRS Commands)
271 * this files specifies the data driven on the DRAM bank pins for
272 * the MRS and EMRS commands
274 * [24:24] SendPchgAll (Send Precharge All Command)
275 * Setting this bit causes the DRAM controller to send a precharge
276 * all command. This bit is cleared by the hardware after the
278 * [25:25] SendAutoRefresh (Send Auto Refresh Command)
279 * Setting this bit causes the DRAM controller to send an auto
280 * refresh command. This bit is cleared by the hardware after the
282 * [26:26] SendMrsCmd (Send MRS/EMRS Command)
283 * Setting this bit causes the DRAM controller to send the MRS or
284 * EMRS command defined by the MrsAddress and MrsBank fields. This
285 * bit is cleared by the hardware adter the commmand completes
286 * [27:27] DeassertMemRstX (De-assert Memory Reset)
287 * Setting this bit causes the DRAM controller to de-assert the
288 * memory reset pin. This bit cannot be used to assert the memory
290 * [28:28] AssertCke (Assert CKE)
291 * setting this bit causes the DRAM controller to assert the CKE
292 * pins. This bit cannot be used to de-assert the CKE pins
294 * [31:31] EnDramInit (Enable DRAM Initialization)
295 * Setting this bit puts the DRAM controller in a BIOS controlled
296 * DRAM initialization mode. BIOS must clear this bit aster DRAM
297 * initialization is complete.
299 // PCI_ADDR(0, 0x18, 2, 0x7C), 0x60f80000, 0,
302 /* DRAM Bank Address Mapping Register
304 * Specify the memory module size
324 PCI_ADDR(0, 0x18, 2, 0x80), 0xffff0000, 0x00000000,
325 /* DRAM Timing Low Register
327 * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid)
337 * [ 5: 4] Trcd (Ras#-active to Cas# read/write delay)
343 * [ 9: 8] Trp (Row Precharge Time, Precharge-to-Active or Auto-Refresh)
349 * [11:11] Trtp (Read to Precharge Time, read Cas# to precharge time)
350 * 0 = 2 clocks for Burst Length of 32 Bytes
351 * 4 clocks for Burst Length of 64 Bytes
352 * 1 = 3 clocks for Burst Length of 32 Bytes
353 * 5 clocks for Burst Length of 64 Bytes
354 * [15:12] Tras (Minimum Ras# Active Time)
357 * 0010 = 5 bus clocks
359 * 1111 = 18 bus clocks
360 * [19:16] Trc (Row Cycle Time, Ras#-active to Ras#-active or auto
361 * refresh of the same bank)
362 * 0000 = 11 bus clocks
363 * 0010 = 12 bus clocks
365 * 1110 = 25 bus clocks
366 * 1111 = 26 bus clocks
367 * [21:20] Twr (Write Recovery Time, From the last data to precharge,
368 * writes can go back-to-back)
373 * [23:22] Trrd (Active-to-active(Ras#-to-Ras#) Delay of different banks)
378 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A,
379 * BIOS should set it to reduce the power consumption)
380 * Bit F(1207) M2 Package S1g1 Package
382 * 1 N/A MA0_CLK1 MA0_CLK1
385 * 4 MA1_CLK MA1_CLK0 N/A
386 * 5 MA0_CLK MA0_CLK0 MA0_CLK0
388 * 7 N/A MA0_CLK2 MA0_CLK2
390 PCI_ADDR(0, 0x18, 2, 0x88), 0x000004c8, 0xff000002 /* 0x03623125 */ ,
391 /* DRAM Timing High Register
394 * [ 6: 4] TrwtTO (Read-to-Write Turnaround for Data, DQS Contention)
404 * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay,
405 * minium write-to-read delay when both access the same chip select)
410 * [11:10] Twrrd (Write to Read DIMM Termination Turnaround, minimum
411 * write-to-read delay when accessing two different DIMMs)
416 * [13:12] Twrwr (Write to Write Timing)
417 * 00 = 1 bus clocks ( 0 idle cycle on the bus)
418 * 01 = 2 bus clocks ( 1 idle cycle on the bus)
419 * 10 = 3 bus clocks ( 2 idle cycles on the bus)
421 * [15:14] Trdrd ( Read to Read Timing)
422 * 00 = 2 bus clocks ( 1 idle cycle on the bus)
423 * 01 = 3 bus clocks ( 2 idle cycles on the bus)
424 * 10 = 4 bus clocks ( 3 idle cycles on the bus)
425 * 11 = 5 bus clocks ( 4 idel cycles on the bus)
426 * [17:16] Tref (Refresh Rate)
427 * 00 = Undefined behavior
429 * 10 = Refresh interval of 7.8 microseconds
430 * 11 = Refresh interval of 3.9 microseconds
432 * [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0,
433 * based on DRAM density and speed)
434 * 000 = 75 ns (all speeds, 256Mbit)
435 * 001 = 105 ns (all speeds, 512Mbit)
436 * 010 = 127.5 ns (all speeds, 1Gbit)
437 * 011 = 195 ns (all speeds, 2Gbit)
438 * 100 = 327.5 ns (all speeds, 4Gbit)
442 * [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1,
443 * based on DRAM density and speed)
444 * [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2,
445 * based on DRAM density and speed)
446 * [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3,
447 * based on DRAM density and speed)
449 PCI_ADDR(0, 0x18, 2, 0x8c), 0x000c008f, (2 << 16)|(1 << 8),
450 /* DRAM Config Low Register
452 * [ 0: 0] InitDram (Initialize DRAM)
453 * 1 = write 1 cause DRAM controller to execute the DRAM
454 * initialization, when done it read to 0
455 * [ 1: 1] ExitSelfRef ( Exit Self Refresh Command )
456 * 1 = write 1 causes the DRAM controller to bring the DRAMs out
457 * for self refresh mode
459 * [ 5: 4] DramTerm (DRAM Termination)
460 * 00 = On die termination disabled
465 * [ 7: 7] DramDrvWeak ( DRAM Drivers Weak Mode)
466 * 0 = Normal drive strength mode.
467 * 1 = Weak drive strength mode
468 * [ 8: 8] ParEn (Parity Enable)
469 * 1 = Enable address parity computation output, PAR,
470 * and enables the parity error input, ERR
471 * [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable)
472 * 1 = Enable high temperature ( two times normal )
474 * [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes)
477 * [11:11] Width128 ( Width of DRAM interface)
478 * 0 = the controller DRAM interface is 64-bits wide
479 * 1 = the controller DRAM interface is 128-bits wide
480 * [12:12] X4Dimm (DIMM 0 is x4)
481 * [13:13] X4Dimm (DIMM 1 is x4)
482 * [14:14] X4Dimm (DIMM 2 is x4)
483 * [15:15] X4Dimm (DIMM 3 is x4)
485 * 1 = x4 DIMM present
486 * [16:16] UnBuffDimm ( Unbuffered DIMMs)
488 * 1 = Unbuffered DIMMs
490 * [19:19] DimmEccEn ( DIMM ECC Enable )
491 * 1 = ECC checking is being enabled for all DIMMs on the DRAM
492 * controller ( Through F3 0x44[EccEn])
495 PCI_ADDR(0, 0x18, 2, 0x90), 0xfff6004c, 0x00000010,
496 /* DRAM Config High Register
498 * [ 0: 2] MemClkFreq ( Memory Clock Frequency)
504 * [ 3: 3] MemClkFreqVal (Memory Clock Freqency Valid)
505 * 1 = BIOS need to set the bit when setting up MemClkFreq to
507 * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency)
512 * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8
513 * registered DIMMs are present in the system
514 * 0 = DM pins function as data mask pins
515 * 1 = DM pins function as read DQS pins
517 * [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit
518 * is set, the DRAM controller is disabled, and interface in low power
520 * 0 = Enabled (default)
522 * [15:15] PowerDownEn ( Power Down Mode Enable )
523 * 0 = Disabled (default)
525 * [16:16] PowerDown ( Power Down Mode )
526 * 0 = Channel CKE Control
527 * 1 = Chip Select CKE Control
528 * [17:17] FourRankSODimm (Four Rank SO-DIMM)
529 * 1 = this bit is set by BIOS to indicate that a four rank
531 * [18:18] FourRankRDimm (Four Rank Registered DIMM)
532 * 1 = this bit is set by BIOS to indicate that a four rank
533 * registered DIMM is present
535 * [20:20] SlowAccessMode (Slow Access Mode (2T Mode))
536 * 0 = DRAM address and control signals are driven for one
538 * 1 = One additional MEMCLK of setup time is provided on all
539 * DRAM address and control signals except CS, CKE, and ODT;
540 * i.e., these signals are drivern for two MEMCLK cycles
543 * [22:22] BankSwizzleMode ( Bank Swizzle Mode),
544 * 0 = Disabled (default)
547 * [27:24] DcqBypassMax ( DRAM Controller Queue Bypass Maximum)
548 * 0000 = No bypass; the oldest request is never bypassed
549 * 0001 = The oldest request may be bypassed no more than 1 time
551 * 1111 = The oldest request may be bypassed no more than 15\
553 * [31:28] FourActWindow ( Four Bank Activate Window) , not more than
554 * 4 banks in a 8 bank device are activated
555 * 0000 = No tFAW window restriction
556 * 0001 = 8 MEMCLK cycles
557 * 0010 = 9 MEMCLK cycles
559 * 1101 = 20 MEMCLK cycles
562 PCI_ADDR(0, 0x18, 2, 0x94), 0x00a82f00,0x00008000,
563 /* DRAM Delay Line Register
565 * [ 0: 0] MemClrStatus (Memory Clear Status) : Readonly
566 * when set, this bit indicates that the memory clear function
567 * is complete. Only clear by reset. BIOS should not write or
568 * read the DRAM until this bit is set by hardware
569 * [ 1: 1] DisableJitter ( Disable Jitter)
570 * When set the DDR compensation circuit will not change the
571 * values unless the change is more than one step from the
573 * [ 3: 2] RdWrQByp ( Read/Write Queue Bypass Count)
578 * [ 4: 4] Mode64BitMux (Mismatched DIMM Support Enable)
579 * 1 When bit enables support for mismatched DIMMs when using
580 * 128-bit DRAM interface, the Width128 no effect, only for
582 * [ 5: 5] DCC_EN ( Dynamica Idle Cycle Counter Enable)
583 * When set to 1, indicates that each entry in the page tables
584 * dynamically adjusts the idle cycle limit based on page
585 * Conflict/Page Miss (PC/PM) traffic
586 * [ 8: 6] ILD_lmt ( Idle Cycle Limit)
595 * [ 9: 9] DramEnabled ( DRAM Enabled)
596 * When Set, this bit indicates that the DRAM is enabled, this
597 * bit is set by hardware after DRAM initialization or on an exit
598 * from self refresh. The DRAM controller is intialized after the
599 * hardware-controlled initialization process ( initiated by the
600 * F2 0x90[DramInit]) completes or when the BIOS-controlled
601 * initialization process completes (F2 0x7c(EnDramInit] is
602 * written from 1 to 0)
604 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B,
605 * BIOS should set it to reduce the power consumption)
606 * Bit F(1207) M2 Package S1g1 Package
608 * 1 N/A MA0_CLK1 MA0_CLK1
611 * 4 MA1_CLK MA1_CLK0 N/A
612 * 5 MA0_CLK MA0_CLK0 MA0_CLK0
614 * 7 N/A MA0_CLK2 MA0_CLK2
616 PCI_ADDR(0, 0x18, 2, 0xa0), 0x00fffc00, 0xff000000,
618 /* DRAM Scrub Control Register
620 * [ 4: 0] DRAM Scrube Rate
622 * [12: 8] L2 Scrub Rate
624 * [20:16] Dcache Scrub
627 * 00000 = Do not scrub
649 * All Others = Reserved
651 PCI_ADDR(0, 0x18, 3, 0x58), 0xffe0e0e0, 0x00000000,
652 /* DRAM Scrub Address Low Register
654 * [ 0: 0] DRAM Scrubber Redirect Enable
656 * 1 = Scrubber Corrects errors found in normal operation
658 * [31: 6] DRAM Scrub Address 31-6
660 PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000,
661 /* DRAM Scrub Address High Register
663 * [ 7: 0] DRAM Scrubb Address 39-32
666 PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
668 /* for PCI_ADDR(0, 0x18, 2, 0x98) index,
669 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
672 [29: 0] DctOffset (Dram Controller Offset)
673 [30:30] DctAccessWrite (Dram Controller Read/Write Select)
676 [31:31] DctAccessDone (Dram Controller Access Done)
677 0 = Access in progress
678 1 = No access is progress
681 [31: 0] DctOffsetData (Dram Controller Offset Data)
684 - Write the register num to DctOffset with DctAccessWrite = 0
685 - poll the DctAccessDone until it = 1
686 - Read the data from DctOffsetData
688 - Write the data to DctOffsetData
689 - Write register num to DctOffset with DctAccessWrite = 1
690 - poll the DctAccessDone untio it = 1
696 if (!controller_present(ctrl)) {
697 sysinfo->ctrl_present[ctrl->node_id] = 0;
700 sysinfo->ctrl_present[ctrl->node_id] = 1;
702 printk_spew("setting up CPU %02x northbridge registers\n", ctrl->node_id);
703 max = ARRAY_SIZE(register_values);
704 for (i = 0; i < max; i += 3) {
708 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
709 where = register_values[i] & 0xff;
710 reg = pci_read_config32(dev, where);
711 reg &= register_values[i+1];
712 reg |= register_values[i+2];
713 pci_write_config32(dev, where, reg);
715 printk_spew("done.\n");
718 static int is_dual_channel(const struct mem_controller *ctrl)
721 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
722 return dcl & DCL_Width128;
725 static int is_opteron(const struct mem_controller *ctrl)
727 /* Test to see if I am an Opteron.
728 * FIXME Testing dual channel capability is correct for now
729 * but a better test is probably required.
730 * m2 and s1g1 support dual channel too. but only support unbuffered dimm
732 #warning "FIXME implement a better test for opterons"
734 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
735 return !!(nbcap & NBCAP_128Bit);
738 static int is_registered(const struct mem_controller *ctrl)
740 /* Test to see if we are dealing with registered SDRAM.
741 * If we are not registered we are unbuffered.
742 * This function must be called after spd_handle_unbuffered_dimms.
745 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
746 return !(dcl & DCL_UnBuffDimm);
750 static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
752 /* Calculate the log base 2 size of a DIMM in bits */
759 value = spd_read_byte(device, SPD_ROW_NUM); /* rows */
760 if (value < 0) goto hw_err;
761 if ((value & 0xff) == 0) goto val_err; /* max is 16 ? */
762 sz->per_rank += value & 0xff;
763 sz->rows = value & 0xff;
765 value = spd_read_byte(device, SPD_COL_NUM); /* columns */
766 if (value < 0) goto hw_err;
767 if ((value & 0xff) == 0) goto val_err; /* max is 11 */
768 sz->per_rank += value & 0xff;
769 sz->col = value & 0xff;
771 value = spd_read_byte(device, SPD_BANK_NUM); /* banks */
772 if (value < 0) goto hw_err;
773 if ((value & 0xff) == 0) goto val_err;
774 sz->bank = log2(value & 0xff); // convert 4 to 2, and 8 to 3
775 sz->per_rank += sz->bank;
777 /* Get the module data width and convert it to a power of two */
778 value = spd_read_byte(device, SPD_DATA_WIDTH);
779 if (value < 0) goto hw_err;
781 if ((value != 72) && (value != 64)) goto val_err;
782 sz->per_rank += log2(value) - 3; //64 bit So another 3 lines
784 /* How many ranks? */
785 /* number of physical banks */
786 value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK);
787 if (value < 0) goto hw_err;
788 /* value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT; */
789 value &= SPD_MOD_ATTRIB_RANK_NUM_MASK;
790 value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4
792 rank == 1 only one rank or say one side
793 rank == 2 two side , and two ranks
794 rank == 4 two side , and four ranks total
795 Some one side two ranks, because of stacked
797 if ((value != 1) && (value != 2) && (value != 4 )) {
802 /* verify if per_rank is equal byte 31
803 it has the DIMM size as a multiple of 128MB.
805 value = spd_read_byte(device, SPD_RANK_SIZE);
806 if (value < 0) goto hw_err;
809 if (value <=4 ) value += 8; // add back to 1G to high
810 value += (27-5); // make 128MB to the real lines
811 if ( value != (sz->per_rank)) {
812 printk_err("Bad RANK Size --\n");
819 die("Bad SPD value\n");
820 /* If an hw_error occurs report that I have no memory */
832 static void set_dimm_size(const struct mem_controller *ctrl,
833 struct dimm_size *sz, unsigned index,
834 struct mem_info *meminfo)
836 uint32_t base0, base1;
838 /* For each base register.
839 * Place the dimm size in 32 MB quantities in the bits 31 - 21.
840 * The initialize dimm size is in bits.
841 * Set the base enable bit0.
846 /* Make certain side1 of the dimm is at least 128MB */
847 if (sz->per_rank >= 27) {
848 base0 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
851 /* Make certain side2 of the dimm is at least 128MB */
852 if (sz->rank > 1) { // 2 ranks or 4 ranks
853 base1 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
856 /* Double the size if we are using dual channel memory */
857 if (meminfo->is_Width128) {
858 base0 = (base0 << 1) | (base0 & 1);
859 base1 = (base1 << 1) | (base1 & 1);
862 /* Clear the reserved bits */
863 base0 &= ~0xe007fffe;
864 base1 &= ~0xe007fffe;
866 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
867 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
868 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
870 /* Set the appropriate DIMM base address register */
871 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0);
872 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1);
873 #if QRANK_DIMM_SUPPORT == 1
875 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
876 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
881 /* Enable the memory clocks for this DIMM by Clear the MemClkDis bit*/
885 #if CONFIG_CPU_SOCKET_TYPE == 0x10 /* L1 */
886 ClkDis0 = DTL_MemClkDis0;
887 #elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM2 */
888 ClkDis0 = DTL_MemClkDis0_AM2;
889 #elif CONFIG_CPU_SOCKET_TYPE == 0x12 /* S1G1 */
890 ClkDis0 = DTL_MemClkDis0_S1g1;
893 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
894 dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
895 dword &= ~(ClkDis0 >> index);
896 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
899 dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
900 dword &= ~(ClkDis0 >> index);
901 #if QRANK_DIMM_SUPPORT == 1
903 dword &= ~(ClkDis0 >> (index+2));
906 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dword);
908 if (meminfo->is_Width128) { // ChannelA+B
909 dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
910 dword &= ~(ClkDis0 >> index);
911 #if QRANK_DIMM_SUPPORT == 1
913 dword &= ~(ClkDis0 >> (index+2));
916 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
923 /* row col bank for 64 bit
939 static void set_dimm_cs_map(const struct mem_controller *ctrl,
940 struct dimm_size *sz, unsigned index,
941 struct mem_info *meminfo)
943 static const uint8_t cs_map_aaa[24] = {
944 /* (bank=2, row=13, col=9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */
959 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
962 map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
963 map &= ~(0xf << (index * 4));
964 #if QRANK_DIMM_SUPPORT == 1
966 map &= ~(0xf << ( (index + 2) * 4));
970 /* Make certain side1 of the dimm is at least 128MB */
971 if (sz->per_rank >= 27) {
973 temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ];
974 map |= temp_map << (index*4);
975 #if QRANK_DIMM_SUPPORT == 1
977 map |= temp_map << ( (index + 2) * 4);
982 pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
987 static long spd_set_ram_size(const struct mem_controller *ctrl,
988 struct mem_info *meminfo)
992 for (i = 0; i < DIMM_SOCKETS; i++) {
993 struct dimm_size *sz = &(meminfo->sz[i]);
994 u32 spd_device = ctrl->channel0[i];
996 if (!(meminfo->dimm_mask & (1 << i))) {
997 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
998 spd_device = ctrl->channel1[i];
1004 spd_get_dimm_size(spd_device, sz);
1005 if (sz->per_rank == 0) {
1006 return -1; /* Report SPD error */
1008 set_dimm_size(ctrl, sz, i, meminfo);
1009 set_dimm_cs_map(ctrl, sz, i, meminfo);
1011 return meminfo->dimm_mask;
1014 static void route_dram_accesses(const struct mem_controller *ctrl,
1015 unsigned long base_k, unsigned long limit_k)
1017 /* Route the addresses to the controller node */
1022 unsigned limit_reg, base_reg;
1025 node_id = ctrl->node_id;
1026 index = (node_id << 3);
1027 limit = (limit_k << 2);
1028 limit &= 0xffff0000;
1029 limit -= 0x00010000;
1030 limit |= ( 0 << 8) | (node_id << 0);
1031 base = (base_k << 2);
1033 base |= (0 << 8) | (1<<1) | (1<<0);
1035 limit_reg = 0x44 + index;
1036 base_reg = 0x40 + index;
1037 for (device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1);
1038 device += PCI_DEV(0, 1, 0)) {
1039 pci_write_config32(device, limit_reg, limit);
1040 pci_write_config32(device, base_reg, base);
1044 static void set_top_mem(unsigned tom_k, unsigned hole_startk)
1046 /* Error if I don't have memory */
1051 /* Report the amount of memory. */
1052 printk_debug("RAM end at 0x%08x kB\n", tom_k);
1054 /* Now set top of memory */
1056 if (tom_k > (4*1024*1024)) {
1057 printk_raminit("Handling memory mapped above 4 GB\n");
1058 printk_raminit("Upper RAM end at 0x%08x kB\n", tom_k);
1059 msr.lo = (tom_k & 0x003fffff) << 10;
1060 msr.hi = (tom_k & 0xffc00000) >> 22;
1061 wrmsr(TOP_MEM2, msr);
1062 printk_raminit("Correcting memory amount mapped below 4 GB\n");
1065 /* Leave a 64M hole between TOP_MEM and TOP_MEM2
1066 * so I can see my rom chip and other I/O devices.
1068 if (tom_k >= 0x003f0000) {
1069 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
1070 if (hole_startk != 0) {
1071 tom_k = hole_startk;
1075 printk_raminit("Adjusting lower RAM end\n");
1077 printk_raminit("Lower RAM end at 0x%08x kB\n", tom_k);
1078 msr.lo = (tom_k & 0x003fffff) << 10;
1079 msr.hi = (tom_k & 0xffc00000) >> 22;
1080 wrmsr(TOP_MEM, msr);
1083 static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, int is_Width128)
1087 static const uint8_t csbase_low_f0_shift[] = {
1088 /* 128MB */ (14 - (13-5)),
1089 /* 256MB */ (15 - (13-5)),
1090 /* 512MB */ (15 - (13-5)),
1091 /* 512MB */ (16 - (13-5)),
1092 /* 512MB */ (16 - (13-5)),
1093 /* 1GB */ (16 - (13-5)),
1094 /* 1GB */ (16 - (13-5)),
1095 /* 2GB */ (16 - (13-5)),
1096 /* 2GB */ (17 - (13-5)),
1097 /* 4GB */ (17 - (13-5)),
1098 /* 4GB */ (16 - (13-5)),
1099 /* 8GB */ (17 - (13-5)),
1102 /* cs_base_high is not changed */
1104 uint32_t csbase_inc;
1105 int chip_selects, index;
1107 unsigned common_size;
1108 unsigned common_cs_mode;
1109 uint32_t csbase, csmask;
1111 /* See if all of the memory chip selects are the same size
1112 * and if so count them.
1116 common_cs_mode = 0xff;
1117 for (index = 0; index < 8; index++) {
1122 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1124 /* Is it enabled? */
1129 size = (value >> 19) & 0x3ff;
1130 if (common_size == 0) {
1133 /* The size differed fail */
1134 if (common_size != size) {
1138 value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
1139 cs_mode =( value >> ((index>>1)*4)) & 0xf;
1140 if (common_cs_mode == 0xff) {
1141 common_cs_mode = cs_mode;
1143 /* The cs_mode differed fail */
1144 if (common_cs_mode != cs_mode) {
1149 /* Chip selects can only be interleaved when there is
1150 * more than one and their is a power of two of them.
1152 bits = log2(chip_selects);
1153 if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) {
1154 //chip_selects max = 8
1158 /* Find the bits of csbase that we need to interleave on */
1159 csbase_inc = 1 << (csbase_low_f0_shift[common_cs_mode]);
1164 /* Compute the initial values for csbase and csbask.
1165 * In csbase just set the enable bit and the base to zero.
1166 * In csmask set the mask bits for the size and page level interleave.
1169 csmask = (((common_size << bits) - 1) << 19);
1170 csmask |= 0x3fe0 & ~((csbase_inc << bits) - csbase_inc);
1171 for (index = 0; index < 8; index++) {
1174 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1175 /* Is it enabled? */
1179 pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
1180 if ((index & 1) == 0) { //only have 4 CSMASK
1181 pci_write_config32(ctrl->f2, DRAM_CSMASK + ((index>>1) << 2), csmask);
1183 csbase += csbase_inc;
1186 printk_debug("Interleaved\n");
1188 /* Return the memory size in K */
1189 return common_size << ((27-10) + bits);
1192 static unsigned long order_chip_selects(const struct mem_controller *ctrl)
1196 /* Remember which registers we have used in the high 8 bits of tom */
1199 /* Find the largest remaining canidate */
1200 unsigned index, canidate;
1201 uint32_t csbase, csmask;
1205 for (index = 0; index < 8; index++) {
1207 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1209 /* Is it enabled? */
1214 /* Is it greater? */
1215 if (value <= csbase) {
1219 /* Has it already been selected */
1220 if (tom & (1 << (index + 24))) {
1223 /* I have a new canidate */
1228 /* See if I have found a new canidate */
1233 /* Remember the dimm size */
1234 size = csbase >> 19;
1236 /* Remember I have used this register */
1237 tom |= (1 << (canidate + 24));
1239 /* Recompute the cs base register value */
1240 csbase = (tom << 19) | 1;
1242 /* Increment the top of memory */
1245 /* Compute the memory mask */
1246 csmask = ((size -1) << 19);
1247 csmask |= 0x3fe0; /* For now don't optimize */
1249 /* Write the new base register */
1250 pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
1251 /* Write the new mask register */
1252 if ((canidate & 1) == 0) { //only have 4 CSMASK
1253 pci_write_config32(ctrl->f2, DRAM_CSMASK + ((canidate >> 1) << 2), csmask);
1257 /* Return the memory size in K */
1258 return (tom & ~0xff000000) << (27-10);
1261 unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
1265 /* Find the last memory address used */
1267 for (node_id = 0; node_id < max_node_id; node_id++) {
1268 uint32_t limit, base;
1270 index = node_id << 3;
1271 base = pci_read_config32(ctrl->f1, 0x40 + index);
1272 /* Only look at the limit if the base is enabled */
1273 if ((base & 3) == 3) {
1274 limit = pci_read_config32(ctrl->f1, 0x44 + index);
1275 end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
1281 static void order_dimms(const struct mem_controller *ctrl,
1282 struct mem_info *meminfo)
1284 unsigned long tom_k, base_k;
1286 if (read_option(CMOS_VSTART_interleave_chip_selects,
1287 CMOS_VLEN_interleave_chip_selects, 1) != 0) {
1288 tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
1290 printk_debug("Interleaving disabled\n");
1295 tom_k = order_chip_selects(ctrl);
1298 /* Compute the memory base address */
1299 base_k = memory_end_k(ctrl, ctrl->node_id);
1301 route_dram_accesses(ctrl, base_k, tom_k);
1302 set_top_mem(tom_k, 0);
1305 static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
1306 struct mem_info *meminfo)
1308 printk_debug("disabling dimm %02x\n", index);
1309 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
1310 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
1311 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
1313 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0);
1314 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0);
1315 #if QRANK_DIMM_SUPPORT == 1
1316 if (meminfo->sz[index].rank == 4) {
1317 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
1318 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
1323 meminfo->dimm_mask &= ~(1 << index);
1324 return meminfo->dimm_mask;
1327 static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
1328 struct mem_info *meminfo)
1331 uint32_t registered;
1334 for (i = 0; (i < DIMM_SOCKETS); i++) {
1336 u32 spd_device = ctrl->channel0[i];
1337 if (!(meminfo->dimm_mask & (1 << i))) {
1338 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1339 spd_device = ctrl->channel1[i];
1344 value = spd_read_byte(spd_device, SPD_DIMM_TYPE);
1349 /* Registered dimm ? */
1351 if ((value == SPD_DIMM_TYPE_RDIMM) || (value == SPD_DIMM_TYPE_mRDIMM)) {
1352 //check SPD_MOD_ATTRIB to verify it is SPD_MOD_ATTRIB_REGADC (0x11)?
1353 registered |= (1<<i);
1357 if (is_opteron(ctrl)) {
1359 if ( registered != (meminfo->dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) {
1360 meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffed dimm
1361 // die("Mixed buffered and registered dimms not supported");
1363 //By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM
1365 die("Unbuffered Dimms not supported on Opteron");
1371 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1372 dcl &= ~DCL_UnBuffDimm;
1373 meminfo->is_registered = 1;
1375 dcl |= DCL_UnBuffDimm;
1376 meminfo->is_registered = 0;
1378 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1380 if (meminfo->is_registered) {
1381 printk_spew("Registered\n");
1383 printk_spew("Unbuffered\n");
1385 return meminfo->dimm_mask;
1388 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
1393 for (i = 0; i < DIMM_SOCKETS; i++) {
1396 device = ctrl->channel0[i];
1397 printk_raminit("DIMM socket %i, channel 0 SPD device is 0x%02x\n", i, device);
1399 byte = spd_read_byte(ctrl->channel0[i], SPD_MEM_TYPE); /* Type */
1400 if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
1401 dimm_mask |= (1 << i);
1404 device = ctrl->channel1[i];
1405 printk_raminit("DIMM socket %i, channel 1 SPD device is 0x%02x\n", i, device);
1407 byte = spd_read_byte(ctrl->channel1[i], SPD_MEM_TYPE);
1408 if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
1409 dimm_mask |= (1 << (i + DIMM_SOCKETS));
1416 static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_info *meminfo)
1420 /* SPD addresses to verify are identical */
1421 static const uint8_t addresses[] = {
1422 2, /* Type should be DDR2 SDRAM */
1423 3, /* *Row addresses */
1424 4, /* *Column addresses */
1425 5, /* *Number of DIMM Ranks */
1426 6, /* *Module Data Width*/
1427 11, /* *DIMM Conf Type */
1428 13, /* *Pri SDRAM Width */
1429 17, /* *Logical Banks */
1430 20, /* *DIMM Type Info */
1431 21, /* *SDRAM Module Attributes */
1432 27, /* *tRP Row precharge time */
1433 28, /* *Minimum Row Active to Row Active Delay (tRRD) */
1434 29, /* *tRCD RAS to CAS */
1435 30, /* *tRAS Activate to Precharge */
1436 36, /* *Write recovery time (tWR) */
1437 37, /* *Internal write to read command delay (tRDP) */
1438 38, /* *Internal read to precharge command delay (tRTP) */
1439 40, /* *Extension of Byte 41 tRC and Byte 42 tRFC */
1440 41, /* *Minimum Active to Active/Auto Refresh Time(Trc) */
1441 42, /* *Minimum Auto Refresh Command Time(Trfc) */
1442 /* The SPD addresses 18, 9, 23, 26 need special treatment like
1443 * in spd_set_memclk. Right now they cause many false negatives.
1444 * Keep them at the end to see other mismatches (if any).
1446 18, /* *Supported CAS Latencies */
1447 9, /* *Cycle time at highest CAS Latency CL=X */
1448 23, /* *Cycle time at CAS Latency (CLX - 1) */
1449 26, /* *Cycle time at CAS Latency (CLX - 2) */
1454 /* S1G1 and AM2 sockets are Mod64BitMux capable. */
1455 #if CONFIG_CPU_SOCKET_TYPE == 0x11 || CONFIG_CPU_SOCKET_TYPE == 0x12
1461 /* If the dimms are not in pairs do not do dual channels */
1462 if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
1463 ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1464 goto single_channel;
1466 /* If the cpu is not capable of doing dual channels don't do dual channels */
1467 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1468 if (!(nbcap & NBCAP_128Bit)) {
1469 goto single_channel;
1471 for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
1472 unsigned device0, device1;
1475 /* If I don't have a dimm skip this one */
1476 if (!(meminfo->dimm_mask & (1 << i))) {
1479 device0 = ctrl->channel0[i];
1480 device1 = ctrl->channel1[i];
1481 /* Abort if the chips don't support a common CAS latency. */
1482 common_cl = spd_read_byte(device0, 18) & spd_read_byte(device1, 18);
1484 printk_debug("No common CAS latency supported\n");
1485 goto single_channel;
1487 printk_raminit("Common CAS latency bitfield: 0x%02x\n", common_cl);
1489 for (j = 0; j < ARRAY_SIZE(addresses); j++) {
1491 addr = addresses[j];
1492 value0 = spd_read_byte(device0, addr);
1496 value1 = spd_read_byte(device1, addr);
1500 if (value0 != value1) {
1501 printk_raminit("SPD values differ between channel 0/1 for byte %i\n", addr);
1502 goto single_channel;
1506 printk_spew("Enabling dual channel memory\n");
1507 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1508 dcl &= ~DCL_BurstLength32; /* 32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses
1509 32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode */
1510 dcl |= DCL_Width128;
1511 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1512 meminfo->is_Width128 = 1;
1513 return meminfo->dimm_mask;
1516 meminfo->is_Width128 = 0;
1517 meminfo->is_64MuxMode = 0;
1520 if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
1521 ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1522 if (((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1523 /* mux capable and single dimm in channelB */
1525 printk_spew("Enable 64MuxMode & BurstLength32\n");
1526 dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
1527 dcm |= DCM_Mode64BitMux;
1528 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
1529 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1530 //dcl |= DCL_BurstLength32; /* 32byte mode for channelB only */
1531 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1532 meminfo->is_64MuxMode = 1;
1534 meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
1537 } else { /* unmatched dual dimms ? */
1538 /* unmatched dual dimms not supported by meminit code. Use single channelA dimm. */
1539 meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
1540 printk_spew("Unmatched dual dimms. Use single channelA dimm.\n");
1542 return meminfo->dimm_mask;
1546 uint16_t cycle_time;
1547 uint8_t divisor; /* In 1/40 ns increments */
1552 uint8_t DcqByPassMax;
1553 uint32_t dch_memclk;
1557 static const struct mem_param speed[] = {
1560 .cycle_time = 0x500,
1561 .divisor = 200, // how many 1/40ns per clock
1562 .dch_memclk = DCH_MemClkFreq_200MHz, //0
1572 .cycle_time = 0x375,
1573 .divisor = 150, //????
1574 .dch_memclk = DCH_MemClkFreq_266MHz, //1
1583 .cycle_time = 0x300,
1585 .dch_memclk = DCH_MemClkFreq_333MHz, //2
1595 .cycle_time = 0x250,
1597 .dch_memclk = DCH_MemClkFreq_400MHz,//3
1605 .cycle_time = 0x000,
1609 static const struct mem_param *get_mem_param(unsigned min_cycle_time)
1612 const struct mem_param *param;
1613 for (param = &speed[0]; param->cycle_time ; param++) {
1614 if (min_cycle_time > (param+1)->cycle_time) {
1618 if (!param->cycle_time) {
1619 die("min_cycle_time to low");
1621 printk_spew("%s\n", param->name);
1625 static uint8_t get_exact_divisor(int i, uint8_t divisor)
1627 //input divisor could be 200(200), 150(266), 120(333), 100 (400)
1628 static const uint8_t dv_a[] = {
1629 /* 200 266 333 400 */
1630 /*4 */ 250, 250, 250, 250,
1631 /*5 */ 200, 200, 200, 100,
1632 /*6 */ 200, 166, 166, 100,
1633 /*7 */ 200, 171, 142, 100,
1635 /*8 */ 200, 150, 125, 100,
1636 /*9 */ 200, 156, 133, 100,
1637 /*10*/ 200, 160, 120, 100,
1638 /*11*/ 200, 163, 127, 100,
1640 /*12*/ 200, 150, 133, 100,
1641 /*13*/ 200, 153, 123, 100,
1642 /*14*/ 200, 157, 128, 100,
1643 /*15*/ 200, 160, 120, 100,
1650 /* Check for FID control support */
1651 struct cpuid_result cpuid1;
1652 cpuid1 = cpuid(0x80000007);
1653 if( cpuid1.edx & 0x02 ) {
1654 /* Use current FID */
1656 msr = rdmsr(0xc0010042);
1657 fid_cur = msr.lo & 0x3f;
1661 /* Use startup FID */
1663 msr = rdmsr(0xc0010015);
1664 fid_start = (msr.lo & (0x3f << 24));
1666 index = fid_start>>25;
1669 if (index>12) return divisor;
1671 if (i>3) return divisor;
1673 return dv_a[index * 4+i];
1678 struct spd_set_memclk_result {
1679 const struct mem_param *param;
1684 static unsigned convert_to_linear(unsigned value)
1686 static const unsigned fraction[] = { 0x25, 0x33, 0x66, 0x75 };
1689 /* We need to convert value to more readable */
1690 if ((value & 0xf) < 10) { //no .25, .33, .66, .75
1693 valuex = ((value & 0xf0) << 4) | fraction [(value & 0xf)-10];
1699 static const uint8_t latency_indicies[] = { 25, 23, 9 };
1701 int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time)
1703 int new_cycle_time, new_latency;
1708 /* First find the supported CAS latencies
1709 * Byte 18 for DDR SDRAM is interpreted:
1710 * bit 3 == CAS Latency = 3
1711 * bit 4 == CAS Latency = 4
1712 * bit 5 == CAS Latency = 5
1713 * bit 6 == CAS Latency = 6
1715 new_cycle_time = 0x500;
1718 latencies = spd_read_byte(spd_device, SPD_CAS_LAT);
1722 printk_raminit("\tlatencies: %08x\n", latencies);
1723 /* Compute the lowest cas latency which can be expressed in this
1724 * particular SPD EEPROM. You can store at most settings for 3
1725 * contiguous CAS latencies, so by taking the highest CAS
1726 * latency maked as supported in the SPD and subtracting 2 you
1727 * get the lowest expressable CAS latency. That latency is not
1728 * necessarily supported, but a (maybe invalid) entry exists
1731 latency = log2(latencies) - 2;
1733 /* Loop through and find a fast clock with a low latency */
1734 for (index = 0; index < 3; index++, latency++) {
1736 if ((latency < 3) || (latency > 6) ||
1737 (!(latencies & (1 << latency)))) {
1740 value = spd_read_byte(spd_device, latency_indicies[index]);
1745 printk_raminit("\tindex: %08x\n", index);
1746 printk_raminit("\t\tlatency: %08x\n", latency);
1747 printk_raminit("\t\tvalue1: %08x\n", value);
1749 value = convert_to_linear(value);
1751 printk_raminit("\t\tvalue2: %08x\n", value);
1753 /* Only increase the latency if we decrease the clock */
1754 if (value >= *min_cycle_time ) {
1755 if (value < new_cycle_time) {
1756 new_cycle_time = value;
1757 new_latency = latency;
1758 } else if (value == new_cycle_time) {
1759 if (new_latency > latency) {
1760 new_latency = latency;
1764 printk_raminit("\t\tnew_cycle_time: %08x\n", new_cycle_time);
1765 printk_raminit("\t\tnew_latency: %08x\n", new_latency);
1769 if (new_latency > 6){
1773 /* Does min_latency need to be increased? */
1774 if (new_cycle_time > *min_cycle_time) {
1775 *min_cycle_time = new_cycle_time;
1778 /* Does min_cycle_time need to be increased? */
1779 if (new_latency > *min_latency) {
1780 *min_latency = new_latency;
1783 printk_raminit("2 min_cycle_time: %08x\n", *min_cycle_time);
1784 printk_raminit("2 min_latency: %08x\n", *min_latency);
1789 static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, struct mem_info *meminfo)
1791 /* Compute the minimum cycle time for these dimms */
1792 struct spd_set_memclk_result result;
1793 unsigned min_cycle_time, min_latency, bios_cycle_time;
1797 static const uint16_t min_cycle_times[] = { // use full speed to compare
1798 [NBCAP_MEMCLK_NOLIMIT] = 0x250, /*2.5ns */
1799 [NBCAP_MEMCLK_333MHZ] = 0x300, /* 3.0ns */
1800 [NBCAP_MEMCLK_266MHZ] = 0x375, /* 3.75ns */
1801 [NBCAP_MEMCLK_200MHZ] = 0x500, /* 5.0s */
1805 value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1806 min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
1807 bios_cycle_time = min_cycle_times[
1808 read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
1809 if (bios_cycle_time > min_cycle_time) {
1810 min_cycle_time = bios_cycle_time;
1814 printk_raminit("1 min_cycle_time: %08x\n", min_cycle_time);
1816 /* Compute the least latency with the fastest clock supported
1817 * by both the memory controller and the dimms.
1819 for (i = 0; i < DIMM_SOCKETS; i++) {
1822 printk_raminit("1.1 dimm_mask: %08x\n", meminfo->dimm_mask);
1823 printk_raminit("i: %08x\n",i);
1825 if (meminfo->dimm_mask & (1 << i)) {
1826 spd_device = ctrl->channel0[i];
1827 printk_raminit("Channel 0 settings:\n");
1829 switch (find_optimum_spd_latency(spd_device, &min_latency, &min_cycle_time)) {
1837 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) {
1838 spd_device = ctrl->channel1[i];
1839 printk_raminit("Channel 1 settings:\n");
1841 switch (find_optimum_spd_latency(spd_device, &min_latency, &min_cycle_time)) {
1851 /* Make a second pass through the dimms and disable
1852 * any that cannot support the selected memclk and cas latency.
1855 printk_raminit("3 min_cycle_time: %08x\n", min_cycle_time);
1856 printk_raminit("3 min_latency: %08x\n", min_latency);
1858 for (i = 0; (i < DIMM_SOCKETS); i++) {
1863 u32 spd_device = ctrl->channel0[i];
1865 if (!(meminfo->dimm_mask & (1 << i))) {
1866 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1867 spd_device = ctrl->channel1[i];
1873 latencies = spd_read_byte(spd_device, SPD_CAS_LAT);
1874 if (latencies < 0) goto hw_error;
1875 if (latencies == 0) {
1879 /* Compute the lowest cas latency supported */
1880 latency = log2(latencies) -2;
1882 /* Walk through searching for the selected latency */
1883 for (index = 0; index < 3; index++, latency++) {
1884 if (!(latencies & (1 << latency))) {
1887 if (latency == min_latency)
1890 /* If I can't find the latency or my index is bad error */
1891 if ((latency != min_latency) || (index >= 3)) {
1895 /* Read the min_cycle_time for this latency */
1896 val = spd_read_byte(spd_device, latency_indicies[index]);
1897 if (val < 0) goto hw_error;
1899 val = convert_to_linear(val);
1900 /* All is good if the selected clock speed
1901 * is what I need or slower.
1903 if (val <= min_cycle_time) {
1906 /* Otherwise I have an error, disable the dimm */
1908 meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo);
1911 printk_raminit("4 min_cycle_time: %08x\n", min_cycle_time);
1913 /* Now that I know the minimum cycle time lookup the memory parameters */
1914 result.param = get_mem_param(min_cycle_time);
1916 /* Update DRAM Config High with our selected memory speed */
1917 value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
1918 value &= ~(DCH_MemClkFreq_MASK << DCH_MemClkFreq_SHIFT);
1920 value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT;
1921 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
1923 printk_debug("%s\n", result.param->name);
1925 /* Update DRAM Timing Low with our selected cas latency */
1926 value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1927 value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
1928 value |= (min_latency - DTL_TCL_BASE) << DTL_TCL_SHIFT;
1929 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
1931 result.dimm_mask = meminfo->dimm_mask;
1934 result.param = (const struct mem_param *)0;
1935 result.dimm_mask = -1;
1939 static unsigned convert_to_1_4(unsigned value)
1941 static const uint8_t fraction[] = { 0, 1, 2, 2, 3, 3, 0 };
1944 /* We need to convert value to more readable */
1945 valuex = fraction [value & 0x7];
1949 int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param)
1954 value = spd_read_byte(spd_device, SPD_TRC);
1957 printk_raminit("update_dimm_Trc: tRC (41) = %08x\n", value);
1959 value2 = spd_read_byte(spd_device, SPD_TRC -1);
1961 value += convert_to_1_4(value2>>4);
1964 printk_raminit("update_dimm_Trc: tRC final value = %i\n", value);
1966 clocks = (value + param->divisor - 1)/param->divisor;
1967 printk_raminit("update_dimm_Trc: clocks = %i\n", clocks);
1969 if (clocks < DTL_TRC_MIN) {
1970 #warning We should die here or at least disable this bank.
1971 printk_notice("update_dimm_Trc: can't refresh fast enough, "
1972 "want %i clocks, can %i clocks\n", clocks, DTL_TRC_MIN);
1973 clocks = DTL_TRC_MIN;
1978 static int update_dimm_Trc(const struct mem_controller *ctrl,
1979 const struct mem_param *param,
1980 int i, long dimm_mask)
1982 int clocks, old_clocks;
1984 u32 spd_device = ctrl->channel0[i];
1986 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
1987 spd_device = ctrl->channel1[i];
1990 clocks = get_dimm_Trc_clocks(spd_device, param);
1993 if (clocks > DTL_TRC_MAX) {
1996 printk_raminit("update_dimm_Trc: clocks after adjustment = %i\n", clocks);
1998 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1999 old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
2000 if (old_clocks >= clocks) { //?? someone did it
2001 // clocks = old_clocks;
2004 dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
2005 dtl |= ((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
2006 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
2010 static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i, struct mem_info *meminfo)
2012 unsigned clocks, old_clocks;
2016 u32 spd_device = ctrl->channel0[i];
2018 if (!(meminfo->dimm_mask & (1 << i)) && (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2019 spd_device = ctrl->channel1[i];
2020 ch_b = 2; /* offset to channelB trfc setting */
2023 //get the cs_size --> logic dimm size
2024 value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
2029 value = 6 - log2(value); //4-->4, 8-->3, 16-->2
2031 clocks = meminfo->sz[i].per_rank - 27 + 2 - value;
2033 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
2035 old_clocks = ((dth >> (DTH_TRFC0_SHIFT + ((i + ch_b) * 3))) & DTH_TRFC_MASK);
2037 if (old_clocks >= clocks) { // some one did it?
2040 dth &= ~(DTH_TRFC_MASK << (DTH_TRFC0_SHIFT + ((i + ch_b) * 3)));
2041 dth |= clocks << (DTH_TRFC0_SHIFT + ((i + ch_b) * 3));
2042 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2046 static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask,
2048 unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX )
2050 unsigned clocks, old_clocks;
2053 u32 spd_device = ctrl->channel0[i];
2055 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2056 spd_device = ctrl->channel1[i];
2059 value = spd_read_byte(spd_device, SPD_TT); //already in 1/4 ns
2060 if (value < 0) return -1;
2062 clocks = (value + param->divisor -1)/param->divisor;
2063 if (clocks < TT_MIN) {
2067 if (clocks > TT_MAX) {
2068 printk_info("warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
2072 dtl = pci_read_config32(ctrl->f2, TT_REG);
2074 old_clocks = ((dtl >> TT_SHIFT) & TT_MASK) + TT_BASE;
2075 if (old_clocks >= clocks) { //some one did it?
2076 // clocks = old_clocks;
2079 dtl &= ~(TT_MASK << TT_SHIFT);
2080 dtl |= ((clocks - TT_BASE) << TT_SHIFT);
2081 pci_write_config32(ctrl->f2, TT_REG, dtl);
2085 static int update_dimm_Trcd(const struct mem_controller *ctrl,
2086 const struct mem_param *param, int i, long dimm_mask)
2088 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRCD, DTL_TRCD_SHIFT, DTL_TRCD_MASK, DTL_TRCD_BASE, DTL_TRCD_MIN, DTL_TRCD_MAX);
2091 static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2093 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRRD, DTL_TRRD_SHIFT, DTL_TRRD_MASK, DTL_TRRD_BASE, DTL_TRRD_MIN, DTL_TRRD_MAX);
2096 static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2098 unsigned clocks, old_clocks;
2101 u32 spd_device = ctrl->channel0[i];
2103 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2104 spd_device = ctrl->channel1[i];
2107 value = spd_read_byte(spd_device, SPD_TRAS); //in 1 ns
2108 if (value < 0) return -1;
2109 printk_raminit("update_dimm_Tras: 0 value= %08x\n", value);
2111 value <<= 2; //convert it to in 1/4ns
2114 printk_raminit("update_dimm_Tras: 1 value= %08x\n", value);
2116 clocks = (value + param->divisor - 1)/param->divisor;
2117 printk_raminit("update_dimm_Tras: divisor= %08x\n", param->divisor);
2118 printk_raminit("update_dimm_Tras: clocks= %08x\n", clocks);
2119 if (clocks < DTL_TRAS_MIN) {
2120 clocks = DTL_TRAS_MIN;
2122 if (clocks > DTL_TRAS_MAX) {
2125 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
2126 old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
2127 if (old_clocks >= clocks) { // someone did it?
2130 dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
2131 dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
2132 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
2136 static int update_dimm_Trp(const struct mem_controller *ctrl,
2137 const struct mem_param *param, int i, long dimm_mask)
2139 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRP, DTL_TRP_SHIFT, DTL_TRP_MASK, DTL_TRP_BASE, DTL_TRP_MIN, DTL_TRP_MAX);
2143 static int update_dimm_Trtp(const struct mem_controller *ctrl,
2144 const struct mem_param *param, int i, struct mem_info *meminfo)
2146 /* need to figure if it is 32 byte burst or 64 bytes burst */
2148 if (!meminfo->is_Width128) {
2150 dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2151 if ((dword & DCL_BurstLength32)) offset = 0;
2153 return update_dimm_TT_1_4(ctrl, param, i, meminfo->dimm_mask, DRAM_TIMING_LOW, SPD_TRTP, DTL_TRTP_SHIFT, DTL_TRTP_MASK, DTL_TRTP_BASE+offset, DTL_TRTP_MIN+offset, DTL_TRTP_MAX+offset);
2157 static int update_dimm_Twr(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2159 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TWR, DTL_TWR_SHIFT, DTL_TWR_MASK, DTL_TWR_BASE, DTL_TWR_MIN, DTL_TWR_MAX);
2163 static int update_dimm_Tref(const struct mem_controller *ctrl,
2164 const struct mem_param *param, int i, long dimm_mask)
2166 uint32_t dth, dth_old;
2168 u32 spd_device = ctrl->channel0[i];
2170 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2171 spd_device = ctrl->channel1[i];
2174 value = spd_read_byte(spd_device, SPD_TREF); // 0: 15.625us, 1: 3.9us 2: 7.8 us....
2175 if (value < 0) return -1;
2183 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
2186 dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
2187 dth |= (value << DTH_TREF_SHIFT);
2188 if (dth_old != dth) {
2189 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2194 static void set_4RankRDimm(const struct mem_controller *ctrl,
2195 const struct mem_param *param, struct mem_info *meminfo)
2197 #if QRANK_DIMM_SUPPORT == 1
2200 long dimm_mask = meminfo->dimm_mask;
2203 if (!(meminfo->is_registered)) return;
2207 for (i = 0; i < DIMM_SOCKETS; i++) {
2208 if (!(dimm_mask & (1 << i))) {
2212 if (meminfo->sz[i].rank == 4) {
2220 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2221 dch |= DCH_FourRankRDimm;
2222 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2227 static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
2228 struct mem_info *meminfo)
2234 uint32_t mask_single_rank;
2235 uint32_t mask_page_1k;
2237 #if QRANK_DIMM_SUPPORT == 1
2241 long dimm_mask = meminfo->dimm_mask;
2246 mask_single_rank = 0;
2249 for (i = 0; i < DIMM_SOCKETS; i++) {
2250 u32 spd_device = ctrl->channel0[i];
2251 if (!(dimm_mask & (1 << i))) {
2252 if (dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
2253 spd_device = ctrl->channel1[i];
2259 if (meminfo->sz[i].rank == 1) {
2260 mask_single_rank |= 1<<i;
2263 if (meminfo->sz[i].col==10) {
2264 mask_page_1k |= 1<<i;
2268 value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
2270 #if QRANK_DIMM_SUPPORT == 1
2271 rank = meminfo->sz[i].rank;
2276 #if QRANK_DIMM_SUPPORT == 1
2278 mask_x4 |= 1<<(i+2);
2281 } else if (value==16) {
2283 #if QRANK_DIMM_SUPPORT == 1
2285 mask_x16 |= 1<<(i+2);
2292 meminfo->x4_mask= mask_x4;
2293 meminfo->x16_mask = mask_x16;
2295 meminfo->single_rank_mask = mask_single_rank;
2296 meminfo->page_1k_mask = mask_page_1k;
2303 static void set_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2306 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2307 dcl &= ~(DCL_X4Dimm_MASK<<DCL_X4Dimm_SHIFT);
2308 dcl |= ((meminfo->x4_mask) & 0xf) << (DCL_X4Dimm_SHIFT);
2309 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2313 static int count_ones(uint32_t dimm_mask)
2318 for (index = 0; index < (2 * DIMM_SOCKETS); index++, dimm_mask >>= 1) {
2319 if (dimm_mask & 1) {
2327 static void set_DramTerm(const struct mem_controller *ctrl,
2328 const struct mem_param *param, struct mem_info *meminfo)
2334 if (param->divisor == 100) { //DDR2 800
2335 if (meminfo->is_Width128) {
2336 if (count_ones(meminfo->dimm_mask & 0x0f)==2) {
2344 #if CONFIG_DIMM_SUPPORT == 0x0204
2345 odt = 0x2; /* 150 ohms */
2348 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2349 dcl &= ~(DCL_DramTerm_MASK<<DCL_DramTerm_SHIFT);
2350 dcl |= (odt & DCL_DramTerm_MASK) << (DCL_DramTerm_SHIFT);
2351 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2354 static void set_ecc(const struct mem_controller *ctrl,
2355 const struct mem_param *param, struct mem_info *meminfo)
2360 uint32_t dcl, nbcap;
2361 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
2362 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2363 dcl &= ~DCL_DimmEccEn;
2364 if (nbcap & NBCAP_ECC) {
2365 dcl |= DCL_DimmEccEn;
2367 if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
2368 dcl &= ~DCL_DimmEccEn;
2370 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2372 meminfo->is_ecc = 1;
2373 if (!(dcl & DCL_DimmEccEn)) {
2374 meminfo->is_ecc = 0;
2375 return; // already disabled the ECC, so don't need to read SPD any more
2378 for (i = 0; i < DIMM_SOCKETS; i++) {
2379 u32 spd_device = ctrl->channel0[i];
2380 if (!(meminfo->dimm_mask & (1 << i))) {
2381 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
2382 spd_device = ctrl->channel1[i];
2383 printk_debug("set_ecc spd_device: 0x%x\n", spd_device);
2389 value = spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONF_TYPE);
2391 if (!(value & SPD_DIMM_CONF_TYPE_ECC)) {
2392 dcl &= ~DCL_DimmEccEn;
2393 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2394 meminfo->is_ecc = 0;
2402 static int update_dimm_Twtr(const struct mem_controller *ctrl,
2403 const struct mem_param *param, int i, long dimm_mask)
2405 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_HIGH, SPD_TWTR, DTH_TWTR_SHIFT, DTH_TWTR_MASK, DTH_TWTR_BASE, DTH_TWTR_MIN, DTH_TWTR_MAX);
2408 static void set_TT(const struct mem_controller *ctrl,
2409 const struct mem_param *param, unsigned TT_REG, unsigned TT_SHIFT,
2410 unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX,
2411 unsigned val, const char *str)
2415 if ((val < TT_MIN) || (val > TT_MAX)) {
2420 reg = pci_read_config32(ctrl->f2, TT_REG);
2421 reg &= ~(TT_MASK << TT_SHIFT);
2422 reg |= ((val - TT_BASE) << TT_SHIFT);
2423 pci_write_config32(ctrl->f2, TT_REG, reg);
2428 static void set_TrwtTO(const struct mem_controller *ctrl,
2429 const struct mem_param *param)
2431 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRWTTO_SHIFT, DTH_TRWTTO_MASK,DTH_TRWTTO_BASE, DTH_TRWTTO_MIN, DTH_TRWTTO_MAX, param->TrwtTO, "TrwtTO");
2435 static void set_Twrrd(const struct mem_controller *ctrl, const struct mem_param *param)
2437 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRRD_SHIFT, DTH_TWRRD_MASK,DTH_TWRRD_BASE, DTH_TWRRD_MIN, DTH_TWRRD_MAX, param->Twrrd, "Twrrd");
2441 static void set_Twrwr(const struct mem_controller *ctrl, const struct mem_param *param)
2443 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRWR_SHIFT, DTH_TWRWR_MASK,DTH_TWRWR_BASE, DTH_TWRWR_MIN, DTH_TWRWR_MAX, param->Twrwr, "Twrwr");
2446 static void set_Trdrd(const struct mem_controller *ctrl, const struct mem_param *param)
2448 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRDRD_SHIFT, DTH_TRDRD_MASK,DTH_TRDRD_BASE, DTH_TRDRD_MIN, DTH_TRDRD_MAX, param->Trdrd, "Trdrd");
2451 static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem_param *param)
2453 set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS
2456 static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2458 static const uint8_t faw_1k[] = {8, 10, 13, 14};
2459 static const uint8_t faw_2k[] = {10, 14, 17, 18};
2460 unsigned memclkfreq_index;
2464 memclkfreq_index = param->dch_memclk;
2466 if (meminfo->page_1k_mask != 0) { //1k page
2467 faw = faw_1k[memclkfreq_index];
2469 faw = faw_2k[memclkfreq_index];
2472 set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_FourActWindow_SHIFT, DCH_FourActWindow_MASK, DCH_FourActWindow_BASE, DCH_FourActWindow_MIN, DCH_FourActWindow_MAX, faw, "FourActWindow");
2475 static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
2481 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2482 dch &= ~(DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT);
2484 //FIXME: We need to use Max of DqsRcvEnDelay + 6ns here: After trainning and get that from index reg 0x10, 0x13, 0x16, 0x19, 0x30, 0x33, 0x36, 0x39
2488 dch |= ((async_lat - DCH_MaxAsyncLat_BASE) << DCH_MaxAsyncLat_SHIFT);
2489 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2492 static void set_SlowAccessMode(const struct mem_controller *ctrl)
2496 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2500 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2504 DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20
2505 DRAM_ADDR_TIMING_CTRL 04, 0x24
2507 static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *meminfo)
2511 #if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
2512 unsigned SlowAccessMode = 0;
2515 long dimm_mask = meminfo->dimm_mask & 0x0f;
2517 #if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */
2520 dwordx = 0x002f0000;
2521 switch (meminfo->memclk_set) {
2522 case DCH_MemClkFreq_266MHz:
2523 if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
2524 dwordx = 0x002f2700;
2527 case DCH_MemClkFreq_333MHz:
2528 if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
2529 if ((meminfo->single_rank_mask & 0x03)!=0x03) { //any double rank there?
2530 dwordx = 0x002f2f00;
2534 case DCH_MemClkFreq_400MHz:
2535 dwordx = 0x002f3300;
2541 #if CONFIG_DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */
2543 dwordx = 0x002F2F00;
2545 switch (meminfo->memclk_set) {
2546 case DCH_MemClkFreq_200MHz: /* nothing to be set here */
2548 case DCH_MemClkFreq_266MHz:
2549 if ((meminfo->single_rank_mask == 0)
2550 && (meminfo->x4_mask == 0) && (meminfo->x16_mask))
2551 dwordx = 0x002C2C00; /* Double rank x8 */
2552 /* else SRx16, SRx8, DRx16 == 0x002F2F00 */
2554 case DCH_MemClkFreq_333MHz:
2555 if ((meminfo->single_rank_mask == 1)
2556 && (meminfo->x16_mask == 1)) /* SR x16 */
2557 dwordx = 0x00272700;
2558 else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
2559 && (meminfo->single_rank_mask == 0)) { /* DR x8 */
2561 dwordx = 0x00002800;
2562 } else { /* SR x8, DR x16 */
2563 dwordx = 0x002A2A00;
2566 case DCH_MemClkFreq_400MHz:
2567 if ((meminfo->single_rank_mask == 1)
2568 && (meminfo->x16_mask == 1)) /* SR x16 */
2569 dwordx = 0x00292900;
2570 else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
2571 && (meminfo->single_rank_mask == 0)) { /* DR x8 */
2573 dwordx = 0x00002A00;
2574 } else { /* SR x8, DR x16 */
2575 dwordx = 0x002A2A00;
2581 #if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */
2582 /* for UNBUF DIMM */
2584 dwordx = 0x002f2f00;
2585 switch (meminfo->memclk_set) {
2586 case DCH_MemClkFreq_200MHz:
2587 if (dimm_mask == 0x03) {
2592 case DCH_MemClkFreq_266MHz:
2593 if (dimm_mask == 0x03) {
2596 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
2597 switch (meminfo->single_rank_mask) {
2599 dwordx = 0x00002f00; //x8 single Rank
2602 dwordx = 0x00342f00; //x8 double Rank
2605 dwordx = 0x00372f00; //x8 single Rank and double Rank mixed
2607 } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
2608 dwordx = 0x00382f00; //x8 Double Rank and x16 single Rank mixed
2609 } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
2610 dwordx = 0x00382f00; //x16 single Rank and x8 double Rank mixed
2614 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank
2615 dwordx = 0x002f2f00;
2617 dwordx = 0x002b2f00;
2621 case DCH_MemClkFreq_333MHz:
2622 dwordx = 0x00202220;
2623 if (dimm_mask == 0x03) {
2626 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
2627 switch (meminfo->single_rank_mask) {
2629 dwordx = 0x00302220; //x8 single Rank
2632 dwordx = 0x002b2220; //x8 double Rank
2635 dwordx = 0x002a2220; //x8 single Rank and double Rank mixed
2637 } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
2638 dwordx = 0x002c2220; //x8 Double Rank and x16 single Rank mixed
2639 } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
2640 dwordx = 0x002c2220; //x16 single Rank and x8 double Rank mixed
2644 case DCH_MemClkFreq_400MHz:
2645 dwordx = 0x00202520;
2647 if (dimm_mask == 0x03) {
2655 printk_raminit("\tdimm_mask = %08x\n", meminfo->dimm_mask);
2656 printk_raminit("\tx4_mask = %08x\n", meminfo->x4_mask);
2657 printk_raminit("\tx16_mask = %08x\n", meminfo->x16_mask);
2658 printk_raminit("\tsingle_rank_mask = %08x\n", meminfo->single_rank_mask);
2659 printk_raminit("\tODC = %08x\n", dword);
2660 printk_raminit("\tAddr Timing= %08x\n", dwordx);
2663 #if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
2664 if (SlowAccessMode) {
2665 set_SlowAccessMode(ctrl);
2669 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
2670 /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */
2671 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword);
2673 /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */
2674 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx);
2676 /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */
2677 pci_write_config32_index_wait(ctrl->f2, 0x98, 0, dword);
2678 if (meminfo->is_Width128) {
2679 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword);
2682 /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */
2683 pci_write_config32_index_wait(ctrl->f2, 0x98, 4, dwordx);
2684 if (meminfo->is_Width128) {
2685 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx);
2691 static void set_RDqsEn(const struct mem_controller *ctrl,
2692 const struct mem_param *param, struct mem_info *meminfo)
2694 #if CONFIG_CPU_SOCKET_TYPE==0x10
2695 //only need to set for reg and x8
2698 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2701 if ((!meminfo->x4_mask) && (!meminfo->x16_mask)) {
2705 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2709 static void set_idle_cycle_limit(const struct mem_controller *ctrl,
2710 const struct mem_param *param)
2713 /* AMD says to Hardcode this */
2714 dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
2715 dcm &= ~(DCM_ILD_lmt_MASK << DCM_ILD_lmt_SHIFT);
2716 dcm |= DCM_ILD_lmt_16 << DCM_ILD_lmt_SHIFT;
2718 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
2721 static void set_RdWrQByp(const struct mem_controller *ctrl,
2722 const struct mem_param *param)
2724 set_TT(ctrl, param, DRAM_CTRL_MISC, DCM_RdWrQByp_SHIFT, DCM_RdWrQByp_MASK,0, 0, 3, 2, "RdWrQByp");
2727 static long spd_set_dram_timing(const struct mem_controller *ctrl,
2728 const struct mem_param *param,
2729 struct mem_info *meminfo)
2733 for (i = 0; i < DIMM_SOCKETS; i++) {
2735 if (!(meminfo->dimm_mask & (1 << i)) &&
2736 !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) ) {
2739 printk_raminit("spd_set_dram_timing dimm socket: %08x\n", i);
2740 /* DRAM Timing Low Register */
2741 printk_raminit("\ttrc\n");
2742 if ((rc = update_dimm_Trc (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2744 printk_raminit("\ttrcd\n");
2745 if ((rc = update_dimm_Trcd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2747 printk_raminit("\ttrrd\n");
2748 if ((rc = update_dimm_Trrd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2750 printk_raminit("\ttras\n");
2751 if ((rc = update_dimm_Tras(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2753 printk_raminit("\ttrp\n");
2754 if ((rc = update_dimm_Trp (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2756 printk_raminit("\ttrtp\n");
2757 if ((rc = update_dimm_Trtp(ctrl, param, i, meminfo)) <= 0) goto dimm_err;
2759 printk_raminit("\ttwr\n");
2760 if ((rc = update_dimm_Twr (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2762 /* DRAM Timing High Register */
2763 printk_raminit("\ttref\n");
2764 if ((rc = update_dimm_Tref(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2766 printk_raminit("\ttwtr\n");
2767 if ((rc = update_dimm_Twtr(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2769 printk_raminit("\ttrfc\n");
2770 if ((rc = update_dimm_Trfc(ctrl, param, i, meminfo)) <= 0) goto dimm_err;
2772 /* DRAM Config Low */
2776 printk_debug("spd_set_dram_timing dimm_err!\n");
2780 meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo);
2783 get_extra_dimm_mask(ctrl, meminfo); // will be used by RDqsEn and dimm_x4
2784 /* DRAM Timing Low Register */
2786 /* DRAM Timing High Register */
2787 set_TrwtTO(ctrl, param);
2788 set_Twrrd (ctrl, param);
2789 set_Twrwr (ctrl, param);
2790 set_Trdrd (ctrl, param);
2792 set_4RankRDimm(ctrl, param, meminfo);
2794 /* DRAM Config High */
2795 set_Tfaw(ctrl, param, meminfo);
2796 set_DcqBypassMax(ctrl, param);
2797 set_max_async_latency(ctrl, param);
2798 set_RDqsEn(ctrl, param, meminfo);
2800 /* DRAM Config Low */
2801 set_ecc(ctrl, param, meminfo);
2802 set_dimm_x4(ctrl, param, meminfo);
2803 set_DramTerm(ctrl, param, meminfo);
2805 /* DRAM Control Misc */
2806 set_idle_cycle_limit(ctrl, param);
2807 set_RdWrQByp(ctrl, param);
2809 return meminfo->dimm_mask;
2812 static void sdram_set_spd_registers(const struct mem_controller *ctrl,
2813 struct sys_info *sysinfo)
2815 struct spd_set_memclk_result result;
2816 const struct mem_param *param;
2817 struct mem_param paramx;
2818 struct mem_info *meminfo;
2820 if (!sysinfo->ctrl_present[ctrl->node_id]) {
2824 meminfo = &sysinfo->meminfo[ctrl->node_id];
2826 printk_debug("sdram_set_spd_registers: paramx :%p\n", ¶mx);
2828 activate_spd_rom(ctrl);
2829 meminfo->dimm_mask = spd_detect_dimms(ctrl);
2831 printk_raminit("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask);
2833 if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1)))
2835 printk_debug("No memory for this cpu\n");
2838 meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo);
2839 printk_raminit("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask);
2840 if (meminfo->dimm_mask == -1)
2843 meminfo->dimm_mask = spd_set_ram_size(ctrl, meminfo);
2844 printk_raminit("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask);
2845 if (meminfo->dimm_mask == -1)
2848 meminfo->dimm_mask = spd_handle_unbuffered_dimms(ctrl, meminfo);
2849 printk_raminit("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask);
2850 if (meminfo->dimm_mask == -1)
2853 result = spd_set_memclk(ctrl, meminfo);
2854 param = result.param;
2855 meminfo->dimm_mask = result.dimm_mask;
2856 printk_raminit("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask);
2857 if (meminfo->dimm_mask == -1)
2860 //store memclk set to sysinfo, incase we need rebuilt param again
2861 meminfo->memclk_set = param->dch_memclk;
2863 memcpy(¶mx, param, sizeof(paramx));
2865 paramx.divisor = get_exact_divisor(param->dch_memclk, paramx.divisor);
2867 meminfo->dimm_mask = spd_set_dram_timing(ctrl, ¶mx, meminfo);
2868 printk_raminit("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask);
2869 if (meminfo->dimm_mask == -1)
2872 order_dimms(ctrl, meminfo);
2876 /* Unrecoverable error reading SPD data */
2877 die("Unrecoverable error reading SPD data. No qualified DIMMs?");
2881 #define TIMEOUT_LOOPS 300000
2883 #include "raminit_f_dqs.c"
2885 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
2886 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i)
2889 uint32_t carry_over;
2891 uint32_t base, limit;
2896 carry_over = (4*1024*1024) - hole_startk;
2898 for (ii=controllers - 1;ii>i;ii--) {
2899 base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
2900 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2903 limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
2904 limit += (carry_over << 2 );
2905 base += (carry_over << 2 );
2906 for (j = 0; j < controllers; j++) {
2907 pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit);
2908 pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base );
2911 limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
2912 limit += (carry_over << 2);
2913 for (j = 0; j < controllers; j++) {
2914 pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit);
2917 base = pci_read_config32(dev, 0x40 + (i << 3));
2918 basek = (base & 0xffff0000) >> 2;
2919 if (basek == hole_startk) {
2920 //don't need set memhole here, because hole off set will be 0, overflow
2921 //so need to change base reg instead, new basek will be 4*1024*1024
2923 base |= (4*1024*1024)<<2;
2924 for (j = 0; j < controllers; j++) {
2925 pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
2928 hoist = /* hole start address */
2929 ((hole_startk << 10) & 0xff000000) +
2930 /* hole address to memory controller address */
2931 (((basek + carry_over) >> 6) & 0x0000ff00) +
2934 pci_write_config32(dev, 0xf0, hoist);
2940 static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
2943 uint32_t hole_startk;
2946 hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
2948 printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk);
2949 #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
2950 /* We need to double check if the hole_startk is valid, if it is equal
2951 to basek, we need to decrease it some */
2953 for (i=0; i<controllers; i++) {
2956 base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
2957 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2960 base_k = (base & 0xffff0000) >> 2;
2961 if (base_k == hole_startk) {
2962 /* decrease mem hole startk to make sure it is
2963 on middle of previous node */
2964 hole_startk -= (base_k - basek_pri) >> 1;
2965 break; //only one hole
2969 printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
2971 /* find node index that need do set hole */
2972 for (i=0; i < controllers; i++) {
2973 uint32_t base, limit;
2974 unsigned base_k, limit_k;
2975 base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
2976 if ((base & ((1 << 1) | (1 << 0))) != ((1 << 1) | (1 << 0))) {
2979 limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
2980 base_k = (base & 0xffff0000) >> 2;
2981 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
2982 if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
2984 hoist_memory(controllers, ctrl, hole_startk, i);
2985 end_k = memory_end_k(ctrl, controllers);
2986 set_top_mem(end_k, hole_startk);
2987 break; //only one hole
2994 #include "exit_from_self.c"
2996 static void sdram_enable(int controllers, const struct mem_controller *ctrl,
2997 struct sys_info *sysinfo)
3000 #ifdef ACPI_IS_WAKEUP_EARLY
3001 int suspend = acpi_is_wakeup_early();
3006 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3007 unsigned cpu_f0_f1[8];
3008 /* FIXME: How about 32 node machine later? */
3011 printk_debug("sdram_enable: tsc0[8]: %p", &tsc0[0]);
3015 /* Error if I don't have memory */
3016 if (memory_end_k(ctrl, controllers) == 0) {
3020 /* Before enabling memory start the memory clocks */
3021 for (i = 0; i < controllers; i++) {
3023 if (!sysinfo->ctrl_present[ i ])
3025 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
3027 /* if no memory installed, disabled the interface */
3028 if (sysinfo->meminfo[i].dimm_mask==0x00){
3029 dch |= DCH_DisDramInterface;
3030 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
3033 dch |= DCH_MemClkFreqVal;
3034 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
3035 /* address timing and Output driver comp Control */
3036 set_misc_timing(ctrl+i, sysinfo->meminfo+i );
3040 /* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */
3041 memreset(controllers, ctrl);
3043 /* lets override the rest of the routine */
3045 printk_debug("Wakeup!\n");
3046 exit_from_self(controllers, ctrl, sysinfo);
3047 printk_debug("Mem running !\n");
3051 for (i = 0; i < controllers; i++) {
3053 if (!sysinfo->ctrl_present[ i ])
3055 /* Skip everything if I don't have any memory on this controller */
3056 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
3057 if (!(dch & DCH_MemClkFreqVal)) {
3062 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
3063 if (dcl & DCL_DimmEccEn) {
3065 printk_spew("ECC enabled\n");
3066 mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
3068 if (dcl & DCL_Width128) {
3069 mnc |= MNC_CHIPKILL_EN;
3071 pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
3074 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3075 cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i);
3077 //Rev F0/F1 workaround
3079 /* Set the DqsRcvEnTrain bit */
3080 dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
3081 dword |= DC_DqsRcvEnTrain;
3082 pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
3088 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
3089 dcl |= DCL_InitDram;
3090 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
3093 for (i = 0; i < controllers; i++) {
3095 if (!sysinfo->ctrl_present[ i ])
3097 /* Skip everything if I don't have any memory on this controller */
3098 if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
3100 printk_debug("Initializing memory: ");
3103 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
3105 if ((loops & 1023) == 0) {
3108 } while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS));
3109 if (loops >= TIMEOUT_LOOPS) {
3110 printk_debug(" failed\n");
3114 /* Wait until it is safe to touch memory */
3116 dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
3117 } while(((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ );
3119 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3123 print_debug_dqs_tsc("\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
3124 print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2);
3126 if (tsc.lo<tsc0[i].lo) {
3129 tsc.lo -= tsc0[i].lo;
3130 tsc.hi -= tsc0[i].hi;
3132 tsc0[i].lo = tsc.lo;
3133 tsc0[i].hi = tsc.hi;
3135 print_debug_dqs_tsc(" dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
3138 printk_debug(" done\n");
3141 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
3142 /* init hw mem hole here */
3143 /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
3144 set_hw_mem_hole(controllers, ctrl);
3147 /* store tom to sysinfo, and it will be used by dqs_timing */
3151 msr = rdmsr(TOP_MEM);
3152 sysinfo->tom_k = ((msr.hi<<24) | (msr.lo>>8))>>2;
3155 msr = rdmsr(TOP_MEM2);
3156 sysinfo->tom2_k = ((msr.hi<<24)| (msr.lo>>8))>>2;
3159 for (i = 0; i < controllers; i++) {
3160 sysinfo->mem_trained[i] = 0;
3162 if (!sysinfo->ctrl_present[ i ])
3165 /* Skip everything if I don't have any memory on this controller */
3166 if (sysinfo->meminfo[i].dimm_mask==0x00)
3169 sysinfo->mem_trained[i] = 0x80; // mem need to be trained
3173 #if CONFIG_MEM_TRAIN_SEQ == 0
3174 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3175 dqs_timing(controllers, ctrl, tsc0, sysinfo);
3177 dqs_timing(controllers, ctrl, sysinfo);
3181 #if CONFIG_MEM_TRAIN_SEQ == 2
3182 /* need to enable mtrr, so dqs training could access the test address */
3183 setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
3186 for (i = 0; i < controllers; i++) {
3187 /* Skip everything if I don't have any memory on this controller */
3188 if (sysinfo->mem_trained[i]!=0x80)
3191 dqs_timing(i, &ctrl[i], sysinfo, 1);
3193 #if CONFIG_MEM_TRAIN_SEQ == 1
3194 break; // only train the first node with ram
3198 #if CONFIG_MEM_TRAIN_SEQ == 2
3199 clear_mtrr_dqs(sysinfo->tom2_k);
3204 #if CONFIG_MEM_TRAIN_SEQ != 1
3205 wait_all_core0_mem_trained(sysinfo);
3210 static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
3211 const uint16_t *spd_addr)
3215 struct mem_controller *ctrl;
3216 for (i=0;i<controllers; i++) {
3219 ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
3220 ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
3221 ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
3222 ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
3224 if (spd_addr == (void *)0) continue;
3226 for (j=0;j<DIMM_SOCKETS;j++) {
3227 ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
3228 ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];