2 * This file is part of the coreboot project.
4 * Copyright (C) 2002 Linux Networx
5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
6 * Copyright (C) 2004 YingHai Lu
7 * Copyright (C) 2008 Advanced Micro Devices, Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <cpu/x86/cache.h>
24 #include <cpu/x86/mtrr.h>
25 #include <cpu/x86/tsc.h>
32 #ifndef QRANK_DIMM_SUPPORT
33 #define QRANK_DIMM_SUPPORT 0
37 #define printk_raminit(fmt, arg...) printk(BIOS_DEBUG, fmt, arg)
39 #define printk_raminit(fmt, arg...)
43 #if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
44 # error "CONFIG_RAMTOP must be a power of 2"
47 #include "amdk8_f_pci.c"
50 /* for PCI_ADDR(0, 0x18, 2, 0x98) index,
51 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
54 [29: 0] DctOffset (Dram Controller Offset)
55 [30:30] DctAccessWrite (Dram Controller Read/Write Select)
58 [31:31] DctAccessDone (Dram Controller Access Done)
59 0 = Access in progress
60 1 = No access is progress
63 [31: 0] DctOffsetData (Dram Controller Offset Data)
66 - Write the register num to DctOffset with
68 - poll the DctAccessDone until it = 1
69 - Read the data from DctOffsetData
71 - Write the data to DctOffsetData
72 - Write register num to DctOffset with DctAccessWrite = 1
73 - poll the DctAccessDone untio it = 1
77 static void setup_resource_map(const unsigned int *register_values, int max)
80 for (i = 0; i < max; i += 3) {
84 dev = register_values[i] & ~0xff;
85 where = register_values[i] & 0xff;
86 reg = pci_read_config32(dev, where);
87 reg &= register_values[i+1];
88 reg |= register_values[i+2];
89 pci_write_config32(dev, where, reg);
93 static int controller_present(const struct mem_controller *ctrl)
95 return pci_read_config32(ctrl->f0, 0) == 0x11001022;
98 static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
100 static const unsigned int register_values[] = {
102 /* Careful set limit registers before base registers which
103 contain the enables */
104 /* DRAM Limit i Registers
113 * [ 2: 0] Destination Node ID
123 * [10: 8] Interleave select
124 * specifies the values of A[14:12] to use with interleave enable.
126 * [31:16] DRAM Limit Address i Bits 39-24
127 * This field defines the upper address bits of a 40 bit address
128 * that define the end of the DRAM region.
130 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
131 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
132 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
133 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
134 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
135 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
136 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
137 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
138 /* DRAM Base i Registers
147 * [ 0: 0] Read Enable
150 * [ 1: 1] Write Enable
151 * 0 = Writes Disabled
154 * [10: 8] Interleave Enable
155 * 000 = No interleave
156 * 001 = Interleave on A[12] (2 nodes)
158 * 011 = Interleave on A[12] and A[14] (4 nodes)
162 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
164 * [13:16] DRAM Base Address i Bits 39-24
165 * This field defines the upper address bits of a 40-bit address
166 * that define the start of the DRAM region.
168 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
169 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
170 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
171 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
172 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
173 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
174 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
175 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
177 /* DRAM CS Base Address i Registers
186 * [ 0: 0] Chip-Select Bank Enable
190 * [ 2: 2] Memory Test Failed
192 * [13: 5] Base Address (21-13)
193 * An optimization used when all DIMM are the same size...
195 * [28:19] Base Address (36-27)
196 * This field defines the top 11 addresses bit of a 40-bit
197 * address that define the memory address space. These
198 * bits decode 32-MByte blocks of memory.
201 PCI_ADDR(0, 0x18, 2, 0x40), 0xe007c018, 0x00000000,
202 PCI_ADDR(0, 0x18, 2, 0x44), 0xe007c018, 0x00000000,
203 PCI_ADDR(0, 0x18, 2, 0x48), 0xe007c018, 0x00000000,
204 PCI_ADDR(0, 0x18, 2, 0x4C), 0xe007c018, 0x00000000,
205 PCI_ADDR(0, 0x18, 2, 0x50), 0xe007c018, 0x00000000,
206 PCI_ADDR(0, 0x18, 2, 0x54), 0xe007c018, 0x00000000,
207 PCI_ADDR(0, 0x18, 2, 0x58), 0xe007c018, 0x00000000,
208 PCI_ADDR(0, 0x18, 2, 0x5C), 0xe007c018, 0x00000000,
209 /* DRAM CS Mask Address i Registers
214 * Select bits to exclude from comparison with the DRAM Base address register.
216 * [13: 5] Address Mask (21-13)
217 * Address to be excluded from the optimized case
219 * [28:19] Address Mask (36-27)
220 * The bits with an address mask of 1 are excluded from address comparison
224 PCI_ADDR(0, 0x18, 2, 0x60), 0xe007c01f, 0x00000000,
225 PCI_ADDR(0, 0x18, 2, 0x64), 0xe007c01f, 0x00000000,
226 PCI_ADDR(0, 0x18, 2, 0x68), 0xe007c01f, 0x00000000,
227 PCI_ADDR(0, 0x18, 2, 0x6C), 0xe007c01f, 0x00000000,
229 /* DRAM Control Register
231 * [ 3: 0] RdPtrInit ( Read Pointer Initial Value)
232 * 0x03-0x00: reserved
233 * [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO)
236 * 010 = 1.5 Memory Clocks
237 * 011 = 2 Memory Clocks
238 * 100 = 2.5 Memory Clocks
239 * 101 = 3 Memory Clocks
240 * 110 = 3.5 Memory Clocks
243 * [16:16] AltVidC3MemClkTriEn (AltVID Memory Clock Tristate Enable)
244 * Enables the DDR memory clocks to be tristated when alternate VID
245 * mode is enabled. This bit has no effect if the DisNbClkRamp bit
247 * [17:17] DllTempAdjTime (DLL Temperature Adjust Cycle Time)
250 * [18:18] DqsRcvEnTrain (DQS Receiver Enable Training Mode)
251 * 0 = Normal DQS Receiver enable operation
252 * 1 = DQS receiver enable training mode
255 PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6<<4)|(6<<0),
257 /* DRAM Initialization Register
259 * [15: 0] MrsAddress (Address for MRS/EMRS Commands)
260 * this field specifies the dsata driven on the DRAM address pins
261 * 15-0 for MRS and EMRS commands
262 * [18:16] MrsBank (Bank Address for MRS/EMRS Commands)
263 * this files specifies the data driven on the DRAM bank pins for
264 * the MRS and EMRS commands
266 * [24:24] SendPchgAll (Send Precharge All Command)
267 * Setting this bit causes the DRAM controller to send a precharge
268 * all command. This bit is cleared by the hardware after the
270 * [25:25] SendAutoRefresh (Send Auto Refresh Command)
271 * Setting this bit causes the DRAM controller to send an auto
272 * refresh command. This bit is cleared by the hardware after the
274 * [26:26] SendMrsCmd (Send MRS/EMRS Command)
275 * Setting this bit causes the DRAM controller to send the MRS or
276 * EMRS command defined by the MrsAddress and MrsBank fields. This
277 * bit is cleared by the hardware adter the commmand completes
278 * [27:27] DeassertMemRstX (De-assert Memory Reset)
279 * Setting this bit causes the DRAM controller to de-assert the
280 * memory reset pin. This bit cannot be used to assert the memory
282 * [28:28] AssertCke (Assert CKE)
283 * setting this bit causes the DRAM controller to assert the CKE
284 * pins. This bit cannot be used to de-assert the CKE pins
286 * [31:31] EnDramInit (Enable DRAM Initialization)
287 * Setting this bit puts the DRAM controller in a BIOS controlled
288 * DRAM initialization mode. BIOS must clear this bit aster DRAM
289 * initialization is complete.
291 // PCI_ADDR(0, 0x18, 2, 0x7C), 0x60f80000, 0,
294 /* DRAM Bank Address Mapping Register
296 * Specify the memory module size
316 PCI_ADDR(0, 0x18, 2, 0x80), 0xffff0000, 0x00000000,
317 /* DRAM Timing Low Register
319 * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid)
329 * [ 5: 4] Trcd (Ras#-active to Cas# read/write delay)
335 * [ 9: 8] Trp (Row Precharge Time, Precharge-to-Active or Auto-Refresh)
341 * [11:11] Trtp (Read to Precharge Time, read Cas# to precharge time)
342 * 0 = 2 clocks for Burst Length of 32 Bytes
343 * 4 clocks for Burst Length of 64 Bytes
344 * 1 = 3 clocks for Burst Length of 32 Bytes
345 * 5 clocks for Burst Length of 64 Bytes
346 * [15:12] Tras (Minimum Ras# Active Time)
349 * 0010 = 5 bus clocks
351 * 1111 = 18 bus clocks
352 * [19:16] Trc (Row Cycle Time, Ras#-active to Ras#-active or auto
353 * refresh of the same bank)
354 * 0000 = 11 bus clocks
355 * 0010 = 12 bus clocks
357 * 1110 = 25 bus clocks
358 * 1111 = 26 bus clocks
359 * [21:20] Twr (Write Recovery Time, From the last data to precharge,
360 * writes can go back-to-back)
365 * [23:22] Trrd (Active-to-active(Ras#-to-Ras#) Delay of different banks)
370 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A,
371 * BIOS should set it to reduce the power consumption)
372 * Bit F(1207) M2 Package S1g1 Package
374 * 1 N/A MA0_CLK1 MA0_CLK1
377 * 4 MA1_CLK MA1_CLK0 N/A
378 * 5 MA0_CLK MA0_CLK0 MA0_CLK0
380 * 7 N/A MA0_CLK2 MA0_CLK2
382 PCI_ADDR(0, 0x18, 2, 0x88), 0x000004c8, 0xff000002 /* 0x03623125 */ ,
383 /* DRAM Timing High Register
386 * [ 6: 4] TrwtTO (Read-to-Write Turnaround for Data, DQS Contention)
396 * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay,
397 * minium write-to-read delay when both access the same chip select)
402 * [11:10] Twrrd (Write to Read DIMM Termination Turnaround, minimum
403 * write-to-read delay when accessing two different DIMMs)
408 * [13:12] Twrwr (Write to Write Timing)
409 * 00 = 1 bus clocks ( 0 idle cycle on the bus)
410 * 01 = 2 bus clocks ( 1 idle cycle on the bus)
411 * 10 = 3 bus clocks ( 2 idle cycles on the bus)
413 * [15:14] Trdrd ( Read to Read Timing)
414 * 00 = 2 bus clocks ( 1 idle cycle on the bus)
415 * 01 = 3 bus clocks ( 2 idle cycles on the bus)
416 * 10 = 4 bus clocks ( 3 idle cycles on the bus)
417 * 11 = 5 bus clocks ( 4 idel cycles on the bus)
418 * [17:16] Tref (Refresh Rate)
419 * 00 = Undefined behavior
421 * 10 = Refresh interval of 7.8 microseconds
422 * 11 = Refresh interval of 3.9 microseconds
424 * [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0,
425 * based on DRAM density and speed)
426 * 000 = 75 ns (all speeds, 256Mbit)
427 * 001 = 105 ns (all speeds, 512Mbit)
428 * 010 = 127.5 ns (all speeds, 1Gbit)
429 * 011 = 195 ns (all speeds, 2Gbit)
430 * 100 = 327.5 ns (all speeds, 4Gbit)
434 * [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1,
435 * based on DRAM density and speed)
436 * [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2,
437 * based on DRAM density and speed)
438 * [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3,
439 * based on DRAM density and speed)
441 PCI_ADDR(0, 0x18, 2, 0x8c), 0x000c008f, (2 << 16)|(1 << 8),
442 /* DRAM Config Low Register
444 * [ 0: 0] InitDram (Initialize DRAM)
445 * 1 = write 1 cause DRAM controller to execute the DRAM
446 * initialization, when done it read to 0
447 * [ 1: 1] ExitSelfRef ( Exit Self Refresh Command )
448 * 1 = write 1 causes the DRAM controller to bring the DRAMs out
449 * for self refresh mode
451 * [ 5: 4] DramTerm (DRAM Termination)
452 * 00 = On die termination disabled
457 * [ 7: 7] DramDrvWeak ( DRAM Drivers Weak Mode)
458 * 0 = Normal drive strength mode.
459 * 1 = Weak drive strength mode
460 * [ 8: 8] ParEn (Parity Enable)
461 * 1 = Enable address parity computation output, PAR,
462 * and enables the parity error input, ERR
463 * [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable)
464 * 1 = Enable high temperature ( two times normal )
466 * [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes)
469 * [11:11] Width128 ( Width of DRAM interface)
470 * 0 = the controller DRAM interface is 64-bits wide
471 * 1 = the controller DRAM interface is 128-bits wide
472 * [12:12] X4Dimm (DIMM 0 is x4)
473 * [13:13] X4Dimm (DIMM 1 is x4)
474 * [14:14] X4Dimm (DIMM 2 is x4)
475 * [15:15] X4Dimm (DIMM 3 is x4)
477 * 1 = x4 DIMM present
478 * [16:16] UnBuffDimm ( Unbuffered DIMMs)
480 * 1 = Unbuffered DIMMs
482 * [19:19] DimmEccEn ( DIMM ECC Enable )
483 * 1 = ECC checking is being enabled for all DIMMs on the DRAM
484 * controller ( Through F3 0x44[EccEn])
487 PCI_ADDR(0, 0x18, 2, 0x90), 0xfff6004c, 0x00000010,
488 /* DRAM Config High Register
490 * [ 0: 2] MemClkFreq ( Memory Clock Frequency)
496 * [ 3: 3] MemClkFreqVal (Memory Clock Freqency Valid)
497 * 1 = BIOS need to set the bit when setting up MemClkFreq to
499 * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency)
504 * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8
505 * registered DIMMs are present in the system
506 * 0 = DM pins function as data mask pins
507 * 1 = DM pins function as read DQS pins
509 * [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit
510 * is set, the DRAM controller is disabled, and interface in low power
512 * 0 = Enabled (default)
514 * [15:15] PowerDownEn ( Power Down Mode Enable )
515 * 0 = Disabled (default)
517 * [16:16] PowerDown ( Power Down Mode )
518 * 0 = Channel CKE Control
519 * 1 = Chip Select CKE Control
520 * [17:17] FourRankSODimm (Four Rank SO-DIMM)
521 * 1 = this bit is set by BIOS to indicate that a four rank
523 * [18:18] FourRankRDimm (Four Rank Registered DIMM)
524 * 1 = this bit is set by BIOS to indicate that a four rank
525 * registered DIMM is present
527 * [20:20] SlowAccessMode (Slow Access Mode (2T Mode))
528 * 0 = DRAM address and control signals are driven for one
530 * 1 = One additional MEMCLK of setup time is provided on all
531 * DRAM address and control signals except CS, CKE, and ODT;
532 * i.e., these signals are drivern for two MEMCLK cycles
535 * [22:22] BankSwizzleMode ( Bank Swizzle Mode),
536 * 0 = Disabled (default)
539 * [27:24] DcqBypassMax ( DRAM Controller Queue Bypass Maximum)
540 * 0000 = No bypass; the oldest request is never bypassed
541 * 0001 = The oldest request may be bypassed no more than 1 time
543 * 1111 = The oldest request may be bypassed no more than 15\
545 * [31:28] FourActWindow ( Four Bank Activate Window) , not more than
546 * 4 banks in a 8 bank device are activated
547 * 0000 = No tFAW window restriction
548 * 0001 = 8 MEMCLK cycles
549 * 0010 = 9 MEMCLK cycles
551 * 1101 = 20 MEMCLK cycles
554 PCI_ADDR(0, 0x18, 2, 0x94), 0x00a82f00,0x00008000,
555 /* DRAM Delay Line Register
557 * [ 0: 0] MemClrStatus (Memory Clear Status) : Readonly
558 * when set, this bit indicates that the memory clear function
559 * is complete. Only clear by reset. BIOS should not write or
560 * read the DRAM until this bit is set by hardware
561 * [ 1: 1] DisableJitter ( Disable Jitter)
562 * When set the DDR compensation circuit will not change the
563 * values unless the change is more than one step from the
565 * [ 3: 2] RdWrQByp ( Read/Write Queue Bypass Count)
570 * [ 4: 4] Mode64BitMux (Mismatched DIMM Support Enable)
571 * 1 When bit enables support for mismatched DIMMs when using
572 * 128-bit DRAM interface, the Width128 no effect, only for
574 * [ 5: 5] DCC_EN ( Dynamica Idle Cycle Counter Enable)
575 * When set to 1, indicates that each entry in the page tables
576 * dynamically adjusts the idle cycle limit based on page
577 * Conflict/Page Miss (PC/PM) traffic
578 * [ 8: 6] ILD_lmt ( Idle Cycle Limit)
587 * [ 9: 9] DramEnabled ( DRAM Enabled)
588 * When Set, this bit indicates that the DRAM is enabled, this
589 * bit is set by hardware after DRAM initialization or on an exit
590 * from self refresh. The DRAM controller is intialized after the
591 * hardware-controlled initialization process ( initiated by the
592 * F2 0x90[DramInit]) completes or when the BIOS-controlled
593 * initialization process completes (F2 0x7c(EnDramInit] is
594 * written from 1 to 0)
596 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B,
597 * BIOS should set it to reduce the power consumption)
598 * Bit F(1207) M2 Package S1g1 Package
600 * 1 N/A MA0_CLK1 MA0_CLK1
603 * 4 MA1_CLK MA1_CLK0 N/A
604 * 5 MA0_CLK MA0_CLK0 MA0_CLK0
606 * 7 N/A MA0_CLK2 MA0_CLK2
608 PCI_ADDR(0, 0x18, 2, 0xa0), 0x00fffc00, 0xff000000,
610 /* DRAM Scrub Control Register
612 * [ 4: 0] DRAM Scrube Rate
614 * [12: 8] L2 Scrub Rate
616 * [20:16] Dcache Scrub
619 * 00000 = Do not scrub
641 * All Others = Reserved
643 PCI_ADDR(0, 0x18, 3, 0x58), 0xffe0e0e0, 0x00000000,
644 /* DRAM Scrub Address Low Register
646 * [ 0: 0] DRAM Scrubber Redirect Enable
648 * 1 = Scrubber Corrects errors found in normal operation
650 * [31: 6] DRAM Scrub Address 31-6
652 PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000,
653 /* DRAM Scrub Address High Register
655 * [ 7: 0] DRAM Scrubb Address 39-32
658 PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
660 /* for PCI_ADDR(0, 0x18, 2, 0x98) index,
661 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
664 [29: 0] DctOffset (Dram Controller Offset)
665 [30:30] DctAccessWrite (Dram Controller Read/Write Select)
668 [31:31] DctAccessDone (Dram Controller Access Done)
669 0 = Access in progress
670 1 = No access is progress
673 [31: 0] DctOffsetData (Dram Controller Offset Data)
676 - Write the register num to DctOffset with DctAccessWrite = 0
677 - poll the DctAccessDone until it = 1
678 - Read the data from DctOffsetData
680 - Write the data to DctOffsetData
681 - Write register num to DctOffset with DctAccessWrite = 1
682 - poll the DctAccessDone untio it = 1
688 if (!controller_present(ctrl)) {
689 sysinfo->ctrl_present[ctrl->node_id] = 0;
692 sysinfo->ctrl_present[ctrl->node_id] = 1;
694 printk(BIOS_SPEW, "setting up CPU %02x northbridge registers\n", ctrl->node_id);
695 max = ARRAY_SIZE(register_values);
696 for (i = 0; i < max; i += 3) {
700 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
701 where = register_values[i] & 0xff;
702 reg = pci_read_config32(dev, where);
703 reg &= register_values[i+1];
704 reg |= register_values[i+2];
705 pci_write_config32(dev, where, reg);
707 printk(BIOS_SPEW, "done.\n");
710 static int is_dual_channel(const struct mem_controller *ctrl)
713 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
714 return dcl & DCL_Width128;
717 static int is_opteron(const struct mem_controller *ctrl)
719 /* Test to see if I am an Opteron.
720 * FIXME Testing dual channel capability is correct for now
721 * but a better test is probably required.
722 * m2 and s1g1 support dual channel too. but only support unbuffered dimm
724 #warning "FIXME implement a better test for opterons"
726 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
727 return !!(nbcap & NBCAP_128Bit);
730 static int is_registered(const struct mem_controller *ctrl)
732 /* Test to see if we are dealing with registered SDRAM.
733 * If we are not registered we are unbuffered.
734 * This function must be called after spd_handle_unbuffered_dimms.
737 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
738 return !(dcl & DCL_UnBuffDimm);
742 static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
744 /* Calculate the log base 2 size of a DIMM in bits */
751 value = spd_read_byte(device, SPD_ROW_NUM); /* rows */
752 if (value < 0) goto hw_err;
753 if ((value & 0xff) == 0) goto val_err; /* max is 16 ? */
754 sz->per_rank += value & 0xff;
755 sz->rows = value & 0xff;
757 value = spd_read_byte(device, SPD_COL_NUM); /* columns */
758 if (value < 0) goto hw_err;
759 if ((value & 0xff) == 0) goto val_err; /* max is 11 */
760 sz->per_rank += value & 0xff;
761 sz->col = value & 0xff;
763 value = spd_read_byte(device, SPD_BANK_NUM); /* banks */
764 if (value < 0) goto hw_err;
765 if ((value & 0xff) == 0) goto val_err;
766 sz->bank = log2(value & 0xff); // convert 4 to 2, and 8 to 3
767 sz->per_rank += sz->bank;
769 /* Get the module data width and convert it to a power of two */
770 value = spd_read_byte(device, SPD_DATA_WIDTH);
771 if (value < 0) goto hw_err;
773 if ((value != 72) && (value != 64)) goto val_err;
774 sz->per_rank += log2(value) - 3; //64 bit So another 3 lines
776 /* How many ranks? */
777 /* number of physical banks */
778 value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK);
779 if (value < 0) goto hw_err;
780 /* value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT; */
781 value &= SPD_MOD_ATTRIB_RANK_NUM_MASK;
782 value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4
784 rank == 1 only one rank or say one side
785 rank == 2 two side , and two ranks
786 rank == 4 two side , and four ranks total
787 Some one side two ranks, because of stacked
789 if ((value != 1) && (value != 2) && (value != 4 )) {
794 /* verify if per_rank is equal byte 31
795 it has the DIMM size as a multiple of 128MB.
797 value = spd_read_byte(device, SPD_RANK_SIZE);
798 if (value < 0) goto hw_err;
801 if (value <=4 ) value += 8; // add back to 1G to high
802 value += (27-5); // make 128MB to the real lines
803 if ( value != (sz->per_rank)) {
804 printk(BIOS_ERR, "Bad RANK Size --\n");
811 die("Bad SPD value\n");
812 /* If an hw_error occurs report that I have no memory */
824 static void set_dimm_size(const struct mem_controller *ctrl,
825 struct dimm_size *sz, unsigned index,
826 struct mem_info *meminfo)
828 uint32_t base0, base1;
830 /* For each base register.
831 * Place the dimm size in 32 MB quantities in the bits 31 - 21.
832 * The initialize dimm size is in bits.
833 * Set the base enable bit0.
838 /* Make certain side1 of the dimm is at least 128MB */
839 if (sz->per_rank >= 27) {
840 base0 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
843 /* Make certain side2 of the dimm is at least 128MB */
844 if (sz->rank > 1) { // 2 ranks or 4 ranks
845 base1 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
848 /* Double the size if we are using dual channel memory */
849 if (meminfo->is_Width128) {
850 base0 = (base0 << 1) | (base0 & 1);
851 base1 = (base1 << 1) | (base1 & 1);
854 /* Clear the reserved bits */
855 base0 &= ~0xe007fffe;
856 base1 &= ~0xe007fffe;
858 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
859 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
860 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
862 /* Set the appropriate DIMM base address register */
863 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0);
864 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1);
865 #if QRANK_DIMM_SUPPORT == 1
867 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
868 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
873 /* Enable the memory clocks for this DIMM by Clear the MemClkDis bit*/
877 #if CONFIG_CPU_SOCKET_TYPE == 0x10 /* L1 */
878 ClkDis0 = DTL_MemClkDis0;
879 #elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM2 */
880 ClkDis0 = DTL_MemClkDis0_AM2;
881 #elif CONFIG_CPU_SOCKET_TYPE == 0x12 /* S1G1 */
882 ClkDis0 = DTL_MemClkDis0_S1g1;
885 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
886 dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
887 dword &= ~(ClkDis0 >> index);
888 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
891 dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
892 dword &= ~(ClkDis0 >> index);
893 #if QRANK_DIMM_SUPPORT == 1
895 dword &= ~(ClkDis0 >> (index+2));
898 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dword);
900 if (meminfo->is_Width128) { // ChannelA+B
901 dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
902 dword &= ~(ClkDis0 >> index);
903 #if QRANK_DIMM_SUPPORT == 1
905 dword &= ~(ClkDis0 >> (index+2));
908 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
915 /* row col bank for 64 bit
931 static void set_dimm_cs_map(const struct mem_controller *ctrl,
932 struct dimm_size *sz, unsigned index,
933 struct mem_info *meminfo)
935 static const uint8_t cs_map_aaa[24] = {
936 /* (bank=2, row=13, col=9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */
951 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
954 map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
955 map &= ~(0xf << (index * 4));
956 #if QRANK_DIMM_SUPPORT == 1
958 map &= ~(0xf << ( (index + 2) * 4));
962 /* Make certain side1 of the dimm is at least 128MB */
963 if (sz->per_rank >= 27) {
965 temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ];
966 map |= temp_map << (index*4);
967 #if QRANK_DIMM_SUPPORT == 1
969 map |= temp_map << ( (index + 2) * 4);
974 pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
979 static long spd_set_ram_size(const struct mem_controller *ctrl,
980 struct mem_info *meminfo)
984 for (i = 0; i < DIMM_SOCKETS; i++) {
985 struct dimm_size *sz = &(meminfo->sz[i]);
986 u32 spd_device = ctrl->channel0[i];
988 if (!(meminfo->dimm_mask & (1 << i))) {
989 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
990 spd_device = ctrl->channel1[i];
996 spd_get_dimm_size(spd_device, sz);
997 if (sz->per_rank == 0) {
998 return -1; /* Report SPD error */
1000 set_dimm_size(ctrl, sz, i, meminfo);
1001 set_dimm_cs_map(ctrl, sz, i, meminfo);
1003 return meminfo->dimm_mask;
1006 static void route_dram_accesses(const struct mem_controller *ctrl,
1007 unsigned long base_k, unsigned long limit_k)
1009 /* Route the addresses to the controller node */
1014 unsigned limit_reg, base_reg;
1017 node_id = ctrl->node_id;
1018 index = (node_id << 3);
1019 limit = (limit_k << 2);
1020 limit &= 0xffff0000;
1021 limit -= 0x00010000;
1022 limit |= ( 0 << 8) | (node_id << 0);
1023 base = (base_k << 2);
1025 base |= (0 << 8) | (1<<1) | (1<<0);
1027 limit_reg = 0x44 + index;
1028 base_reg = 0x40 + index;
1029 for (device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1);
1030 device += PCI_DEV(0, 1, 0)) {
1031 pci_write_config32(device, limit_reg, limit);
1032 pci_write_config32(device, base_reg, base);
1036 static void set_top_mem(unsigned tom_k, unsigned hole_startk)
1038 /* Error if I don't have memory */
1043 /* Report the amount of memory. */
1044 printk(BIOS_DEBUG, "RAM end at 0x%08x kB\n", tom_k);
1046 /* Now set top of memory */
1048 if (tom_k > (4*1024*1024)) {
1049 printk_raminit("Handling memory mapped above 4 GB\n");
1050 printk_raminit("Upper RAM end at 0x%08x kB\n", tom_k);
1051 msr.lo = (tom_k & 0x003fffff) << 10;
1052 msr.hi = (tom_k & 0xffc00000) >> 22;
1053 wrmsr(TOP_MEM2, msr);
1054 printk_raminit("Correcting memory amount mapped below 4 GB\n");
1057 /* Leave a 64M hole between TOP_MEM and TOP_MEM2
1058 * so I can see my rom chip and other I/O devices.
1060 if (tom_k >= 0x003f0000) {
1061 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
1062 if (hole_startk != 0) {
1063 tom_k = hole_startk;
1067 printk_raminit("Adjusting lower RAM end\n");
1069 printk_raminit("Lower RAM end at 0x%08x kB\n", tom_k);
1070 msr.lo = (tom_k & 0x003fffff) << 10;
1071 msr.hi = (tom_k & 0xffc00000) >> 22;
1072 wrmsr(TOP_MEM, msr);
1075 static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, int is_Width128)
1079 static const uint8_t csbase_low_f0_shift[] = {
1080 /* 128MB */ (14 - (13-5)),
1081 /* 256MB */ (15 - (13-5)),
1082 /* 512MB */ (15 - (13-5)),
1083 /* 512MB */ (16 - (13-5)),
1084 /* 512MB */ (16 - (13-5)),
1085 /* 1GB */ (16 - (13-5)),
1086 /* 1GB */ (16 - (13-5)),
1087 /* 2GB */ (16 - (13-5)),
1088 /* 2GB */ (17 - (13-5)),
1089 /* 4GB */ (17 - (13-5)),
1090 /* 4GB */ (16 - (13-5)),
1091 /* 8GB */ (17 - (13-5)),
1094 /* cs_base_high is not changed */
1096 uint32_t csbase_inc;
1097 int chip_selects, index;
1099 unsigned common_size;
1100 unsigned common_cs_mode;
1101 uint32_t csbase, csmask;
1103 /* See if all of the memory chip selects are the same size
1104 * and if so count them.
1108 common_cs_mode = 0xff;
1109 for (index = 0; index < 8; index++) {
1114 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1116 /* Is it enabled? */
1121 size = (value >> 19) & 0x3ff;
1122 if (common_size == 0) {
1125 /* The size differed fail */
1126 if (common_size != size) {
1130 value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
1131 cs_mode =( value >> ((index>>1)*4)) & 0xf;
1132 if (common_cs_mode == 0xff) {
1133 common_cs_mode = cs_mode;
1135 /* The cs_mode differed fail */
1136 if (common_cs_mode != cs_mode) {
1141 /* Chip selects can only be interleaved when there is
1142 * more than one and their is a power of two of them.
1144 bits = log2(chip_selects);
1145 if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) {
1146 //chip_selects max = 8
1150 /* Find the bits of csbase that we need to interleave on */
1151 csbase_inc = 1 << (csbase_low_f0_shift[common_cs_mode]);
1156 /* Compute the initial values for csbase and csbask.
1157 * In csbase just set the enable bit and the base to zero.
1158 * In csmask set the mask bits for the size and page level interleave.
1161 csmask = (((common_size << bits) - 1) << 19);
1162 csmask |= 0x3fe0 & ~((csbase_inc << bits) - csbase_inc);
1163 for (index = 0; index < 8; index++) {
1166 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1167 /* Is it enabled? */
1171 pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
1172 if ((index & 1) == 0) { //only have 4 CSMASK
1173 pci_write_config32(ctrl->f2, DRAM_CSMASK + ((index>>1) << 2), csmask);
1175 csbase += csbase_inc;
1178 printk(BIOS_DEBUG, "Interleaved\n");
1180 /* Return the memory size in K */
1181 return common_size << ((27-10) + bits);
1184 static unsigned long order_chip_selects(const struct mem_controller *ctrl)
1188 /* Remember which registers we have used in the high 8 bits of tom */
1191 /* Find the largest remaining canidate */
1192 unsigned index, canidate;
1193 uint32_t csbase, csmask;
1197 for (index = 0; index < 8; index++) {
1199 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1201 /* Is it enabled? */
1206 /* Is it greater? */
1207 if (value <= csbase) {
1211 /* Has it already been selected */
1212 if (tom & (1 << (index + 24))) {
1215 /* I have a new canidate */
1220 /* See if I have found a new canidate */
1225 /* Remember the dimm size */
1226 size = csbase >> 19;
1228 /* Remember I have used this register */
1229 tom |= (1 << (canidate + 24));
1231 /* Recompute the cs base register value */
1232 csbase = (tom << 19) | 1;
1234 /* Increment the top of memory */
1237 /* Compute the memory mask */
1238 csmask = ((size -1) << 19);
1239 csmask |= 0x3fe0; /* For now don't optimize */
1241 /* Write the new base register */
1242 pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
1243 /* Write the new mask register */
1244 if ((canidate & 1) == 0) { //only have 4 CSMASK
1245 pci_write_config32(ctrl->f2, DRAM_CSMASK + ((canidate >> 1) << 2), csmask);
1249 /* Return the memory size in K */
1250 return (tom & ~0xff000000) << (27-10);
1253 static unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
1257 /* Find the last memory address used */
1259 for (node_id = 0; node_id < max_node_id; node_id++) {
1260 uint32_t limit, base;
1262 index = node_id << 3;
1263 base = pci_read_config32(ctrl->f1, 0x40 + index);
1264 /* Only look at the limit if the base is enabled */
1265 if ((base & 3) == 3) {
1266 limit = pci_read_config32(ctrl->f1, 0x44 + index);
1267 end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
1273 static void order_dimms(const struct mem_controller *ctrl,
1274 struct mem_info *meminfo)
1276 unsigned long tom_k, base_k;
1278 if (read_option(CMOS_VSTART_interleave_chip_selects,
1279 CMOS_VLEN_interleave_chip_selects, 1) != 0) {
1280 tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
1282 printk(BIOS_DEBUG, "Interleaving disabled\n");
1287 tom_k = order_chip_selects(ctrl);
1290 /* Compute the memory base address */
1291 base_k = memory_end_k(ctrl, ctrl->node_id);
1293 route_dram_accesses(ctrl, base_k, tom_k);
1294 set_top_mem(tom_k, 0);
1297 static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
1298 struct mem_info *meminfo)
1300 printk(BIOS_DEBUG, "disabling dimm %02x\n", index);
1301 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
1302 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
1303 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
1305 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0);
1306 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0);
1307 #if QRANK_DIMM_SUPPORT == 1
1308 if (meminfo->sz[index].rank == 4) {
1309 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
1310 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
1315 meminfo->dimm_mask &= ~(1 << index);
1316 return meminfo->dimm_mask;
1319 static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
1320 struct mem_info *meminfo)
1323 uint32_t registered;
1326 for (i = 0; (i < DIMM_SOCKETS); i++) {
1328 u32 spd_device = ctrl->channel0[i];
1329 if (!(meminfo->dimm_mask & (1 << i))) {
1330 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1331 spd_device = ctrl->channel1[i];
1336 value = spd_read_byte(spd_device, SPD_DIMM_TYPE);
1341 /* Registered dimm ? */
1343 if ((value == SPD_DIMM_TYPE_RDIMM) || (value == SPD_DIMM_TYPE_mRDIMM)) {
1344 //check SPD_MOD_ATTRIB to verify it is SPD_MOD_ATTRIB_REGADC (0x11)?
1345 registered |= (1<<i);
1349 if (is_opteron(ctrl)) {
1351 if ( registered != (meminfo->dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) {
1352 meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffed dimm
1353 // die("Mixed buffered and registered dimms not supported");
1355 //By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM
1357 die("Unbuffered Dimms not supported on Opteron");
1363 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1364 dcl &= ~DCL_UnBuffDimm;
1365 meminfo->is_registered = 1;
1367 dcl |= DCL_UnBuffDimm;
1368 meminfo->is_registered = 0;
1370 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1372 if (meminfo->is_registered) {
1373 printk(BIOS_SPEW, "Registered\n");
1375 printk(BIOS_SPEW, "Unbuffered\n");
1377 return meminfo->dimm_mask;
1380 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
1385 for (i = 0; i < DIMM_SOCKETS; i++) {
1388 device = ctrl->channel0[i];
1389 printk_raminit("DIMM socket %i, channel 0 SPD device is 0x%02x\n", i, device);
1391 byte = spd_read_byte(ctrl->channel0[i], SPD_MEM_TYPE); /* Type */
1392 if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
1393 dimm_mask |= (1 << i);
1396 device = ctrl->channel1[i];
1397 printk_raminit("DIMM socket %i, channel 1 SPD device is 0x%02x\n", i, device);
1399 byte = spd_read_byte(ctrl->channel1[i], SPD_MEM_TYPE);
1400 if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
1401 dimm_mask |= (1 << (i + DIMM_SOCKETS));
1408 static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_info *meminfo)
1412 /* SPD addresses to verify are identical */
1413 static const uint8_t addresses[] = {
1414 2, /* Type should be DDR2 SDRAM */
1415 3, /* *Row addresses */
1416 4, /* *Column addresses */
1417 5, /* *Number of DIMM Ranks */
1418 6, /* *Module Data Width*/
1419 11, /* *DIMM Conf Type */
1420 13, /* *Pri SDRAM Width */
1421 17, /* *Logical Banks */
1422 20, /* *DIMM Type Info */
1423 21, /* *SDRAM Module Attributes */
1424 27, /* *tRP Row precharge time */
1425 28, /* *Minimum Row Active to Row Active Delay (tRRD) */
1426 29, /* *tRCD RAS to CAS */
1427 30, /* *tRAS Activate to Precharge */
1428 36, /* *Write recovery time (tWR) */
1429 37, /* *Internal write to read command delay (tRDP) */
1430 38, /* *Internal read to precharge command delay (tRTP) */
1431 40, /* *Extension of Byte 41 tRC and Byte 42 tRFC */
1432 41, /* *Minimum Active to Active/Auto Refresh Time(Trc) */
1433 42, /* *Minimum Auto Refresh Command Time(Trfc) */
1434 /* The SPD addresses 18, 9, 23, 26 need special treatment like
1435 * in spd_set_memclk. Right now they cause many false negatives.
1436 * Keep them at the end to see other mismatches (if any).
1438 18, /* *Supported CAS Latencies */
1439 9, /* *Cycle time at highest CAS Latency CL=X */
1440 23, /* *Cycle time at CAS Latency (CLX - 1) */
1441 26, /* *Cycle time at CAS Latency (CLX - 2) */
1446 /* S1G1 and AM2 sockets are Mod64BitMux capable. */
1447 #if CONFIG_CPU_SOCKET_TYPE == 0x11 || CONFIG_CPU_SOCKET_TYPE == 0x12
1453 /* If the dimms are not in pairs do not do dual channels */
1454 if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
1455 ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1456 goto single_channel;
1458 /* If the cpu is not capable of doing dual channels don't do dual channels */
1459 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1460 if (!(nbcap & NBCAP_128Bit)) {
1461 goto single_channel;
1463 for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
1464 unsigned device0, device1;
1467 /* If I don't have a dimm skip this one */
1468 if (!(meminfo->dimm_mask & (1 << i))) {
1471 device0 = ctrl->channel0[i];
1472 device1 = ctrl->channel1[i];
1473 /* Abort if the chips don't support a common CAS latency. */
1474 common_cl = spd_read_byte(device0, 18) & spd_read_byte(device1, 18);
1476 printk(BIOS_DEBUG, "No common CAS latency supported\n");
1477 goto single_channel;
1479 printk_raminit("Common CAS latency bitfield: 0x%02x\n", common_cl);
1481 for (j = 0; j < ARRAY_SIZE(addresses); j++) {
1483 addr = addresses[j];
1484 value0 = spd_read_byte(device0, addr);
1488 value1 = spd_read_byte(device1, addr);
1492 if (value0 != value1) {
1493 printk_raminit("SPD values differ between channel 0/1 for byte %i\n", addr);
1494 goto single_channel;
1498 printk(BIOS_SPEW, "Enabling dual channel memory\n");
1499 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1500 dcl &= ~DCL_BurstLength32; /* 32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses
1501 32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode */
1502 dcl |= DCL_Width128;
1503 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1504 meminfo->is_Width128 = 1;
1505 return meminfo->dimm_mask;
1508 meminfo->is_Width128 = 0;
1509 meminfo->is_64MuxMode = 0;
1512 if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
1513 ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1514 if (((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1515 /* mux capable and single dimm in channelB */
1517 printk(BIOS_SPEW, "Enable 64MuxMode & BurstLength32\n");
1518 dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
1519 dcm |= DCM_Mode64BitMux;
1520 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
1521 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1522 //dcl |= DCL_BurstLength32; /* 32byte mode for channelB only */
1523 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1524 meminfo->is_64MuxMode = 1;
1526 meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
1529 } else { /* unmatched dual dimms ? */
1530 /* unmatched dual dimms not supported by meminit code. Use single channelA dimm. */
1531 meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
1532 printk(BIOS_SPEW, "Unmatched dual dimms. Use single channelA dimm.\n");
1534 return meminfo->dimm_mask;
1538 uint16_t cycle_time;
1539 uint8_t divisor; /* In 1/40 ns increments */
1544 uint8_t DcqByPassMax;
1545 uint32_t dch_memclk;
1549 static const struct mem_param speed[] = {
1552 .cycle_time = 0x500,
1553 .divisor = 200, // how many 1/40ns per clock
1554 .dch_memclk = DCH_MemClkFreq_200MHz, //0
1564 .cycle_time = 0x375,
1565 .divisor = 150, //????
1566 .dch_memclk = DCH_MemClkFreq_266MHz, //1
1575 .cycle_time = 0x300,
1577 .dch_memclk = DCH_MemClkFreq_333MHz, //2
1587 .cycle_time = 0x250,
1589 .dch_memclk = DCH_MemClkFreq_400MHz,//3
1597 .cycle_time = 0x000,
1601 static const struct mem_param *get_mem_param(unsigned min_cycle_time)
1604 const struct mem_param *param;
1605 for (param = &speed[0]; param->cycle_time ; param++) {
1606 if (min_cycle_time > (param+1)->cycle_time) {
1610 if (!param->cycle_time) {
1611 die("min_cycle_time to low");
1613 printk(BIOS_SPEW, "%s\n", param->name);
1617 static uint8_t get_exact_divisor(int i, uint8_t divisor)
1619 //input divisor could be 200(200), 150(266), 120(333), 100 (400)
1620 static const uint8_t dv_a[] = {
1621 /* 200 266 333 400 */
1622 /*4 */ 250, 250, 250, 250,
1623 /*5 */ 200, 200, 200, 100,
1624 /*6 */ 200, 166, 166, 100,
1625 /*7 */ 200, 171, 142, 100,
1627 /*8 */ 200, 150, 125, 100,
1628 /*9 */ 200, 156, 133, 100,
1629 /*10*/ 200, 160, 120, 100,
1630 /*11*/ 200, 163, 127, 100,
1632 /*12*/ 200, 150, 133, 100,
1633 /*13*/ 200, 153, 123, 100,
1634 /*14*/ 200, 157, 128, 100,
1635 /*15*/ 200, 160, 120, 100,
1642 /* Check for FID control support */
1643 struct cpuid_result cpuid1;
1644 cpuid1 = cpuid(0x80000007);
1645 if( cpuid1.edx & 0x02 ) {
1646 /* Use current FID */
1648 msr = rdmsr(0xc0010042);
1649 fid_cur = msr.lo & 0x3f;
1653 /* Use startup FID */
1655 msr = rdmsr(0xc0010015);
1656 fid_start = (msr.lo & (0x3f << 24));
1658 index = fid_start>>25;
1661 if (index>12) return divisor;
1663 if (i>3) return divisor;
1665 return dv_a[index * 4+i];
1670 struct spd_set_memclk_result {
1671 const struct mem_param *param;
1676 static unsigned convert_to_linear(unsigned value)
1678 static const unsigned fraction[] = { 0x25, 0x33, 0x66, 0x75 };
1681 /* We need to convert value to more readable */
1682 if ((value & 0xf) < 10) { //no .25, .33, .66, .75
1685 valuex = ((value & 0xf0) << 4) | fraction [(value & 0xf)-10];
1691 static const uint8_t latency_indicies[] = { 25, 23, 9 };
1693 static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time)
1695 int new_cycle_time, new_latency;
1700 /* First find the supported CAS latencies
1701 * Byte 18 for DDR SDRAM is interpreted:
1702 * bit 3 == CAS Latency = 3
1703 * bit 4 == CAS Latency = 4
1704 * bit 5 == CAS Latency = 5
1705 * bit 6 == CAS Latency = 6
1707 new_cycle_time = 0x500;
1710 latencies = spd_read_byte(spd_device, SPD_CAS_LAT);
1714 printk_raminit("\tlatencies: %08x\n", latencies);
1715 /* Compute the lowest cas latency which can be expressed in this
1716 * particular SPD EEPROM. You can store at most settings for 3
1717 * contiguous CAS latencies, so by taking the highest CAS
1718 * latency maked as supported in the SPD and subtracting 2 you
1719 * get the lowest expressable CAS latency. That latency is not
1720 * necessarily supported, but a (maybe invalid) entry exists
1723 latency = log2(latencies) - 2;
1725 /* Loop through and find a fast clock with a low latency */
1726 for (index = 0; index < 3; index++, latency++) {
1728 if ((latency < 3) || (latency > 6) ||
1729 (!(latencies & (1 << latency)))) {
1732 value = spd_read_byte(spd_device, latency_indicies[index]);
1737 printk_raminit("\tindex: %08x\n", index);
1738 printk_raminit("\t\tlatency: %08x\n", latency);
1739 printk_raminit("\t\tvalue1: %08x\n", value);
1741 value = convert_to_linear(value);
1743 printk_raminit("\t\tvalue2: %08x\n", value);
1745 /* Only increase the latency if we decrease the clock */
1746 if (value >= *min_cycle_time ) {
1747 if (value < new_cycle_time) {
1748 new_cycle_time = value;
1749 new_latency = latency;
1750 } else if (value == new_cycle_time) {
1751 if (new_latency > latency) {
1752 new_latency = latency;
1756 printk_raminit("\t\tnew_cycle_time: %08x\n", new_cycle_time);
1757 printk_raminit("\t\tnew_latency: %08x\n", new_latency);
1761 if (new_latency > 6){
1765 /* Does min_latency need to be increased? */
1766 if (new_cycle_time > *min_cycle_time) {
1767 *min_cycle_time = new_cycle_time;
1770 /* Does min_cycle_time need to be increased? */
1771 if (new_latency > *min_latency) {
1772 *min_latency = new_latency;
1775 printk_raminit("2 min_cycle_time: %08x\n", *min_cycle_time);
1776 printk_raminit("2 min_latency: %08x\n", *min_latency);
1781 static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, struct mem_info *meminfo)
1783 /* Compute the minimum cycle time for these dimms */
1784 struct spd_set_memclk_result result;
1785 unsigned min_cycle_time, min_latency, bios_cycle_time;
1789 static const uint16_t min_cycle_times[] = { // use full speed to compare
1790 [NBCAP_MEMCLK_NOLIMIT] = 0x250, /*2.5ns */
1791 [NBCAP_MEMCLK_333MHZ] = 0x300, /* 3.0ns */
1792 [NBCAP_MEMCLK_266MHZ] = 0x375, /* 3.75ns */
1793 [NBCAP_MEMCLK_200MHZ] = 0x500, /* 5.0s */
1797 value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1798 min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
1799 bios_cycle_time = min_cycle_times[
1800 read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
1801 if (bios_cycle_time > min_cycle_time) {
1802 min_cycle_time = bios_cycle_time;
1806 printk_raminit("1 min_cycle_time: %08x\n", min_cycle_time);
1808 /* Compute the least latency with the fastest clock supported
1809 * by both the memory controller and the dimms.
1811 for (i = 0; i < DIMM_SOCKETS; i++) {
1814 printk_raminit("1.1 dimm_mask: %08x\n", meminfo->dimm_mask);
1815 printk_raminit("i: %08x\n",i);
1817 if (meminfo->dimm_mask & (1 << i)) {
1818 spd_device = ctrl->channel0[i];
1819 printk_raminit("Channel 0 settings:\n");
1821 switch (find_optimum_spd_latency(spd_device, &min_latency, &min_cycle_time)) {
1829 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) {
1830 spd_device = ctrl->channel1[i];
1831 printk_raminit("Channel 1 settings:\n");
1833 switch (find_optimum_spd_latency(spd_device, &min_latency, &min_cycle_time)) {
1843 /* Make a second pass through the dimms and disable
1844 * any that cannot support the selected memclk and cas latency.
1847 printk_raminit("3 min_cycle_time: %08x\n", min_cycle_time);
1848 printk_raminit("3 min_latency: %08x\n", min_latency);
1850 for (i = 0; (i < DIMM_SOCKETS); i++) {
1855 u32 spd_device = ctrl->channel0[i];
1857 if (!(meminfo->dimm_mask & (1 << i))) {
1858 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1859 spd_device = ctrl->channel1[i];
1865 latencies = spd_read_byte(spd_device, SPD_CAS_LAT);
1866 if (latencies < 0) goto hw_error;
1867 if (latencies == 0) {
1871 /* Compute the lowest cas latency supported */
1872 latency = log2(latencies) -2;
1874 /* Walk through searching for the selected latency */
1875 for (index = 0; index < 3; index++, latency++) {
1876 if (!(latencies & (1 << latency))) {
1879 if (latency == min_latency)
1882 /* If I can't find the latency or my index is bad error */
1883 if ((latency != min_latency) || (index >= 3)) {
1887 /* Read the min_cycle_time for this latency */
1888 val = spd_read_byte(spd_device, latency_indicies[index]);
1889 if (val < 0) goto hw_error;
1891 val = convert_to_linear(val);
1892 /* All is good if the selected clock speed
1893 * is what I need or slower.
1895 if (val <= min_cycle_time) {
1898 /* Otherwise I have an error, disable the dimm */
1900 meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo);
1903 printk_raminit("4 min_cycle_time: %08x\n", min_cycle_time);
1905 /* Now that I know the minimum cycle time lookup the memory parameters */
1906 result.param = get_mem_param(min_cycle_time);
1908 /* Update DRAM Config High with our selected memory speed */
1909 value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
1910 value &= ~(DCH_MemClkFreq_MASK << DCH_MemClkFreq_SHIFT);
1912 value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT;
1913 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
1915 printk(BIOS_DEBUG, "%s\n", result.param->name);
1917 /* Update DRAM Timing Low with our selected cas latency */
1918 value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1919 value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
1920 value |= (min_latency - DTL_TCL_BASE) << DTL_TCL_SHIFT;
1921 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
1923 result.dimm_mask = meminfo->dimm_mask;
1926 result.param = (const struct mem_param *)0;
1927 result.dimm_mask = -1;
1931 static unsigned convert_to_1_4(unsigned value)
1933 static const uint8_t fraction[] = { 0, 1, 2, 2, 3, 3, 0 };
1936 /* We need to convert value to more readable */
1937 valuex = fraction [value & 0x7];
1941 static int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param)
1946 value = spd_read_byte(spd_device, SPD_TRC);
1949 printk_raminit("update_dimm_Trc: tRC (41) = %08x\n", value);
1951 value2 = spd_read_byte(spd_device, SPD_TRC -1);
1953 value += convert_to_1_4(value2>>4);
1956 printk_raminit("update_dimm_Trc: tRC final value = %i\n", value);
1958 clocks = (value + param->divisor - 1)/param->divisor;
1959 printk_raminit("update_dimm_Trc: clocks = %i\n", clocks);
1961 if (clocks < DTL_TRC_MIN) {
1962 #warning We should die here or at least disable this bank.
1963 printk(BIOS_NOTICE, "update_dimm_Trc: can't refresh fast enough, "
1964 "want %i clocks, can %i clocks\n", clocks, DTL_TRC_MIN);
1965 clocks = DTL_TRC_MIN;
1970 static int update_dimm_Trc(const struct mem_controller *ctrl,
1971 const struct mem_param *param,
1972 int i, long dimm_mask)
1974 int clocks, old_clocks;
1976 u32 spd_device = ctrl->channel0[i];
1978 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
1979 spd_device = ctrl->channel1[i];
1982 clocks = get_dimm_Trc_clocks(spd_device, param);
1985 if (clocks > DTL_TRC_MAX) {
1988 printk_raminit("update_dimm_Trc: clocks after adjustment = %i\n", clocks);
1990 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1991 old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
1992 if (old_clocks >= clocks) { //?? someone did it
1993 // clocks = old_clocks;
1996 dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
1997 dtl |= ((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
1998 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
2002 static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i, struct mem_info *meminfo)
2004 unsigned clocks, old_clocks;
2008 u32 spd_device = ctrl->channel0[i];
2010 if (!(meminfo->dimm_mask & (1 << i)) && (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2011 spd_device = ctrl->channel1[i];
2012 ch_b = 2; /* offset to channelB trfc setting */
2015 //get the cs_size --> logic dimm size
2016 value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
2021 value = 6 - log2(value); //4-->4, 8-->3, 16-->2
2023 clocks = meminfo->sz[i].per_rank - 27 + 2 - value;
2025 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
2027 old_clocks = ((dth >> (DTH_TRFC0_SHIFT + ((i + ch_b) * 3))) & DTH_TRFC_MASK);
2029 if (old_clocks >= clocks) { // some one did it?
2032 dth &= ~(DTH_TRFC_MASK << (DTH_TRFC0_SHIFT + ((i + ch_b) * 3)));
2033 dth |= clocks << (DTH_TRFC0_SHIFT + ((i + ch_b) * 3));
2034 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2038 static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask,
2040 unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX )
2042 unsigned clocks, old_clocks;
2045 u32 spd_device = ctrl->channel0[i];
2047 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2048 spd_device = ctrl->channel1[i];
2051 value = spd_read_byte(spd_device, SPD_TT); //already in 1/4 ns
2052 if (value < 0) return -1;
2054 clocks = (value + param->divisor -1)/param->divisor;
2055 if (clocks < TT_MIN) {
2059 if (clocks > TT_MAX) {
2060 printk(BIOS_INFO, "warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
2064 dtl = pci_read_config32(ctrl->f2, TT_REG);
2066 old_clocks = ((dtl >> TT_SHIFT) & TT_MASK) + TT_BASE;
2067 if (old_clocks >= clocks) { //some one did it?
2068 // clocks = old_clocks;
2071 dtl &= ~(TT_MASK << TT_SHIFT);
2072 dtl |= ((clocks - TT_BASE) << TT_SHIFT);
2073 pci_write_config32(ctrl->f2, TT_REG, dtl);
2077 static int update_dimm_Trcd(const struct mem_controller *ctrl,
2078 const struct mem_param *param, int i, long dimm_mask)
2080 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRCD, DTL_TRCD_SHIFT, DTL_TRCD_MASK, DTL_TRCD_BASE, DTL_TRCD_MIN, DTL_TRCD_MAX);
2083 static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2085 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRRD, DTL_TRRD_SHIFT, DTL_TRRD_MASK, DTL_TRRD_BASE, DTL_TRRD_MIN, DTL_TRRD_MAX);
2088 static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2090 unsigned clocks, old_clocks;
2093 u32 spd_device = ctrl->channel0[i];
2095 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2096 spd_device = ctrl->channel1[i];
2099 value = spd_read_byte(spd_device, SPD_TRAS); //in 1 ns
2100 if (value < 0) return -1;
2101 printk_raminit("update_dimm_Tras: 0 value= %08x\n", value);
2103 value <<= 2; //convert it to in 1/4ns
2106 printk_raminit("update_dimm_Tras: 1 value= %08x\n", value);
2108 clocks = (value + param->divisor - 1)/param->divisor;
2109 printk_raminit("update_dimm_Tras: divisor= %08x\n", param->divisor);
2110 printk_raminit("update_dimm_Tras: clocks= %08x\n", clocks);
2111 if (clocks < DTL_TRAS_MIN) {
2112 clocks = DTL_TRAS_MIN;
2114 if (clocks > DTL_TRAS_MAX) {
2117 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
2118 old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
2119 if (old_clocks >= clocks) { // someone did it?
2122 dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
2123 dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
2124 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
2128 static int update_dimm_Trp(const struct mem_controller *ctrl,
2129 const struct mem_param *param, int i, long dimm_mask)
2131 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRP, DTL_TRP_SHIFT, DTL_TRP_MASK, DTL_TRP_BASE, DTL_TRP_MIN, DTL_TRP_MAX);
2135 static int update_dimm_Trtp(const struct mem_controller *ctrl,
2136 const struct mem_param *param, int i, struct mem_info *meminfo)
2138 /* need to figure if it is 32 byte burst or 64 bytes burst */
2140 if (!meminfo->is_Width128) {
2142 dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2143 if ((dword & DCL_BurstLength32)) offset = 0;
2145 return update_dimm_TT_1_4(ctrl, param, i, meminfo->dimm_mask, DRAM_TIMING_LOW, SPD_TRTP, DTL_TRTP_SHIFT, DTL_TRTP_MASK, DTL_TRTP_BASE+offset, DTL_TRTP_MIN+offset, DTL_TRTP_MAX+offset);
2149 static int update_dimm_Twr(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2151 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TWR, DTL_TWR_SHIFT, DTL_TWR_MASK, DTL_TWR_BASE, DTL_TWR_MIN, DTL_TWR_MAX);
2155 static int update_dimm_Tref(const struct mem_controller *ctrl,
2156 const struct mem_param *param, int i, long dimm_mask)
2158 uint32_t dth, dth_old;
2160 u32 spd_device = ctrl->channel0[i];
2162 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2163 spd_device = ctrl->channel1[i];
2166 value = spd_read_byte(spd_device, SPD_TREF); // 0: 15.625us, 1: 3.9us 2: 7.8 us....
2167 if (value < 0) return -1;
2175 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
2178 dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
2179 dth |= (value << DTH_TREF_SHIFT);
2180 if (dth_old != dth) {
2181 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2186 static void set_4RankRDimm(const struct mem_controller *ctrl,
2187 const struct mem_param *param, struct mem_info *meminfo)
2189 #if QRANK_DIMM_SUPPORT == 1
2192 long dimm_mask = meminfo->dimm_mask;
2195 if (!(meminfo->is_registered)) return;
2199 for (i = 0; i < DIMM_SOCKETS; i++) {
2200 if (!(dimm_mask & (1 << i))) {
2204 if (meminfo->sz[i].rank == 4) {
2212 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2213 dch |= DCH_FourRankRDimm;
2214 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2219 static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
2220 struct mem_info *meminfo)
2226 uint32_t mask_single_rank;
2227 uint32_t mask_page_1k;
2229 #if QRANK_DIMM_SUPPORT == 1
2233 long dimm_mask = meminfo->dimm_mask;
2238 mask_single_rank = 0;
2241 for (i = 0; i < DIMM_SOCKETS; i++) {
2242 u32 spd_device = ctrl->channel0[i];
2243 if (!(dimm_mask & (1 << i))) {
2244 if (dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
2245 spd_device = ctrl->channel1[i];
2251 if (meminfo->sz[i].rank == 1) {
2252 mask_single_rank |= 1<<i;
2255 if (meminfo->sz[i].col==10) {
2256 mask_page_1k |= 1<<i;
2260 value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
2262 #if QRANK_DIMM_SUPPORT == 1
2263 rank = meminfo->sz[i].rank;
2268 #if QRANK_DIMM_SUPPORT == 1
2270 mask_x4 |= 1<<(i+2);
2273 } else if (value==16) {
2275 #if QRANK_DIMM_SUPPORT == 1
2277 mask_x16 |= 1<<(i+2);
2284 meminfo->x4_mask= mask_x4;
2285 meminfo->x16_mask = mask_x16;
2287 meminfo->single_rank_mask = mask_single_rank;
2288 meminfo->page_1k_mask = mask_page_1k;
2295 static void set_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2298 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2299 dcl &= ~(DCL_X4Dimm_MASK<<DCL_X4Dimm_SHIFT);
2300 dcl |= ((meminfo->x4_mask) & 0xf) << (DCL_X4Dimm_SHIFT);
2301 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2305 static int count_ones(uint32_t dimm_mask)
2310 for (index = 0; index < (2 * DIMM_SOCKETS); index++, dimm_mask >>= 1) {
2311 if (dimm_mask & 1) {
2319 static void set_DramTerm(const struct mem_controller *ctrl,
2320 const struct mem_param *param, struct mem_info *meminfo)
2326 if (param->divisor == 100) { //DDR2 800
2327 if (meminfo->is_Width128) {
2328 if (count_ones(meminfo->dimm_mask & 0x0f)==2) {
2336 #if CONFIG_DIMM_SUPPORT == 0x0204
2337 odt = 0x2; /* 150 ohms */
2340 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2341 dcl &= ~(DCL_DramTerm_MASK<<DCL_DramTerm_SHIFT);
2342 dcl |= (odt & DCL_DramTerm_MASK) << (DCL_DramTerm_SHIFT);
2343 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2346 static void set_ecc(const struct mem_controller *ctrl,
2347 const struct mem_param *param, struct mem_info *meminfo)
2352 uint32_t dcl, nbcap;
2353 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
2354 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2355 dcl &= ~DCL_DimmEccEn;
2356 if (nbcap & NBCAP_ECC) {
2357 dcl |= DCL_DimmEccEn;
2359 if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
2360 dcl &= ~DCL_DimmEccEn;
2362 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2364 meminfo->is_ecc = 1;
2365 if (!(dcl & DCL_DimmEccEn)) {
2366 meminfo->is_ecc = 0;
2367 return; // already disabled the ECC, so don't need to read SPD any more
2370 for (i = 0; i < DIMM_SOCKETS; i++) {
2371 u32 spd_device = ctrl->channel0[i];
2372 if (!(meminfo->dimm_mask & (1 << i))) {
2373 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
2374 spd_device = ctrl->channel1[i];
2375 printk(BIOS_DEBUG, "set_ecc spd_device: 0x%x\n", spd_device);
2381 value = spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONF_TYPE);
2383 if (!(value & SPD_DIMM_CONF_TYPE_ECC)) {
2384 dcl &= ~DCL_DimmEccEn;
2385 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2386 meminfo->is_ecc = 0;
2394 static int update_dimm_Twtr(const struct mem_controller *ctrl,
2395 const struct mem_param *param, int i, long dimm_mask)
2397 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_HIGH, SPD_TWTR, DTH_TWTR_SHIFT, DTH_TWTR_MASK, DTH_TWTR_BASE, DTH_TWTR_MIN, DTH_TWTR_MAX);
2400 static void set_TT(const struct mem_controller *ctrl,
2401 const struct mem_param *param, unsigned TT_REG, unsigned TT_SHIFT,
2402 unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX,
2403 unsigned val, const char *str)
2407 if ((val < TT_MIN) || (val > TT_MAX)) {
2408 printk(BIOS_ERR, str);
2412 reg = pci_read_config32(ctrl->f2, TT_REG);
2413 reg &= ~(TT_MASK << TT_SHIFT);
2414 reg |= ((val - TT_BASE) << TT_SHIFT);
2415 pci_write_config32(ctrl->f2, TT_REG, reg);
2420 static void set_TrwtTO(const struct mem_controller *ctrl,
2421 const struct mem_param *param)
2423 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRWTTO_SHIFT, DTH_TRWTTO_MASK,DTH_TRWTTO_BASE, DTH_TRWTTO_MIN, DTH_TRWTTO_MAX, param->TrwtTO, "TrwtTO");
2427 static void set_Twrrd(const struct mem_controller *ctrl, const struct mem_param *param)
2429 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRRD_SHIFT, DTH_TWRRD_MASK,DTH_TWRRD_BASE, DTH_TWRRD_MIN, DTH_TWRRD_MAX, param->Twrrd, "Twrrd");
2433 static void set_Twrwr(const struct mem_controller *ctrl, const struct mem_param *param)
2435 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRWR_SHIFT, DTH_TWRWR_MASK,DTH_TWRWR_BASE, DTH_TWRWR_MIN, DTH_TWRWR_MAX, param->Twrwr, "Twrwr");
2438 static void set_Trdrd(const struct mem_controller *ctrl, const struct mem_param *param)
2440 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRDRD_SHIFT, DTH_TRDRD_MASK,DTH_TRDRD_BASE, DTH_TRDRD_MIN, DTH_TRDRD_MAX, param->Trdrd, "Trdrd");
2443 static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem_param *param)
2445 set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS
2448 static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2450 static const uint8_t faw_1k[] = {8, 10, 13, 14};
2451 static const uint8_t faw_2k[] = {10, 14, 17, 18};
2452 unsigned memclkfreq_index;
2456 memclkfreq_index = param->dch_memclk;
2458 if (meminfo->page_1k_mask != 0) { //1k page
2459 faw = faw_1k[memclkfreq_index];
2461 faw = faw_2k[memclkfreq_index];
2464 set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_FourActWindow_SHIFT, DCH_FourActWindow_MASK, DCH_FourActWindow_BASE, DCH_FourActWindow_MIN, DCH_FourActWindow_MAX, faw, "FourActWindow");
2467 static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
2473 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2474 dch &= ~(DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT);
2476 //FIXME: We need to use Max of DqsRcvEnDelay + 6ns here: After trainning and get that from index reg 0x10, 0x13, 0x16, 0x19, 0x30, 0x33, 0x36, 0x39
2480 dch |= ((async_lat - DCH_MaxAsyncLat_BASE) << DCH_MaxAsyncLat_SHIFT);
2481 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2484 static void set_SlowAccessMode(const struct mem_controller *ctrl)
2488 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2492 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2496 DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20
2497 DRAM_ADDR_TIMING_CTRL 04, 0x24
2499 static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *meminfo)
2503 #if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
2504 unsigned SlowAccessMode = 0;
2507 long dimm_mask = meminfo->dimm_mask & 0x0f;
2509 #if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */
2512 dwordx = 0x002f0000;
2513 switch (meminfo->memclk_set) {
2514 case DCH_MemClkFreq_266MHz:
2515 if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
2516 dwordx = 0x002f2700;
2519 case DCH_MemClkFreq_333MHz:
2520 if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
2521 if ((meminfo->single_rank_mask & 0x03)!=0x03) { //any double rank there?
2522 dwordx = 0x002f2f00;
2526 case DCH_MemClkFreq_400MHz:
2527 dwordx = 0x002f3300;
2533 #if CONFIG_DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */
2535 dwordx = 0x002F2F00;
2537 switch (meminfo->memclk_set) {
2538 case DCH_MemClkFreq_200MHz: /* nothing to be set here */
2540 case DCH_MemClkFreq_266MHz:
2541 if ((meminfo->single_rank_mask == 0)
2542 && (meminfo->x4_mask == 0) && (meminfo->x16_mask))
2543 dwordx = 0x002C2C00; /* Double rank x8 */
2544 /* else SRx16, SRx8, DRx16 == 0x002F2F00 */
2546 case DCH_MemClkFreq_333MHz:
2547 if ((meminfo->single_rank_mask == 1)
2548 && (meminfo->x16_mask == 1)) /* SR x16 */
2549 dwordx = 0x00272700;
2550 else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
2551 && (meminfo->single_rank_mask == 0)) { /* DR x8 */
2553 dwordx = 0x00002800;
2554 } else { /* SR x8, DR x16 */
2555 dwordx = 0x002A2A00;
2558 case DCH_MemClkFreq_400MHz:
2559 if ((meminfo->single_rank_mask == 1)
2560 && (meminfo->x16_mask == 1)) /* SR x16 */
2561 dwordx = 0x00292900;
2562 else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
2563 && (meminfo->single_rank_mask == 0)) { /* DR x8 */
2565 dwordx = 0x00002A00;
2566 } else { /* SR x8, DR x16 */
2567 dwordx = 0x002A2A00;
2573 #if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */
2574 /* for UNBUF DIMM */
2576 dwordx = 0x002f2f00;
2577 switch (meminfo->memclk_set) {
2578 case DCH_MemClkFreq_200MHz:
2579 if (dimm_mask == 0x03) {
2584 case DCH_MemClkFreq_266MHz:
2585 if (dimm_mask == 0x03) {
2588 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
2589 switch (meminfo->single_rank_mask) {
2591 dwordx = 0x00002f00; //x8 single Rank
2594 dwordx = 0x00342f00; //x8 double Rank
2597 dwordx = 0x00372f00; //x8 single Rank and double Rank mixed
2599 } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
2600 dwordx = 0x00382f00; //x8 Double Rank and x16 single Rank mixed
2601 } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
2602 dwordx = 0x00382f00; //x16 single Rank and x8 double Rank mixed
2606 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank
2607 dwordx = 0x002f2f00;
2609 dwordx = 0x002b2f00;
2613 case DCH_MemClkFreq_333MHz:
2614 dwordx = 0x00202220;
2615 if (dimm_mask == 0x03) {
2618 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
2619 switch (meminfo->single_rank_mask) {
2621 dwordx = 0x00302220; //x8 single Rank
2624 dwordx = 0x002b2220; //x8 double Rank
2627 dwordx = 0x002a2220; //x8 single Rank and double Rank mixed
2629 } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
2630 dwordx = 0x002c2220; //x8 Double Rank and x16 single Rank mixed
2631 } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
2632 dwordx = 0x002c2220; //x16 single Rank and x8 double Rank mixed
2636 case DCH_MemClkFreq_400MHz:
2637 dwordx = 0x00202520;
2639 if (dimm_mask == 0x03) {
2647 printk_raminit("\tdimm_mask = %08x\n", meminfo->dimm_mask);
2648 printk_raminit("\tx4_mask = %08x\n", meminfo->x4_mask);
2649 printk_raminit("\tx16_mask = %08x\n", meminfo->x16_mask);
2650 printk_raminit("\tsingle_rank_mask = %08x\n", meminfo->single_rank_mask);
2651 printk_raminit("\tODC = %08x\n", dword);
2652 printk_raminit("\tAddr Timing= %08x\n", dwordx);
2655 #if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
2656 if (SlowAccessMode) {
2657 set_SlowAccessMode(ctrl);
2661 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
2662 /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */
2663 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword);
2665 /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */
2666 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx);
2668 /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */
2669 pci_write_config32_index_wait(ctrl->f2, 0x98, 0, dword);
2670 if (meminfo->is_Width128) {
2671 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword);
2674 /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */
2675 pci_write_config32_index_wait(ctrl->f2, 0x98, 4, dwordx);
2676 if (meminfo->is_Width128) {
2677 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx);
2683 static void set_RDqsEn(const struct mem_controller *ctrl,
2684 const struct mem_param *param, struct mem_info *meminfo)
2686 #if CONFIG_CPU_SOCKET_TYPE==0x10
2687 //only need to set for reg and x8
2690 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2693 if ((!meminfo->x4_mask) && (!meminfo->x16_mask)) {
2697 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2701 static void set_idle_cycle_limit(const struct mem_controller *ctrl,
2702 const struct mem_param *param)
2705 /* AMD says to Hardcode this */
2706 dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
2707 dcm &= ~(DCM_ILD_lmt_MASK << DCM_ILD_lmt_SHIFT);
2708 dcm |= DCM_ILD_lmt_16 << DCM_ILD_lmt_SHIFT;
2710 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
2713 static void set_RdWrQByp(const struct mem_controller *ctrl,
2714 const struct mem_param *param)
2716 set_TT(ctrl, param, DRAM_CTRL_MISC, DCM_RdWrQByp_SHIFT, DCM_RdWrQByp_MASK,0, 0, 3, 2, "RdWrQByp");
2719 static long spd_set_dram_timing(const struct mem_controller *ctrl,
2720 const struct mem_param *param,
2721 struct mem_info *meminfo)
2725 for (i = 0; i < DIMM_SOCKETS; i++) {
2727 if (!(meminfo->dimm_mask & (1 << i)) &&
2728 !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) ) {
2731 printk_raminit("spd_set_dram_timing dimm socket: %08x\n", i);
2732 /* DRAM Timing Low Register */
2733 printk_raminit("\ttrc\n");
2734 if ((rc = update_dimm_Trc (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2736 printk_raminit("\ttrcd\n");
2737 if ((rc = update_dimm_Trcd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2739 printk_raminit("\ttrrd\n");
2740 if ((rc = update_dimm_Trrd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2742 printk_raminit("\ttras\n");
2743 if ((rc = update_dimm_Tras(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2745 printk_raminit("\ttrp\n");
2746 if ((rc = update_dimm_Trp (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2748 printk_raminit("\ttrtp\n");
2749 if ((rc = update_dimm_Trtp(ctrl, param, i, meminfo)) <= 0) goto dimm_err;
2751 printk_raminit("\ttwr\n");
2752 if ((rc = update_dimm_Twr (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2754 /* DRAM Timing High Register */
2755 printk_raminit("\ttref\n");
2756 if ((rc = update_dimm_Tref(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2758 printk_raminit("\ttwtr\n");
2759 if ((rc = update_dimm_Twtr(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2761 printk_raminit("\ttrfc\n");
2762 if ((rc = update_dimm_Trfc(ctrl, param, i, meminfo)) <= 0) goto dimm_err;
2764 /* DRAM Config Low */
2768 printk(BIOS_DEBUG, "spd_set_dram_timing dimm_err!\n");
2772 meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo);
2775 get_extra_dimm_mask(ctrl, meminfo); // will be used by RDqsEn and dimm_x4
2776 /* DRAM Timing Low Register */
2778 /* DRAM Timing High Register */
2779 set_TrwtTO(ctrl, param);
2780 set_Twrrd (ctrl, param);
2781 set_Twrwr (ctrl, param);
2782 set_Trdrd (ctrl, param);
2784 set_4RankRDimm(ctrl, param, meminfo);
2786 /* DRAM Config High */
2787 set_Tfaw(ctrl, param, meminfo);
2788 set_DcqBypassMax(ctrl, param);
2789 set_max_async_latency(ctrl, param);
2790 set_RDqsEn(ctrl, param, meminfo);
2792 /* DRAM Config Low */
2793 set_ecc(ctrl, param, meminfo);
2794 set_dimm_x4(ctrl, param, meminfo);
2795 set_DramTerm(ctrl, param, meminfo);
2797 /* DRAM Control Misc */
2798 set_idle_cycle_limit(ctrl, param);
2799 set_RdWrQByp(ctrl, param);
2801 return meminfo->dimm_mask;
2804 static void sdram_set_spd_registers(const struct mem_controller *ctrl,
2805 struct sys_info *sysinfo)
2807 struct spd_set_memclk_result result;
2808 const struct mem_param *param;
2809 struct mem_param paramx;
2810 struct mem_info *meminfo;
2812 if (!sysinfo->ctrl_present[ctrl->node_id]) {
2816 meminfo = &sysinfo->meminfo[ctrl->node_id];
2818 printk(BIOS_DEBUG, "sdram_set_spd_registers: paramx :%p\n", ¶mx);
2820 activate_spd_rom(ctrl);
2821 meminfo->dimm_mask = spd_detect_dimms(ctrl);
2823 printk_raminit("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask);
2825 if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1)))
2827 printk(BIOS_DEBUG, "No memory for this cpu\n");
2830 meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo);
2831 printk_raminit("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask);
2832 if (meminfo->dimm_mask == -1)
2835 meminfo->dimm_mask = spd_set_ram_size(ctrl, meminfo);
2836 printk_raminit("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask);
2837 if (meminfo->dimm_mask == -1)
2840 meminfo->dimm_mask = spd_handle_unbuffered_dimms(ctrl, meminfo);
2841 printk_raminit("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask);
2842 if (meminfo->dimm_mask == -1)
2845 result = spd_set_memclk(ctrl, meminfo);
2846 param = result.param;
2847 meminfo->dimm_mask = result.dimm_mask;
2848 printk_raminit("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask);
2849 if (meminfo->dimm_mask == -1)
2852 //store memclk set to sysinfo, incase we need rebuilt param again
2853 meminfo->memclk_set = param->dch_memclk;
2855 memcpy(¶mx, param, sizeof(paramx));
2857 paramx.divisor = get_exact_divisor(param->dch_memclk, paramx.divisor);
2859 meminfo->dimm_mask = spd_set_dram_timing(ctrl, ¶mx, meminfo);
2860 printk_raminit("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask);
2861 if (meminfo->dimm_mask == -1)
2864 order_dimms(ctrl, meminfo);
2868 /* Unrecoverable error reading SPD data */
2869 die("Unrecoverable error reading SPD data. No qualified DIMMs?");
2873 #define TIMEOUT_LOOPS 300000
2875 #include "raminit_f_dqs.c"
2877 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
2878 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i)
2881 uint32_t carry_over;
2883 uint32_t base, limit;
2888 carry_over = (4*1024*1024) - hole_startk;
2890 for (ii=controllers - 1;ii>i;ii--) {
2891 base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
2892 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2895 limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
2896 limit += (carry_over << 2 );
2897 base += (carry_over << 2 );
2898 for (j = 0; j < controllers; j++) {
2899 pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit);
2900 pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base );
2903 limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
2904 limit += (carry_over << 2);
2905 for (j = 0; j < controllers; j++) {
2906 pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit);
2909 base = pci_read_config32(dev, 0x40 + (i << 3));
2910 basek = (base & 0xffff0000) >> 2;
2911 if (basek == hole_startk) {
2912 //don't need set memhole here, because hole off set will be 0, overflow
2913 //so need to change base reg instead, new basek will be 4*1024*1024
2915 base |= (4*1024*1024)<<2;
2916 for (j = 0; j < controllers; j++) {
2917 pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
2920 hoist = /* hole start address */
2921 ((hole_startk << 10) & 0xff000000) +
2922 /* hole address to memory controller address */
2923 (((basek + carry_over) >> 6) & 0x0000ff00) +
2926 pci_write_config32(dev, 0xf0, hoist);
2932 static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
2935 uint32_t hole_startk;
2938 hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
2940 printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk);
2941 #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
2942 /* We need to double check if the hole_startk is valid, if it is equal
2943 to basek, we need to decrease it some */
2945 for (i=0; i<controllers; i++) {
2948 base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
2949 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2952 base_k = (base & 0xffff0000) >> 2;
2953 if (base_k == hole_startk) {
2954 /* decrease mem hole startk to make sure it is
2955 on middle of previous node */
2956 hole_startk -= (base_k - basek_pri) >> 1;
2957 break; //only one hole
2961 printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
2963 /* find node index that need do set hole */
2964 for (i=0; i < controllers; i++) {
2965 uint32_t base, limit;
2966 unsigned base_k, limit_k;
2967 base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
2968 if ((base & ((1 << 1) | (1 << 0))) != ((1 << 1) | (1 << 0))) {
2971 limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
2972 base_k = (base & 0xffff0000) >> 2;
2973 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
2974 if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
2976 hoist_memory(controllers, ctrl, hole_startk, i);
2977 end_k = memory_end_k(ctrl, controllers);
2978 set_top_mem(end_k, hole_startk);
2979 break; //only one hole
2986 #include "exit_from_self.c"
2988 static void sdram_enable(int controllers, const struct mem_controller *ctrl,
2989 struct sys_info *sysinfo)
2992 #ifdef ACPI_IS_WAKEUP_EARLY
2993 int suspend = acpi_is_wakeup_early();
2998 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
2999 unsigned cpu_f0_f1[8];
3000 /* FIXME: How about 32 node machine later? */
3003 printk(BIOS_DEBUG, "sdram_enable: tsc0[8]: %p", &tsc0[0]);
3007 /* Error if I don't have memory */
3008 if (memory_end_k(ctrl, controllers) == 0) {
3012 /* Before enabling memory start the memory clocks */
3013 for (i = 0; i < controllers; i++) {
3015 if (!sysinfo->ctrl_present[ i ])
3017 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
3019 /* if no memory installed, disabled the interface */
3020 if (sysinfo->meminfo[i].dimm_mask==0x00){
3021 dch |= DCH_DisDramInterface;
3022 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
3025 dch |= DCH_MemClkFreqVal;
3026 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
3027 /* address timing and Output driver comp Control */
3028 set_misc_timing(ctrl+i, sysinfo->meminfo+i );
3032 /* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */
3033 memreset(controllers, ctrl);
3035 /* lets override the rest of the routine */
3037 printk(BIOS_DEBUG, "Wakeup!\n");
3038 exit_from_self(controllers, ctrl, sysinfo);
3039 printk(BIOS_DEBUG, "Mem running !\n");
3043 for (i = 0; i < controllers; i++) {
3045 if (!sysinfo->ctrl_present[ i ])
3047 /* Skip everything if I don't have any memory on this controller */
3048 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
3049 if (!(dch & DCH_MemClkFreqVal)) {
3054 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
3055 if (dcl & DCL_DimmEccEn) {
3057 printk(BIOS_SPEW, "ECC enabled\n");
3058 mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
3060 if (dcl & DCL_Width128) {
3061 mnc |= MNC_CHIPKILL_EN;
3063 pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
3066 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3067 cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i);
3069 //Rev F0/F1 workaround
3071 /* Set the DqsRcvEnTrain bit */
3072 dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
3073 dword |= DC_DqsRcvEnTrain;
3074 pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
3080 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
3081 dcl |= DCL_InitDram;
3082 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
3085 for (i = 0; i < controllers; i++) {
3087 if (!sysinfo->ctrl_present[ i ])
3089 /* Skip everything if I don't have any memory on this controller */
3090 if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
3092 printk(BIOS_DEBUG, "Initializing memory: ");
3095 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
3097 if ((loops & 1023) == 0) {
3098 printk(BIOS_DEBUG, ".");
3100 } while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS));
3101 if (loops >= TIMEOUT_LOOPS) {
3102 printk(BIOS_DEBUG, " failed\n");
3106 /* Wait until it is safe to touch memory */
3108 dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
3109 } while(((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ );
3111 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3115 print_debug_dqs_tsc("\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
3116 print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2);
3118 if (tsc.lo<tsc0[i].lo) {
3121 tsc.lo -= tsc0[i].lo;
3122 tsc.hi -= tsc0[i].hi;
3124 tsc0[i].lo = tsc.lo;
3125 tsc0[i].hi = tsc.hi;
3127 print_debug_dqs_tsc(" dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
3130 printk(BIOS_DEBUG, " done\n");
3133 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
3134 /* init hw mem hole here */
3135 /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
3136 set_hw_mem_hole(controllers, ctrl);
3139 /* store tom to sysinfo, and it will be used by dqs_timing */
3143 msr = rdmsr(TOP_MEM);
3144 sysinfo->tom_k = ((msr.hi<<24) | (msr.lo>>8))>>2;
3147 msr = rdmsr(TOP_MEM2);
3148 sysinfo->tom2_k = ((msr.hi<<24)| (msr.lo>>8))>>2;
3151 for (i = 0; i < controllers; i++) {
3152 sysinfo->mem_trained[i] = 0;
3154 if (!sysinfo->ctrl_present[ i ])
3157 /* Skip everything if I don't have any memory on this controller */
3158 if (sysinfo->meminfo[i].dimm_mask==0x00)
3161 sysinfo->mem_trained[i] = 0x80; // mem need to be trained
3165 #if CONFIG_MEM_TRAIN_SEQ == 0
3166 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3167 dqs_timing(controllers, ctrl, tsc0, sysinfo);
3169 dqs_timing(controllers, ctrl, sysinfo);
3173 #if CONFIG_MEM_TRAIN_SEQ == 2
3174 /* need to enable mtrr, so dqs training could access the test address */
3175 setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
3178 for (i = 0; i < controllers; i++) {
3179 /* Skip everything if I don't have any memory on this controller */
3180 if (sysinfo->mem_trained[i]!=0x80)
3183 dqs_timing(i, &ctrl[i], sysinfo, 1);
3185 #if CONFIG_MEM_TRAIN_SEQ == 1
3186 break; // only train the first node with ram
3190 #if CONFIG_MEM_TRAIN_SEQ == 2
3191 clear_mtrr_dqs(sysinfo->tom2_k);
3196 #if CONFIG_MEM_TRAIN_SEQ != 1
3197 wait_all_core0_mem_trained(sysinfo);
3202 static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
3203 const uint16_t *spd_addr)
3207 struct mem_controller *ctrl;
3208 for (i=0;i<controllers; i++) {
3211 ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
3212 ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
3213 ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
3214 ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
3216 if (spd_addr == (void *)0) continue;
3218 for (j=0;j<DIMM_SOCKETS;j++) {
3219 ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
3220 ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];