2 * This file is part of the coreboot project.
4 * Copyright (C) 2002 Linux Networx
5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
6 * Copyright (C) 2004 YingHai Lu
7 * Copyright (C) 2008 Advanced Micro Devices, Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <cpu/x86/mem.h>
24 #include <cpu/x86/cache.h>
25 #include <cpu/x86/mtrr.h>
26 #include <cpu/x86/tsc.h>
33 #ifndef QRANK_DIMM_SUPPORT
34 #define QRANK_DIMM_SUPPORT 0
37 #define RAM_TIMING_DEBUG 0
39 #if RAM_TIMING_DEBUG == 1
40 #define printk_raminit printk_debug
42 #define printk_raminit(fmt, arg...)
46 #if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
47 # error "CONFIG_RAMTOP must be a power of 2"
50 #include "amdk8_f_pci.c"
53 /* for PCI_ADDR(0, 0x18, 2, 0x98) index,
54 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
57 [29: 0] DctOffset (Dram Controller Offset)
58 [30:30] DctAccessWrite (Dram Controller Read/Write Select)
61 [31:31] DctAccessDone (Dram Controller Access Done)
62 0 = Access in progress
63 1 = No access is progress
66 [31: 0] DctOffsetData (Dram Controller Offset Data)
69 - Write the register num to DctOffset with
71 - poll the DctAccessDone until it = 1
72 - Read the data from DctOffsetData
74 - Write the data to DctOffsetData
75 - Write register num to DctOffset with DctAccessWrite = 1
76 - poll the DctAccessDone untio it = 1
80 static void setup_resource_map(const unsigned int *register_values, int max)
83 for (i = 0; i < max; i += 3) {
87 dev = register_values[i] & ~0xff;
88 where = register_values[i] & 0xff;
89 reg = pci_read_config32(dev, where);
90 reg &= register_values[i+1];
91 reg |= register_values[i+2];
92 pci_write_config32(dev, where, reg);
96 static int controller_present(const struct mem_controller *ctrl)
98 return pci_read_config32(ctrl->f0, 0) == 0x11001022;
101 static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
103 static const unsigned int register_values[] = {
105 /* Careful set limit registers before base registers which
106 contain the enables */
107 /* DRAM Limit i Registers
116 * [ 2: 0] Destination Node ID
126 * [10: 8] Interleave select
127 * specifies the values of A[14:12] to use with interleave enable.
129 * [31:16] DRAM Limit Address i Bits 39-24
130 * This field defines the upper address bits of a 40 bit address
131 * that define the end of the DRAM region.
133 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
134 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
135 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
136 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
137 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
138 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
139 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
140 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
141 /* DRAM Base i Registers
150 * [ 0: 0] Read Enable
153 * [ 1: 1] Write Enable
154 * 0 = Writes Disabled
157 * [10: 8] Interleave Enable
158 * 000 = No interleave
159 * 001 = Interleave on A[12] (2 nodes)
161 * 011 = Interleave on A[12] and A[14] (4 nodes)
165 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
167 * [13:16] DRAM Base Address i Bits 39-24
168 * This field defines the upper address bits of a 40-bit address
169 * that define the start of the DRAM region.
171 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
172 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
173 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
174 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
175 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
176 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
177 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
178 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
180 /* DRAM CS Base Address i Registers
189 * [ 0: 0] Chip-Select Bank Enable
193 * [ 2: 2] Memory Test Failed
195 * [13: 5] Base Address (21-13)
196 * An optimization used when all DIMM are the same size...
198 * [28:19] Base Address (36-27)
199 * This field defines the top 11 addresses bit of a 40-bit
200 * address that define the memory address space. These
201 * bits decode 32-MByte blocks of memory.
204 PCI_ADDR(0, 0x18, 2, 0x40), 0xe007c018, 0x00000000,
205 PCI_ADDR(0, 0x18, 2, 0x44), 0xe007c018, 0x00000000,
206 PCI_ADDR(0, 0x18, 2, 0x48), 0xe007c018, 0x00000000,
207 PCI_ADDR(0, 0x18, 2, 0x4C), 0xe007c018, 0x00000000,
208 PCI_ADDR(0, 0x18, 2, 0x50), 0xe007c018, 0x00000000,
209 PCI_ADDR(0, 0x18, 2, 0x54), 0xe007c018, 0x00000000,
210 PCI_ADDR(0, 0x18, 2, 0x58), 0xe007c018, 0x00000000,
211 PCI_ADDR(0, 0x18, 2, 0x5C), 0xe007c018, 0x00000000,
212 /* DRAM CS Mask Address i Registers
217 * Select bits to exclude from comparison with the DRAM Base address register.
219 * [13: 5] Address Mask (21-13)
220 * Address to be excluded from the optimized case
222 * [28:19] Address Mask (36-27)
223 * The bits with an address mask of 1 are excluded from address comparison
227 PCI_ADDR(0, 0x18, 2, 0x60), 0xe007c01f, 0x00000000,
228 PCI_ADDR(0, 0x18, 2, 0x64), 0xe007c01f, 0x00000000,
229 PCI_ADDR(0, 0x18, 2, 0x68), 0xe007c01f, 0x00000000,
230 PCI_ADDR(0, 0x18, 2, 0x6C), 0xe007c01f, 0x00000000,
232 /* DRAM Control Register
234 * [ 3: 0] RdPtrInit ( Read Pointer Initial Value)
235 * 0x03-0x00: reserved
236 * [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO)
239 * 010 = 1.5 Memory Clocks
240 * 011 = 2 Memory Clocks
241 * 100 = 2.5 Memory Clocks
242 * 101 = 3 Memory Clocks
243 * 110 = 3.5 Memory Clocks
246 * [16:16] AltVidC3MemClkTriEn (AltVID Memory Clock Tristate Enable)
247 * Enables the DDR memory clocks to be tristated when alternate VID
248 * mode is enabled. This bit has no effect if the DisNbClkRamp bit
250 * [17:17] DllTempAdjTime (DLL Temperature Adjust Cycle Time)
253 * [18:18] DqsRcvEnTrain (DQS Receiver Enable Training Mode)
254 * 0 = Normal DQS Receiver enable operation
255 * 1 = DQS receiver enable training mode
258 PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6<<4)|(6<<0),
260 /* DRAM Initialization Register
262 * [15: 0] MrsAddress (Address for MRS/EMRS Commands)
263 * this field specifies the dsata driven on the DRAM address pins
264 * 15-0 for MRS and EMRS commands
265 * [18:16] MrsBank (Bank Address for MRS/EMRS Commands)
266 * this files specifies the data driven on the DRAM bank pins for
267 * the MRS and EMRS commands
269 * [24:24] SendPchgAll (Send Precharge All Command)
270 * Setting this bit causes the DRAM controller to send a precharge
271 * all command. This bit is cleared by the hardware after the
273 * [25:25] SendAutoRefresh (Send Auto Refresh Command)
274 * Setting this bit causes the DRAM controller to send an auto
275 * refresh command. This bit is cleared by the hardware after the
277 * [26:26] SendMrsCmd (Send MRS/EMRS Command)
278 * Setting this bit causes the DRAM controller to send the MRS or
279 * EMRS command defined by the MrsAddress and MrsBank fields. This
280 * bit is cleared by the hardware adter the commmand completes
281 * [27:27] DeassertMemRstX (De-assert Memory Reset)
282 * Setting this bit causes the DRAM controller to de-assert the
283 * memory reset pin. This bit cannot be used to assert the memory
285 * [28:28] AssertCke (Assert CKE)
286 * setting this bit causes the DRAM controller to assert the CKE
287 * pins. This bit cannot be used to de-assert the CKE pins
289 * [31:31] EnDramInit (Enable DRAM Initialization)
290 * Setting this bit puts the DRAM controller in a BIOS controlled
291 * DRAM initialization mode. BIOS must clear this bit aster DRAM
292 * initialization is complete.
294 // PCI_ADDR(0, 0x18, 2, 0x7C), 0x60f80000, 0,
297 /* DRAM Bank Address Mapping Register
299 * Specify the memory module size
319 PCI_ADDR(0, 0x18, 2, 0x80), 0xffff0000, 0x00000000,
320 /* DRAM Timing Low Register
322 * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid)
332 * [ 5: 4] Trcd (Ras#-active to Cas# read/write delay)
338 * [ 9: 8] Trp (Row Precharge Time, Precharge-to-Active or Auto-Refresh)
344 * [11:11] Trtp (Read to Precharge Time, read Cas# to precharge time)
345 * 0 = 2 clocks for Burst Length of 32 Bytes
346 * 4 clocks for Burst Length of 64 Bytes
347 * 1 = 3 clocks for Burst Length of 32 Bytes
348 * 5 clocks for Burst Length of 64 Bytes
349 * [15:12] Tras (Minimum Ras# Active Time)
352 * 0010 = 5 bus clocks
354 * 1111 = 18 bus clocks
355 * [19:16] Trc (Row Cycle Time, Ras#-active to Ras#-active or auto
356 * refresh of the same bank)
357 * 0000 = 11 bus clocks
358 * 0010 = 12 bus clocks
360 * 1110 = 25 bus clocks
361 * 1111 = 26 bus clocks
362 * [21:20] Twr (Write Recovery Time, From the last data to precharge,
363 * writes can go back-to-back)
368 * [23:22] Trrd (Active-to-active(Ras#-to-Ras#) Delay of different banks)
373 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A,
374 * BIOS should set it to reduce the power consumption)
375 * Bit F(1207) M2 Package S1g1 Package
377 * 1 N/A MA0_CLK1 MA0_CLK1
380 * 4 MA1_CLK MA1_CLK0 N/A
381 * 5 MA0_CLK MA0_CLK0 MA0_CLK0
383 * 7 N/A MA0_CLK2 MA0_CLK2
385 PCI_ADDR(0, 0x18, 2, 0x88), 0x000004c8, 0xff000002 /* 0x03623125 */ ,
386 /* DRAM Timing High Register
389 * [ 6: 4] TrwtTO (Read-to-Write Turnaround for Data, DQS Contention)
399 * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay,
400 * minium write-to-read delay when both access the same chip select)
405 * [11:10] Twrrd (Write to Read DIMM Termination Turnaround, minimum
406 * write-to-read delay when accessing two different DIMMs)
411 * [13:12] Twrwr (Write to Write Timing)
412 * 00 = 1 bus clocks ( 0 idle cycle on the bus)
413 * 01 = 2 bus clocks ( 1 idle cycle on the bus)
414 * 10 = 3 bus clocks ( 2 idle cycles on the bus)
416 * [15:14] Trdrd ( Read to Read Timing)
417 * 00 = 2 bus clocks ( 1 idle cycle on the bus)
418 * 01 = 3 bus clocks ( 2 idle cycles on the bus)
419 * 10 = 4 bus clocks ( 3 idle cycles on the bus)
420 * 11 = 5 bus clocks ( 4 idel cycles on the bus)
421 * [17:16] Tref (Refresh Rate)
422 * 00 = Undefined behavior
424 * 10 = Refresh interval of 7.8 microseconds
425 * 11 = Refresh interval of 3.9 microseconds
427 * [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0,
428 * based on DRAM density and speed)
429 * 000 = 75 ns (all speeds, 256Mbit)
430 * 001 = 105 ns (all speeds, 512Mbit)
431 * 010 = 127.5 ns (all speeds, 1Gbit)
432 * 011 = 195 ns (all speeds, 2Gbit)
433 * 100 = 327.5 ns (all speeds, 4Gbit)
437 * [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1,
438 * based on DRAM density and speed)
439 * [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2,
440 * based on DRAM density and speed)
441 * [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3,
442 * based on DRAM density and speed)
444 PCI_ADDR(0, 0x18, 2, 0x8c), 0x000c008f, (2 << 16)|(1 << 8),
445 /* DRAM Config Low Register
447 * [ 0: 0] InitDram (Initialize DRAM)
448 * 1 = write 1 cause DRAM controller to execute the DRAM
449 * initialization, when done it read to 0
450 * [ 1: 1] ExitSelfRef ( Exit Self Refresh Command )
451 * 1 = write 1 causes the DRAM controller to bring the DRAMs out
452 * for self refresh mode
454 * [ 5: 4] DramTerm (DRAM Termination)
455 * 00 = On die termination disabled
460 * [ 7: 7] DramDrvWeak ( DRAM Drivers Weak Mode)
461 * 0 = Normal drive strength mode.
462 * 1 = Weak drive strength mode
463 * [ 8: 8] ParEn (Parity Enable)
464 * 1 = Enable address parity computation output, PAR,
465 * and enables the parity error input, ERR
466 * [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable)
467 * 1 = Enable high temperature ( two times normal )
469 * [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes)
472 * [11:11] Width128 ( Width of DRAM interface)
473 * 0 = the controller DRAM interface is 64-bits wide
474 * 1 = the controller DRAM interface is 128-bits wide
475 * [12:12] X4Dimm (DIMM 0 is x4)
476 * [13:13] X4Dimm (DIMM 1 is x4)
477 * [14:14] X4Dimm (DIMM 2 is x4)
478 * [15:15] X4Dimm (DIMM 3 is x4)
480 * 1 = x4 DIMM present
481 * [16:16] UnBuffDimm ( Unbuffered DIMMs)
483 * 1 = Unbuffered DIMMs
485 * [19:19] DimmEccEn ( DIMM ECC Enable )
486 * 1 = ECC checking is being enabled for all DIMMs on the DRAM
487 * controller ( Through F3 0x44[EccEn])
490 PCI_ADDR(0, 0x18, 2, 0x90), 0xfff6004c, 0x00000010,
491 /* DRAM Config High Register
493 * [ 0: 2] MemClkFreq ( Memory Clock Frequency)
499 * [ 3: 3] MemClkFreqVal (Memory Clock Freqency Valid)
500 * 1 = BIOS need to set the bit when setting up MemClkFreq to
502 * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency)
507 * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8
508 * registered DIMMs are present in the system
509 * 0 = DM pins function as data mask pins
510 * 1 = DM pins function as read DQS pins
512 * [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit
513 * is set, the DRAM controller is disabled, and interface in low power
515 * 0 = Enabled (default)
517 * [15:15] PowerDownEn ( Power Down Mode Enable )
518 * 0 = Disabled (default)
520 * [16:16] PowerDown ( Power Down Mode )
521 * 0 = Channel CKE Control
522 * 1 = Chip Select CKE Control
523 * [17:17] FourRankSODimm (Four Rank SO-DIMM)
524 * 1 = this bit is set by BIOS to indicate that a four rank
526 * [18:18] FourRankRDimm (Four Rank Registered DIMM)
527 * 1 = this bit is set by BIOS to indicate that a four rank
528 * registered DIMM is present
530 * [20:20] SlowAccessMode (Slow Access Mode (2T Mode))
531 * 0 = DRAM address and control signals are driven for one
533 * 1 = One additional MEMCLK of setup time is provided on all
534 * DRAM address and control signals except CS, CKE, and ODT;
535 * i.e., these signals are drivern for two MEMCLK cycles
538 * [22:22] BankSwizzleMode ( Bank Swizzle Mode),
539 * 0 = Disabled (default)
542 * [27:24] DcqBypassMax ( DRAM Controller Queue Bypass Maximum)
543 * 0000 = No bypass; the oldest request is never bypassed
544 * 0001 = The oldest request may be bypassed no more than 1 time
546 * 1111 = The oldest request may be bypassed no more than 15\
548 * [31:28] FourActWindow ( Four Bank Activate Window) , not more than
549 * 4 banks in a 8 bank device are activated
550 * 0000 = No tFAW window restriction
551 * 0001 = 8 MEMCLK cycles
552 * 0010 = 9 MEMCLK cycles
554 * 1101 = 20 MEMCLK cycles
557 PCI_ADDR(0, 0x18, 2, 0x94), 0x00a82f00,0x00008000,
558 /* DRAM Delay Line Register
560 * [ 0: 0] MemClrStatus (Memory Clear Status) : Readonly
561 * when set, this bit indicates that the memory clear function
562 * is complete. Only clear by reset. BIOS should not write or
563 * read the DRAM until this bit is set by hardware
564 * [ 1: 1] DisableJitter ( Disable Jitter)
565 * When set the DDR compensation circuit will not change the
566 * values unless the change is more than one step from the
568 * [ 3: 2] RdWrQByp ( Read/Write Queue Bypass Count)
573 * [ 4: 4] Mode64BitMux (Mismatched DIMM Support Enable)
574 * 1 When bit enables support for mismatched DIMMs when using
575 * 128-bit DRAM interface, the Width128 no effect, only for
577 * [ 5: 5] DCC_EN ( Dynamica Idle Cycle Counter Enable)
578 * When set to 1, indicates that each entry in the page tables
579 * dynamically adjusts the idle cycle limit based on page
580 * Conflict/Page Miss (PC/PM) traffic
581 * [ 8: 6] ILD_lmt ( Idle Cycle Limit)
590 * [ 9: 9] DramEnabled ( DRAM Enabled)
591 * When Set, this bit indicates that the DRAM is enabled, this
592 * bit is set by hardware after DRAM initialization or on an exit
593 * from self refresh. The DRAM controller is intialized after the
594 * hardware-controlled initialization process ( initiated by the
595 * F2 0x90[DramInit]) completes or when the BIOS-controlled
596 * initialization process completes (F2 0x7c(EnDramInit] is
597 * written from 1 to 0)
599 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B,
600 * BIOS should set it to reduce the power consumption)
601 * Bit F(1207) M2 Package S1g1 Package
603 * 1 N/A MA0_CLK1 MA0_CLK1
606 * 4 MA1_CLK MA1_CLK0 N/A
607 * 5 MA0_CLK MA0_CLK0 MA0_CLK0
609 * 7 N/A MA0_CLK2 MA0_CLK2
611 PCI_ADDR(0, 0x18, 2, 0xa0), 0x00fffc00, 0xff000000,
613 /* DRAM Scrub Control Register
615 * [ 4: 0] DRAM Scrube Rate
617 * [12: 8] L2 Scrub Rate
619 * [20:16] Dcache Scrub
622 * 00000 = Do not scrub
644 * All Others = Reserved
646 PCI_ADDR(0, 0x18, 3, 0x58), 0xffe0e0e0, 0x00000000,
647 /* DRAM Scrub Address Low Register
649 * [ 0: 0] DRAM Scrubber Redirect Enable
651 * 1 = Scrubber Corrects errors found in normal operation
653 * [31: 6] DRAM Scrub Address 31-6
655 PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000,
656 /* DRAM Scrub Address High Register
658 * [ 7: 0] DRAM Scrubb Address 39-32
661 PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
663 /* for PCI_ADDR(0, 0x18, 2, 0x98) index,
664 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
667 [29: 0] DctOffset (Dram Controller Offset)
668 [30:30] DctAccessWrite (Dram Controller Read/Write Select)
671 [31:31] DctAccessDone (Dram Controller Access Done)
672 0 = Access in progress
673 1 = No access is progress
676 [31: 0] DctOffsetData (Dram Controller Offset Data)
679 - Write the register num to DctOffset with DctAccessWrite = 0
680 - poll the DctAccessDone until it = 1
681 - Read the data from DctOffsetData
683 - Write the data to DctOffsetData
684 - Write register num to DctOffset with DctAccessWrite = 1
685 - poll the DctAccessDone untio it = 1
691 if (!controller_present(ctrl)) {
692 sysinfo->ctrl_present[ctrl->node_id] = 0;
695 sysinfo->ctrl_present[ctrl->node_id] = 1;
697 printk_spew("setting up CPU %02x northbridge registers\n", ctrl->node_id);
698 max = ARRAY_SIZE(register_values);
699 for (i = 0; i < max; i += 3) {
703 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
704 where = register_values[i] & 0xff;
705 reg = pci_read_config32(dev, where);
706 reg &= register_values[i+1];
707 reg |= register_values[i+2];
708 pci_write_config32(dev, where, reg);
710 printk_spew("done.\n");
713 static int is_dual_channel(const struct mem_controller *ctrl)
716 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
717 return dcl & DCL_Width128;
720 static int is_opteron(const struct mem_controller *ctrl)
722 /* Test to see if I am an Opteron.
723 * FIXME Testing dual channel capability is correct for now
724 * but a better test is probably required.
725 * m2 and s1g1 support dual channel too. but only support unbuffered dimm
727 #warning "FIXME implement a better test for opterons"
729 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
730 return !!(nbcap & NBCAP_128Bit);
733 static int is_registered(const struct mem_controller *ctrl)
735 /* Test to see if we are dealing with registered SDRAM.
736 * If we are not registered we are unbuffered.
737 * This function must be called after spd_handle_unbuffered_dimms.
740 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
741 return !(dcl & DCL_UnBuffDimm);
745 static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
747 /* Calculate the log base 2 size of a DIMM in bits */
754 value = spd_read_byte(device, SPD_ROW_NUM); /* rows */
755 if (value < 0) goto hw_err;
756 if ((value & 0xff) == 0) goto val_err; /* max is 16 ? */
757 sz->per_rank += value & 0xff;
758 sz->rows = value & 0xff;
760 value = spd_read_byte(device, SPD_COL_NUM); /* columns */
761 if (value < 0) goto hw_err;
762 if ((value & 0xff) == 0) goto val_err; /* max is 11 */
763 sz->per_rank += value & 0xff;
764 sz->col = value & 0xff;
766 value = spd_read_byte(device, SPD_BANK_NUM); /* banks */
767 if (value < 0) goto hw_err;
768 if ((value & 0xff) == 0) goto val_err;
769 sz->bank = log2(value & 0xff); // convert 4 to 2, and 8 to 3
770 sz->per_rank += sz->bank;
772 /* Get the module data width and convert it to a power of two */
773 value = spd_read_byte(device, SPD_DATA_WIDTH);
774 if (value < 0) goto hw_err;
776 if ((value != 72) && (value != 64)) goto val_err;
777 sz->per_rank += log2(value) - 3; //64 bit So another 3 lines
779 /* How many ranks? */
780 /* number of physical banks */
781 value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK);
782 if (value < 0) goto hw_err;
783 /* value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT; */
784 value &= SPD_MOD_ATTRIB_RANK_NUM_MASK;
785 value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4
787 rank == 1 only one rank or say one side
788 rank == 2 two side , and two ranks
789 rank == 4 two side , and four ranks total
790 Some one side two ranks, because of stacked
792 if ((value != 1) && (value != 2) && (value != 4 )) {
797 /* verify if per_rank is equal byte 31
798 it has the DIMM size as a multiple of 128MB.
800 value = spd_read_byte(device, SPD_RANK_SIZE);
801 if (value < 0) goto hw_err;
804 if (value <=4 ) value += 8; // add back to 1G to high
805 value += (27-5); // make 128MB to the real lines
806 if ( value != (sz->per_rank)) {
807 printk_err("Bad RANK Size --\n");
814 die("Bad SPD value\n");
815 /* If an hw_error occurs report that I have no memory */
827 static void set_dimm_size(const struct mem_controller *ctrl,
828 struct dimm_size *sz, unsigned index,
829 struct mem_info *meminfo)
831 uint32_t base0, base1;
833 /* For each base register.
834 * Place the dimm size in 32 MB quantities in the bits 31 - 21.
835 * The initialize dimm size is in bits.
836 * Set the base enable bit0.
841 /* Make certain side1 of the dimm is at least 128MB */
842 if (sz->per_rank >= 27) {
843 base0 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
846 /* Make certain side2 of the dimm is at least 128MB */
847 if (sz->rank > 1) { // 2 ranks or 4 ranks
848 base1 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
851 /* Double the size if we are using dual channel memory */
852 if (meminfo->is_Width128) {
853 base0 = (base0 << 1) | (base0 & 1);
854 base1 = (base1 << 1) | (base1 & 1);
857 /* Clear the reserved bits */
858 base0 &= ~0xe007fffe;
859 base1 &= ~0xe007fffe;
861 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
862 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
863 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
865 /* Set the appropriate DIMM base address register */
866 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0);
867 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1);
868 #if QRANK_DIMM_SUPPORT == 1
870 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
871 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
876 /* Enable the memory clocks for this DIMM by Clear the MemClkDis bit*/
880 #if CONFIG_CPU_SOCKET_TYPE == 0x10 /* L1 */
881 ClkDis0 = DTL_MemClkDis0;
882 #elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM2 */
883 ClkDis0 = DTL_MemClkDis0_AM2;
884 #elif CONFIG_CPU_SOCKET_TYPE == 0x12 /* S1G1 */
885 ClkDis0 = DTL_MemClkDis0_S1g1;
888 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
889 dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
890 dword &= ~(ClkDis0 >> index);
891 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
894 dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
895 dword &= ~(ClkDis0 >> index);
896 #if QRANK_DIMM_SUPPORT == 1
898 dword &= ~(ClkDis0 >> (index+2));
901 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dword);
903 if (meminfo->is_Width128) { // ChannelA+B
904 dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
905 dword &= ~(ClkDis0 >> index);
906 #if QRANK_DIMM_SUPPORT == 1
908 dword &= ~(ClkDis0 >> (index+2));
911 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
918 /* row col bank for 64 bit
934 static void set_dimm_cs_map(const struct mem_controller *ctrl,
935 struct dimm_size *sz, unsigned index,
936 struct mem_info *meminfo)
938 static const uint8_t cs_map_aaa[24] = {
939 /* (bank=2, row=13, col=9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */
954 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
957 map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
958 map &= ~(0xf << (index * 4));
959 #if QRANK_DIMM_SUPPORT == 1
961 map &= ~(0xf << ( (index + 2) * 4));
965 /* Make certain side1 of the dimm is at least 128MB */
966 if (sz->per_rank >= 27) {
968 temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ];
969 map |= temp_map << (index*4);
970 #if QRANK_DIMM_SUPPORT == 1
972 map |= temp_map << ( (index + 2) * 4);
977 pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
982 static long spd_set_ram_size(const struct mem_controller *ctrl,
983 struct mem_info *meminfo)
987 for (i = 0; i < DIMM_SOCKETS; i++) {
988 struct dimm_size *sz = &(meminfo->sz[i]);
989 u32 spd_device = ctrl->channel0[i];
991 if (!(meminfo->dimm_mask & (1 << i))) {
992 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
993 spd_device = ctrl->channel1[i];
999 spd_get_dimm_size(spd_device, sz);
1000 if (sz->per_rank == 0) {
1001 return -1; /* Report SPD error */
1003 set_dimm_size(ctrl, sz, i, meminfo);
1004 set_dimm_cs_map(ctrl, sz, i, meminfo);
1006 return meminfo->dimm_mask;
1009 static void route_dram_accesses(const struct mem_controller *ctrl,
1010 unsigned long base_k, unsigned long limit_k)
1012 /* Route the addresses to the controller node */
1017 unsigned limit_reg, base_reg;
1020 node_id = ctrl->node_id;
1021 index = (node_id << 3);
1022 limit = (limit_k << 2);
1023 limit &= 0xffff0000;
1024 limit -= 0x00010000;
1025 limit |= ( 0 << 8) | (node_id << 0);
1026 base = (base_k << 2);
1028 base |= (0 << 8) | (1<<1) | (1<<0);
1030 limit_reg = 0x44 + index;
1031 base_reg = 0x40 + index;
1032 for (device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1);
1033 device += PCI_DEV(0, 1, 0)) {
1034 pci_write_config32(device, limit_reg, limit);
1035 pci_write_config32(device, base_reg, base);
1039 static void set_top_mem(unsigned tom_k, unsigned hole_startk)
1041 /* Error if I don't have memory */
1046 /* Report the amount of memory. */
1047 printk_debug("RAM end at 0x%08x kB\n", tom_k);
1049 /* Now set top of memory */
1051 if (tom_k > (4*1024*1024)) {
1052 printk_raminit("Handling memory mapped above 4 GB\n");
1053 printk_raminit("Upper RAM end at 0x%08x kB\n", tom_k);
1054 msr.lo = (tom_k & 0x003fffff) << 10;
1055 msr.hi = (tom_k & 0xffc00000) >> 22;
1056 wrmsr(TOP_MEM2, msr);
1057 printk_raminit("Correcting memory amount mapped below 4 GB\n");
1060 /* Leave a 64M hole between TOP_MEM and TOP_MEM2
1061 * so I can see my rom chip and other I/O devices.
1063 if (tom_k >= 0x003f0000) {
1064 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
1065 if (hole_startk != 0) {
1066 tom_k = hole_startk;
1070 printk_raminit("Adjusting lower RAM end\n");
1072 printk_raminit("Lower RAM end at 0x%08x kB\n", tom_k);
1073 msr.lo = (tom_k & 0x003fffff) << 10;
1074 msr.hi = (tom_k & 0xffc00000) >> 22;
1075 wrmsr(TOP_MEM, msr);
1078 static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, int is_Width128)
1082 static const uint8_t csbase_low_f0_shift[] = {
1083 /* 128MB */ (14 - (13-5)),
1084 /* 256MB */ (15 - (13-5)),
1085 /* 512MB */ (15 - (13-5)),
1086 /* 512MB */ (16 - (13-5)),
1087 /* 512MB */ (16 - (13-5)),
1088 /* 1GB */ (16 - (13-5)),
1089 /* 1GB */ (16 - (13-5)),
1090 /* 2GB */ (16 - (13-5)),
1091 /* 2GB */ (17 - (13-5)),
1092 /* 4GB */ (17 - (13-5)),
1093 /* 4GB */ (16 - (13-5)),
1094 /* 8GB */ (17 - (13-5)),
1097 /* cs_base_high is not changed */
1099 uint32_t csbase_inc;
1100 int chip_selects, index;
1102 unsigned common_size;
1103 unsigned common_cs_mode;
1104 uint32_t csbase, csmask;
1106 /* See if all of the memory chip selects are the same size
1107 * and if so count them.
1111 common_cs_mode = 0xff;
1112 for (index = 0; index < 8; index++) {
1117 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1119 /* Is it enabled? */
1124 size = (value >> 19) & 0x3ff;
1125 if (common_size == 0) {
1128 /* The size differed fail */
1129 if (common_size != size) {
1133 value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
1134 cs_mode =( value >> ((index>>1)*4)) & 0xf;
1135 if (common_cs_mode == 0xff) {
1136 common_cs_mode = cs_mode;
1138 /* The cs_mode differed fail */
1139 if (common_cs_mode != cs_mode) {
1144 /* Chip selects can only be interleaved when there is
1145 * more than one and their is a power of two of them.
1147 bits = log2(chip_selects);
1148 if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) {
1149 //chip_selects max = 8
1153 /* Find the bits of csbase that we need to interleave on */
1154 csbase_inc = 1 << (csbase_low_f0_shift[common_cs_mode]);
1159 /* Compute the initial values for csbase and csbask.
1160 * In csbase just set the enable bit and the base to zero.
1161 * In csmask set the mask bits for the size and page level interleave.
1164 csmask = (((common_size << bits) - 1) << 19);
1165 csmask |= 0x3fe0 & ~((csbase_inc << bits) - csbase_inc);
1166 for (index = 0; index < 8; index++) {
1169 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1170 /* Is it enabled? */
1174 pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
1175 if ((index & 1) == 0) { //only have 4 CSMASK
1176 pci_write_config32(ctrl->f2, DRAM_CSMASK + ((index>>1) << 2), csmask);
1178 csbase += csbase_inc;
1181 printk_debug("Interleaved\n");
1183 /* Return the memory size in K */
1184 return common_size << ((27-10) + bits);
1187 static unsigned long order_chip_selects(const struct mem_controller *ctrl)
1191 /* Remember which registers we have used in the high 8 bits of tom */
1194 /* Find the largest remaining canidate */
1195 unsigned index, canidate;
1196 uint32_t csbase, csmask;
1200 for (index = 0; index < 8; index++) {
1202 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1204 /* Is it enabled? */
1209 /* Is it greater? */
1210 if (value <= csbase) {
1214 /* Has it already been selected */
1215 if (tom & (1 << (index + 24))) {
1218 /* I have a new canidate */
1223 /* See if I have found a new canidate */
1228 /* Remember the dimm size */
1229 size = csbase >> 19;
1231 /* Remember I have used this register */
1232 tom |= (1 << (canidate + 24));
1234 /* Recompute the cs base register value */
1235 csbase = (tom << 19) | 1;
1237 /* Increment the top of memory */
1240 /* Compute the memory mask */
1241 csmask = ((size -1) << 19);
1242 csmask |= 0x3fe0; /* For now don't optimize */
1244 /* Write the new base register */
1245 pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
1246 /* Write the new mask register */
1247 if ((canidate & 1) == 0) { //only have 4 CSMASK
1248 pci_write_config32(ctrl->f2, DRAM_CSMASK + ((canidate >> 1) << 2), csmask);
1252 /* Return the memory size in K */
1253 return (tom & ~0xff000000) << (27-10);
1256 unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
1260 /* Find the last memory address used */
1262 for (node_id = 0; node_id < max_node_id; node_id++) {
1263 uint32_t limit, base;
1265 index = node_id << 3;
1266 base = pci_read_config32(ctrl->f1, 0x40 + index);
1267 /* Only look at the limit if the base is enabled */
1268 if ((base & 3) == 3) {
1269 limit = pci_read_config32(ctrl->f1, 0x44 + index);
1270 end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
1276 static void order_dimms(const struct mem_controller *ctrl,
1277 struct mem_info *meminfo)
1279 unsigned long tom_k, base_k;
1281 if (read_option(CMOS_VSTART_interleave_chip_selects,
1282 CMOS_VLEN_interleave_chip_selects, 1) != 0) {
1283 tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
1285 printk_debug("Interleaving disabled\n");
1290 tom_k = order_chip_selects(ctrl);
1293 /* Compute the memory base address */
1294 base_k = memory_end_k(ctrl, ctrl->node_id);
1296 route_dram_accesses(ctrl, base_k, tom_k);
1297 set_top_mem(tom_k, 0);
1300 static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
1301 struct mem_info *meminfo)
1303 printk_debug("disabling dimm %02x\n", index);
1304 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
1305 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
1306 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
1308 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0);
1309 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0);
1310 #if QRANK_DIMM_SUPPORT == 1
1311 if (meminfo->sz[index].rank == 4) {
1312 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
1313 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
1318 meminfo->dimm_mask &= ~(1 << index);
1319 return meminfo->dimm_mask;
1322 static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
1323 struct mem_info *meminfo)
1326 uint32_t registered;
1329 for (i = 0; (i < DIMM_SOCKETS); i++) {
1331 u32 spd_device = ctrl->channel0[i];
1332 if (!(meminfo->dimm_mask & (1 << i))) {
1333 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1334 spd_device = ctrl->channel1[i];
1339 value = spd_read_byte(spd_device, SPD_DIMM_TYPE);
1344 /* Registered dimm ? */
1346 if ((value == SPD_DIMM_TYPE_RDIMM) || (value == SPD_DIMM_TYPE_mRDIMM)) {
1347 //check SPD_MOD_ATTRIB to verify it is SPD_MOD_ATTRIB_REGADC (0x11)?
1348 registered |= (1<<i);
1352 if (is_opteron(ctrl)) {
1354 if ( registered != (meminfo->dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) {
1355 meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffed dimm
1356 // die("Mixed buffered and registered dimms not supported");
1358 //By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM
1360 die("Unbuffered Dimms not supported on Opteron");
1366 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1367 dcl &= ~DCL_UnBuffDimm;
1368 meminfo->is_registered = 1;
1370 dcl |= DCL_UnBuffDimm;
1371 meminfo->is_registered = 0;
1373 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1375 if (meminfo->is_registered) {
1376 printk_spew("Registered\n");
1378 printk_spew("Unbuffered\n");
1380 return meminfo->dimm_mask;
1383 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
1388 for (i = 0; i < DIMM_SOCKETS; i++) {
1391 device = ctrl->channel0[i];
1392 printk_raminit("DIMM socket %i, channel 0 SPD device is 0x%02x\n", i, device);
1394 byte = spd_read_byte(ctrl->channel0[i], SPD_MEM_TYPE); /* Type */
1395 if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
1396 dimm_mask |= (1 << i);
1399 device = ctrl->channel1[i];
1400 printk_raminit("DIMM socket %i, channel 1 SPD device is 0x%02x\n", i, device);
1402 byte = spd_read_byte(ctrl->channel1[i], SPD_MEM_TYPE);
1403 if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
1404 dimm_mask |= (1 << (i + DIMM_SOCKETS));
1411 static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_info *meminfo)
1415 /* SPD addresses to verify are identical */
1416 static const uint8_t addresses[] = {
1417 2, /* Type should be DDR2 SDRAM */
1418 3, /* *Row addresses */
1419 4, /* *Column addresses */
1420 5, /* *Number of DIMM Ranks */
1421 6, /* *Module Data Width*/
1422 11, /* *DIMM Conf Type */
1423 13, /* *Pri SDRAM Width */
1424 17, /* *Logical Banks */
1425 20, /* *DIMM Type Info */
1426 21, /* *SDRAM Module Attributes */
1427 27, /* *tRP Row precharge time */
1428 28, /* *Minimum Row Active to Row Active Delay (tRRD) */
1429 29, /* *tRCD RAS to CAS */
1430 30, /* *tRAS Activate to Precharge */
1431 36, /* *Write recovery time (tWR) */
1432 37, /* *Internal write to read command delay (tRDP) */
1433 38, /* *Internal read to precharge command delay (tRTP) */
1434 40, /* *Extension of Byte 41 tRC and Byte 42 tRFC */
1435 41, /* *Minimum Active to Active/Auto Refresh Time(Trc) */
1436 42, /* *Minimum Auto Refresh Command Time(Trfc) */
1437 /* The SPD addresses 18, 9, 23, 26 need special treatment like
1438 * in spd_set_memclk. Right now they cause many false negatives.
1439 * Keep them at the end to see other mismatches (if any).
1441 18, /* *Supported CAS Latencies */
1442 9, /* *Cycle time at highest CAS Latency CL=X */
1443 23, /* *Cycle time at CAS Latency (CLX - 1) */
1444 26, /* *Cycle time at CAS Latency (CLX - 2) */
1449 /* S1G1 and AM2 sockets are Mod64BitMux capable. */
1450 #if CONFIG_CPU_SOCKET_TYPE == 0x11 || CONFIG_CPU_SOCKET_TYPE == 0x12
1456 /* If the dimms are not in pairs do not do dual channels */
1457 if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
1458 ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1459 goto single_channel;
1461 /* If the cpu is not capable of doing dual channels don't do dual channels */
1462 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1463 if (!(nbcap & NBCAP_128Bit)) {
1464 goto single_channel;
1466 for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
1467 unsigned device0, device1;
1470 /* If I don't have a dimm skip this one */
1471 if (!(meminfo->dimm_mask & (1 << i))) {
1474 device0 = ctrl->channel0[i];
1475 device1 = ctrl->channel1[i];
1476 /* Abort if the chips don't support a common CAS latency. */
1477 common_cl = spd_read_byte(device0, 18) & spd_read_byte(device1, 18);
1479 printk_debug("No common CAS latency supported\n");
1480 goto single_channel;
1482 printk_raminit("Common CAS latency bitfield: 0x%02x\n", common_cl);
1484 for (j = 0; j < ARRAY_SIZE(addresses); j++) {
1486 addr = addresses[j];
1487 value0 = spd_read_byte(device0, addr);
1491 value1 = spd_read_byte(device1, addr);
1495 if (value0 != value1) {
1496 printk_raminit("SPD values differ between channel 0/1 for byte %i\n", addr);
1497 goto single_channel;
1501 printk_spew("Enabling dual channel memory\n");
1502 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1503 dcl &= ~DCL_BurstLength32; /* 32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses
1504 32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode */
1505 dcl |= DCL_Width128;
1506 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1507 meminfo->is_Width128 = 1;
1508 return meminfo->dimm_mask;
1511 meminfo->is_Width128 = 0;
1512 meminfo->is_64MuxMode = 0;
1515 if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
1516 ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1517 if (((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1518 /* mux capable and single dimm in channelB */
1520 printk_spew("Enable 64MuxMode & BurstLength32\n");
1521 dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
1522 dcm |= DCM_Mode64BitMux;
1523 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
1524 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1525 //dcl |= DCL_BurstLength32; /* 32byte mode for channelB only */
1526 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1527 meminfo->is_64MuxMode = 1;
1529 meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
1532 } else { /* unmatched dual dimms ? */
1533 /* unmatched dual dimms not supported by meminit code. Use single channelA dimm. */
1534 meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
1535 printk_spew("Unmatched dual dimms. Use single channelA dimm.\n");
1537 return meminfo->dimm_mask;
1541 uint16_t cycle_time;
1542 uint8_t divisor; /* In 1/40 ns increments */
1547 uint8_t DcqByPassMax;
1548 uint32_t dch_memclk;
1552 static const struct mem_param speed[] = {
1555 .cycle_time = 0x500,
1556 .divisor = 200, // how many 1/40ns per clock
1557 .dch_memclk = DCH_MemClkFreq_200MHz, //0
1567 .cycle_time = 0x375,
1568 .divisor = 150, //????
1569 .dch_memclk = DCH_MemClkFreq_266MHz, //1
1578 .cycle_time = 0x300,
1580 .dch_memclk = DCH_MemClkFreq_333MHz, //2
1590 .cycle_time = 0x250,
1592 .dch_memclk = DCH_MemClkFreq_400MHz,//3
1600 .cycle_time = 0x000,
1604 static const struct mem_param *get_mem_param(unsigned min_cycle_time)
1607 const struct mem_param *param;
1608 for (param = &speed[0]; param->cycle_time ; param++) {
1609 if (min_cycle_time > (param+1)->cycle_time) {
1613 if (!param->cycle_time) {
1614 die("min_cycle_time to low");
1616 printk_spew("%s\n", param->name);
1620 static uint8_t get_exact_divisor(int i, uint8_t divisor)
1622 //input divisor could be 200(200), 150(266), 120(333), 100 (400)
1623 static const uint8_t dv_a[] = {
1624 /* 200 266 333 400 */
1625 /*4 */ 250, 250, 250, 250,
1626 /*5 */ 200, 200, 200, 100,
1627 /*6 */ 200, 166, 166, 100,
1628 /*7 */ 200, 171, 142, 100,
1630 /*8 */ 200, 150, 125, 100,
1631 /*9 */ 200, 156, 133, 100,
1632 /*10*/ 200, 160, 120, 100,
1633 /*11*/ 200, 163, 127, 100,
1635 /*12*/ 200, 150, 133, 100,
1636 /*13*/ 200, 153, 123, 100,
1637 /*14*/ 200, 157, 128, 100,
1638 /*15*/ 200, 160, 120, 100,
1645 /* Check for FID control support */
1646 struct cpuid_result cpuid1;
1647 cpuid1 = cpuid(0x80000007);
1648 if( cpuid1.edx & 0x02 ) {
1649 /* Use current FID */
1651 msr = rdmsr(0xc0010042);
1652 fid_cur = msr.lo & 0x3f;
1656 /* Use startup FID */
1658 msr = rdmsr(0xc0010015);
1659 fid_start = (msr.lo & (0x3f << 24));
1661 index = fid_start>>25;
1664 if (index>12) return divisor;
1666 if (i>3) return divisor;
1668 return dv_a[index * 4+i];
1673 struct spd_set_memclk_result {
1674 const struct mem_param *param;
1679 static unsigned convert_to_linear(unsigned value)
1681 static const unsigned fraction[] = { 0x25, 0x33, 0x66, 0x75 };
1684 /* We need to convert value to more readable */
1685 if ((value & 0xf) < 10) { //no .25, .33, .66, .75
1688 valuex = ((value & 0xf0) << 4) | fraction [(value & 0xf)-10];
1694 static const uint8_t latency_indicies[] = { 25, 23, 9 };
1696 int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time)
1698 int new_cycle_time, new_latency;
1703 /* First find the supported CAS latencies
1704 * Byte 18 for DDR SDRAM is interpreted:
1705 * bit 3 == CAS Latency = 3
1706 * bit 4 == CAS Latency = 4
1707 * bit 5 == CAS Latency = 5
1708 * bit 6 == CAS Latency = 6
1710 new_cycle_time = 0x500;
1713 latencies = spd_read_byte(spd_device, SPD_CAS_LAT);
1717 printk_raminit("\tlatencies: %08x\n", latencies);
1718 /* Compute the lowest cas latency which can be expressed in this
1719 * particular SPD EEPROM. You can store at most settings for 3
1720 * contiguous CAS latencies, so by taking the highest CAS
1721 * latency maked as supported in the SPD and subtracting 2 you
1722 * get the lowest expressable CAS latency. That latency is not
1723 * necessarily supported, but a (maybe invalid) entry exists
1726 latency = log2(latencies) - 2;
1728 /* Loop through and find a fast clock with a low latency */
1729 for (index = 0; index < 3; index++, latency++) {
1731 if ((latency < 3) || (latency > 6) ||
1732 (!(latencies & (1 << latency)))) {
1735 value = spd_read_byte(spd_device, latency_indicies[index]);
1740 printk_raminit("\tindex: %08x\n", index);
1741 printk_raminit("\t\tlatency: %08x\n", latency);
1742 printk_raminit("\t\tvalue1: %08x\n", value);
1744 value = convert_to_linear(value);
1746 printk_raminit("\t\tvalue2: %08x\n", value);
1748 /* Only increase the latency if we decrease the clock */
1749 if (value >= *min_cycle_time ) {
1750 if (value < new_cycle_time) {
1751 new_cycle_time = value;
1752 new_latency = latency;
1753 } else if (value == new_cycle_time) {
1754 if (new_latency > latency) {
1755 new_latency = latency;
1759 printk_raminit("\t\tnew_cycle_time: %08x\n", new_cycle_time);
1760 printk_raminit("\t\tnew_latency: %08x\n", new_latency);
1764 if (new_latency > 6){
1768 /* Does min_latency need to be increased? */
1769 if (new_cycle_time > *min_cycle_time) {
1770 *min_cycle_time = new_cycle_time;
1773 /* Does min_cycle_time need to be increased? */
1774 if (new_latency > *min_latency) {
1775 *min_latency = new_latency;
1778 printk_raminit("2 min_cycle_time: %08x\n", *min_cycle_time);
1779 printk_raminit("2 min_latency: %08x\n", *min_latency);
1784 static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, struct mem_info *meminfo)
1786 /* Compute the minimum cycle time for these dimms */
1787 struct spd_set_memclk_result result;
1788 unsigned min_cycle_time, min_latency, bios_cycle_time;
1792 static const uint16_t min_cycle_times[] = { // use full speed to compare
1793 [NBCAP_MEMCLK_NOLIMIT] = 0x250, /*2.5ns */
1794 [NBCAP_MEMCLK_333MHZ] = 0x300, /* 3.0ns */
1795 [NBCAP_MEMCLK_266MHZ] = 0x375, /* 3.75ns */
1796 [NBCAP_MEMCLK_200MHZ] = 0x500, /* 5.0s */
1800 value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1801 min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
1802 bios_cycle_time = min_cycle_times[
1803 read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
1804 if (bios_cycle_time > min_cycle_time) {
1805 min_cycle_time = bios_cycle_time;
1809 printk_raminit("1 min_cycle_time: %08x\n", min_cycle_time);
1811 /* Compute the least latency with the fastest clock supported
1812 * by both the memory controller and the dimms.
1814 for (i = 0; i < DIMM_SOCKETS; i++) {
1817 printk_raminit("1.1 dimm_mask: %08x\n", meminfo->dimm_mask);
1818 printk_raminit("i: %08x\n",i);
1820 if (meminfo->dimm_mask & (1 << i)) {
1821 spd_device = ctrl->channel0[i];
1822 printk_raminit("Channel 0 settings:\n");
1824 switch (find_optimum_spd_latency(spd_device, &min_latency, &min_cycle_time)) {
1832 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) {
1833 spd_device = ctrl->channel1[i];
1834 printk_raminit("Channel 1 settings:\n");
1836 switch (find_optimum_spd_latency(spd_device, &min_latency, &min_cycle_time)) {
1846 /* Make a second pass through the dimms and disable
1847 * any that cannot support the selected memclk and cas latency.
1850 printk_raminit("3 min_cycle_time: %08x\n", min_cycle_time);
1851 printk_raminit("3 min_latency: %08x\n", min_latency);
1853 for (i = 0; (i < DIMM_SOCKETS); i++) {
1858 u32 spd_device = ctrl->channel0[i];
1860 if (!(meminfo->dimm_mask & (1 << i))) {
1861 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1862 spd_device = ctrl->channel1[i];
1868 latencies = spd_read_byte(spd_device, SPD_CAS_LAT);
1869 if (latencies < 0) goto hw_error;
1870 if (latencies == 0) {
1874 /* Compute the lowest cas latency supported */
1875 latency = log2(latencies) -2;
1877 /* Walk through searching for the selected latency */
1878 for (index = 0; index < 3; index++, latency++) {
1879 if (!(latencies & (1 << latency))) {
1882 if (latency == min_latency)
1885 /* If I can't find the latency or my index is bad error */
1886 if ((latency != min_latency) || (index >= 3)) {
1890 /* Read the min_cycle_time for this latency */
1891 val = spd_read_byte(spd_device, latency_indicies[index]);
1892 if (val < 0) goto hw_error;
1894 val = convert_to_linear(val);
1895 /* All is good if the selected clock speed
1896 * is what I need or slower.
1898 if (val <= min_cycle_time) {
1901 /* Otherwise I have an error, disable the dimm */
1903 meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo);
1906 printk_raminit("4 min_cycle_time: %08x\n", min_cycle_time);
1908 /* Now that I know the minimum cycle time lookup the memory parameters */
1909 result.param = get_mem_param(min_cycle_time);
1911 /* Update DRAM Config High with our selected memory speed */
1912 value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
1913 value &= ~(DCH_MemClkFreq_MASK << DCH_MemClkFreq_SHIFT);
1915 value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT;
1916 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
1918 printk_debug("%s\n", result.param->name);
1920 /* Update DRAM Timing Low with our selected cas latency */
1921 value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1922 value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
1923 value |= (min_latency - DTL_TCL_BASE) << DTL_TCL_SHIFT;
1924 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
1926 result.dimm_mask = meminfo->dimm_mask;
1929 result.param = (const struct mem_param *)0;
1930 result.dimm_mask = -1;
1934 static unsigned convert_to_1_4(unsigned value)
1936 static const uint8_t fraction[] = { 0, 1, 2, 2, 3, 3, 0 };
1939 /* We need to convert value to more readable */
1940 valuex = fraction [value & 0x7];
1944 int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param)
1949 value = spd_read_byte(spd_device, SPD_TRC);
1952 printk_raminit("update_dimm_Trc: tRC (41) = %08x\n", value);
1954 value2 = spd_read_byte(spd_device, SPD_TRC -1);
1956 value += convert_to_1_4(value2>>4);
1959 printk_raminit("update_dimm_Trc: tRC final value = %i\n", value);
1961 clocks = (value + param->divisor - 1)/param->divisor;
1962 printk_raminit("update_dimm_Trc: clocks = %i\n", clocks);
1964 if (clocks < DTL_TRC_MIN) {
1965 #warning We should die here or at least disable this bank.
1966 printk_notice("update_dimm_Trc: can't refresh fast enough, "
1967 "want %i clocks, can %i clocks\n", clocks, DTL_TRC_MIN);
1968 clocks = DTL_TRC_MIN;
1973 static int update_dimm_Trc(const struct mem_controller *ctrl,
1974 const struct mem_param *param,
1975 int i, long dimm_mask)
1977 int clocks, old_clocks;
1979 u32 spd_device = ctrl->channel0[i];
1981 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
1982 spd_device = ctrl->channel1[i];
1985 clocks = get_dimm_Trc_clocks(spd_device, param);
1988 if (clocks > DTL_TRC_MAX) {
1991 printk_raminit("update_dimm_Trc: clocks after adjustment = %i\n", clocks);
1993 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1994 old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
1995 if (old_clocks >= clocks) { //?? someone did it
1996 // clocks = old_clocks;
1999 dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
2000 dtl |= ((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
2001 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
2005 static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i, struct mem_info *meminfo)
2007 unsigned clocks, old_clocks;
2011 u32 spd_device = ctrl->channel0[i];
2013 if (!(meminfo->dimm_mask & (1 << i)) && (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2014 spd_device = ctrl->channel1[i];
2015 ch_b = 2; /* offset to channelB trfc setting */
2018 //get the cs_size --> logic dimm size
2019 value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
2024 value = 6 - log2(value); //4-->4, 8-->3, 16-->2
2026 clocks = meminfo->sz[i].per_rank - 27 + 2 - value;
2028 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
2030 old_clocks = ((dth >> (DTH_TRFC0_SHIFT + ((i + ch_b) * 3))) & DTH_TRFC_MASK);
2032 if (old_clocks >= clocks) { // some one did it?
2035 dth &= ~(DTH_TRFC_MASK << (DTH_TRFC0_SHIFT + ((i + ch_b) * 3)));
2036 dth |= clocks << (DTH_TRFC0_SHIFT + ((i + ch_b) * 3));
2037 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2041 static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask,
2043 unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX )
2045 unsigned clocks, old_clocks;
2048 u32 spd_device = ctrl->channel0[i];
2050 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2051 spd_device = ctrl->channel1[i];
2054 value = spd_read_byte(spd_device, SPD_TT); //already in 1/4 ns
2055 if (value < 0) return -1;
2057 clocks = (value + param->divisor -1)/param->divisor;
2058 if (clocks < TT_MIN) {
2062 if (clocks > TT_MAX) {
2063 printk_info("warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
2067 dtl = pci_read_config32(ctrl->f2, TT_REG);
2069 old_clocks = ((dtl >> TT_SHIFT) & TT_MASK) + TT_BASE;
2070 if (old_clocks >= clocks) { //some one did it?
2071 // clocks = old_clocks;
2074 dtl &= ~(TT_MASK << TT_SHIFT);
2075 dtl |= ((clocks - TT_BASE) << TT_SHIFT);
2076 pci_write_config32(ctrl->f2, TT_REG, dtl);
2080 static int update_dimm_Trcd(const struct mem_controller *ctrl,
2081 const struct mem_param *param, int i, long dimm_mask)
2083 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRCD, DTL_TRCD_SHIFT, DTL_TRCD_MASK, DTL_TRCD_BASE, DTL_TRCD_MIN, DTL_TRCD_MAX);
2086 static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2088 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRRD, DTL_TRRD_SHIFT, DTL_TRRD_MASK, DTL_TRRD_BASE, DTL_TRRD_MIN, DTL_TRRD_MAX);
2091 static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2093 unsigned clocks, old_clocks;
2096 u32 spd_device = ctrl->channel0[i];
2098 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2099 spd_device = ctrl->channel1[i];
2102 value = spd_read_byte(spd_device, SPD_TRAS); //in 1 ns
2103 if (value < 0) return -1;
2104 printk_raminit("update_dimm_Tras: 0 value= %08x\n", value);
2106 value <<= 2; //convert it to in 1/4ns
2109 printk_raminit("update_dimm_Tras: 1 value= %08x\n", value);
2111 clocks = (value + param->divisor - 1)/param->divisor;
2112 printk_raminit("update_dimm_Tras: divisor= %08x\n", param->divisor);
2113 printk_raminit("update_dimm_Tras: clocks= %08x\n", clocks);
2114 if (clocks < DTL_TRAS_MIN) {
2115 clocks = DTL_TRAS_MIN;
2117 if (clocks > DTL_TRAS_MAX) {
2120 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
2121 old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
2122 if (old_clocks >= clocks) { // someone did it?
2125 dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
2126 dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
2127 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
2131 static int update_dimm_Trp(const struct mem_controller *ctrl,
2132 const struct mem_param *param, int i, long dimm_mask)
2134 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRP, DTL_TRP_SHIFT, DTL_TRP_MASK, DTL_TRP_BASE, DTL_TRP_MIN, DTL_TRP_MAX);
2138 static int update_dimm_Trtp(const struct mem_controller *ctrl,
2139 const struct mem_param *param, int i, struct mem_info *meminfo)
2141 /* need to figure if it is 32 byte burst or 64 bytes burst */
2143 if (!meminfo->is_Width128) {
2145 dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2146 if ((dword & DCL_BurstLength32)) offset = 0;
2148 return update_dimm_TT_1_4(ctrl, param, i, meminfo->dimm_mask, DRAM_TIMING_LOW, SPD_TRTP, DTL_TRTP_SHIFT, DTL_TRTP_MASK, DTL_TRTP_BASE+offset, DTL_TRTP_MIN+offset, DTL_TRTP_MAX+offset);
2152 static int update_dimm_Twr(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2154 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TWR, DTL_TWR_SHIFT, DTL_TWR_MASK, DTL_TWR_BASE, DTL_TWR_MIN, DTL_TWR_MAX);
2158 static int update_dimm_Tref(const struct mem_controller *ctrl,
2159 const struct mem_param *param, int i, long dimm_mask)
2161 uint32_t dth, dth_old;
2163 u32 spd_device = ctrl->channel0[i];
2165 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2166 spd_device = ctrl->channel1[i];
2169 value = spd_read_byte(spd_device, SPD_TREF); // 0: 15.625us, 1: 3.9us 2: 7.8 us....
2170 if (value < 0) return -1;
2178 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
2181 dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
2182 dth |= (value << DTH_TREF_SHIFT);
2183 if (dth_old != dth) {
2184 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2189 static void set_4RankRDimm(const struct mem_controller *ctrl,
2190 const struct mem_param *param, struct mem_info *meminfo)
2192 #if QRANK_DIMM_SUPPORT == 1
2195 long dimm_mask = meminfo->dimm_mask;
2198 if (!(meminfo->is_registered)) return;
2202 for (i = 0; i < DIMM_SOCKETS; i++) {
2203 if (!(dimm_mask & (1 << i))) {
2207 if (meminfo->sz[i].rank == 4) {
2215 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2216 dch |= DCH_FourRankRDimm;
2217 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2222 static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
2223 struct mem_info *meminfo)
2229 uint32_t mask_single_rank;
2230 uint32_t mask_page_1k;
2232 #if QRANK_DIMM_SUPPORT == 1
2236 long dimm_mask = meminfo->dimm_mask;
2241 mask_single_rank = 0;
2244 for (i = 0; i < DIMM_SOCKETS; i++) {
2245 u32 spd_device = ctrl->channel0[i];
2246 if (!(dimm_mask & (1 << i))) {
2247 if (dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
2248 spd_device = ctrl->channel1[i];
2254 if (meminfo->sz[i].rank == 1) {
2255 mask_single_rank |= 1<<i;
2258 if (meminfo->sz[i].col==10) {
2259 mask_page_1k |= 1<<i;
2263 value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
2265 #if QRANK_DIMM_SUPPORT == 1
2266 rank = meminfo->sz[i].rank;
2271 #if QRANK_DIMM_SUPPORT == 1
2273 mask_x4 |= 1<<(i+2);
2276 } else if (value==16) {
2278 #if QRANK_DIMM_SUPPORT == 1
2280 mask_x16 |= 1<<(i+2);
2287 meminfo->x4_mask= mask_x4;
2288 meminfo->x16_mask = mask_x16;
2290 meminfo->single_rank_mask = mask_single_rank;
2291 meminfo->page_1k_mask = mask_page_1k;
2298 static void set_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2301 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2302 dcl &= ~(DCL_X4Dimm_MASK<<DCL_X4Dimm_SHIFT);
2303 dcl |= ((meminfo->x4_mask) & 0xf) << (DCL_X4Dimm_SHIFT);
2304 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2308 static int count_ones(uint32_t dimm_mask)
2313 for (index = 0; index < (2 * DIMM_SOCKETS); index++, dimm_mask >>= 1) {
2314 if (dimm_mask & 1) {
2322 static void set_DramTerm(const struct mem_controller *ctrl,
2323 const struct mem_param *param, struct mem_info *meminfo)
2329 if (param->divisor == 100) { //DDR2 800
2330 if (meminfo->is_Width128) {
2331 if (count_ones(meminfo->dimm_mask & 0x0f)==2) {
2339 #if CONFIG_DIMM_SUPPORT == 0x0204
2340 odt = 0x2; /* 150 ohms */
2343 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2344 dcl &= ~(DCL_DramTerm_MASK<<DCL_DramTerm_SHIFT);
2345 dcl |= (odt & DCL_DramTerm_MASK) << (DCL_DramTerm_SHIFT);
2346 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2349 static void set_ecc(const struct mem_controller *ctrl,
2350 const struct mem_param *param, struct mem_info *meminfo)
2355 uint32_t dcl, nbcap;
2356 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
2357 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2358 dcl &= ~DCL_DimmEccEn;
2359 if (nbcap & NBCAP_ECC) {
2360 dcl |= DCL_DimmEccEn;
2362 if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
2363 dcl &= ~DCL_DimmEccEn;
2365 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2367 meminfo->is_ecc = 1;
2368 if (!(dcl & DCL_DimmEccEn)) {
2369 meminfo->is_ecc = 0;
2370 return; // already disabled the ECC, so don't need to read SPD any more
2373 for (i = 0; i < DIMM_SOCKETS; i++) {
2374 u32 spd_device = ctrl->channel0[i];
2375 if (!(meminfo->dimm_mask & (1 << i))) {
2376 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
2377 spd_device = ctrl->channel1[i];
2378 printk_debug("set_ecc spd_device: 0x%x\n", spd_device);
2384 value = spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONF_TYPE);
2386 if (!(value & SPD_DIMM_CONF_TYPE_ECC)) {
2387 dcl &= ~DCL_DimmEccEn;
2388 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2389 meminfo->is_ecc = 0;
2397 static int update_dimm_Twtr(const struct mem_controller *ctrl,
2398 const struct mem_param *param, int i, long dimm_mask)
2400 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_HIGH, SPD_TWTR, DTH_TWTR_SHIFT, DTH_TWTR_MASK, DTH_TWTR_BASE, DTH_TWTR_MIN, DTH_TWTR_MAX);
2403 static void set_TT(const struct mem_controller *ctrl,
2404 const struct mem_param *param, unsigned TT_REG, unsigned TT_SHIFT,
2405 unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX,
2406 unsigned val, const char *str)
2410 if ((val < TT_MIN) || (val > TT_MAX)) {
2415 reg = pci_read_config32(ctrl->f2, TT_REG);
2416 reg &= ~(TT_MASK << TT_SHIFT);
2417 reg |= ((val - TT_BASE) << TT_SHIFT);
2418 pci_write_config32(ctrl->f2, TT_REG, reg);
2423 static void set_TrwtTO(const struct mem_controller *ctrl,
2424 const struct mem_param *param)
2426 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRWTTO_SHIFT, DTH_TRWTTO_MASK,DTH_TRWTTO_BASE, DTH_TRWTTO_MIN, DTH_TRWTTO_MAX, param->TrwtTO, "TrwtTO");
2430 static void set_Twrrd(const struct mem_controller *ctrl, const struct mem_param *param)
2432 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRRD_SHIFT, DTH_TWRRD_MASK,DTH_TWRRD_BASE, DTH_TWRRD_MIN, DTH_TWRRD_MAX, param->Twrrd, "Twrrd");
2436 static void set_Twrwr(const struct mem_controller *ctrl, const struct mem_param *param)
2438 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRWR_SHIFT, DTH_TWRWR_MASK,DTH_TWRWR_BASE, DTH_TWRWR_MIN, DTH_TWRWR_MAX, param->Twrwr, "Twrwr");
2441 static void set_Trdrd(const struct mem_controller *ctrl, const struct mem_param *param)
2443 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRDRD_SHIFT, DTH_TRDRD_MASK,DTH_TRDRD_BASE, DTH_TRDRD_MIN, DTH_TRDRD_MAX, param->Trdrd, "Trdrd");
2446 static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem_param *param)
2448 set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS
2451 static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2453 static const uint8_t faw_1k[] = {8, 10, 13, 14};
2454 static const uint8_t faw_2k[] = {10, 14, 17, 18};
2455 unsigned memclkfreq_index;
2459 memclkfreq_index = param->dch_memclk;
2461 if (meminfo->page_1k_mask != 0) { //1k page
2462 faw = faw_1k[memclkfreq_index];
2464 faw = faw_2k[memclkfreq_index];
2467 set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_FourActWindow_SHIFT, DCH_FourActWindow_MASK, DCH_FourActWindow_BASE, DCH_FourActWindow_MIN, DCH_FourActWindow_MAX, faw, "FourActWindow");
2470 static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
2476 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2477 dch &= ~(DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT);
2479 //FIXME: We need to use Max of DqsRcvEnDelay + 6ns here: After trainning and get that from index reg 0x10, 0x13, 0x16, 0x19, 0x30, 0x33, 0x36, 0x39
2483 dch |= ((async_lat - DCH_MaxAsyncLat_BASE) << DCH_MaxAsyncLat_SHIFT);
2484 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2487 static void set_SlowAccessMode(const struct mem_controller *ctrl)
2491 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2495 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2499 DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20
2500 DRAM_ADDR_TIMING_CTRL 04, 0x24
2502 static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *meminfo)
2506 #if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
2507 unsigned SlowAccessMode = 0;
2510 long dimm_mask = meminfo->dimm_mask & 0x0f;
2512 #if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */
2515 dwordx = 0x002f0000;
2516 switch (meminfo->memclk_set) {
2517 case DCH_MemClkFreq_266MHz:
2518 if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
2519 dwordx = 0x002f2700;
2522 case DCH_MemClkFreq_333MHz:
2523 if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
2524 if ((meminfo->single_rank_mask & 0x03)!=0x03) { //any double rank there?
2525 dwordx = 0x002f2f00;
2529 case DCH_MemClkFreq_400MHz:
2530 dwordx = 0x002f3300;
2536 #if CONFIG_DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */
2538 dwordx = 0x002F2F00;
2540 switch (meminfo->memclk_set) {
2541 case DCH_MemClkFreq_200MHz: /* nothing to be set here */
2543 case DCH_MemClkFreq_266MHz:
2544 if ((meminfo->single_rank_mask == 0)
2545 && (meminfo->x4_mask == 0) && (meminfo->x16_mask))
2546 dwordx = 0x002C2C00; /* Double rank x8 */
2547 /* else SRx16, SRx8, DRx16 == 0x002F2F00 */
2549 case DCH_MemClkFreq_333MHz:
2550 if ((meminfo->single_rank_mask == 1)
2551 && (meminfo->x16_mask == 1)) /* SR x16 */
2552 dwordx = 0x00272700;
2553 else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
2554 && (meminfo->single_rank_mask == 0)) { /* DR x8 */
2556 dwordx = 0x00002800;
2557 } else { /* SR x8, DR x16 */
2558 dwordx = 0x002A2A00;
2561 case DCH_MemClkFreq_400MHz:
2562 if ((meminfo->single_rank_mask == 1)
2563 && (meminfo->x16_mask == 1)) /* SR x16 */
2564 dwordx = 0x00292900;
2565 else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
2566 && (meminfo->single_rank_mask == 0)) { /* DR x8 */
2568 dwordx = 0x00002A00;
2569 } else { /* SR x8, DR x16 */
2570 dwordx = 0x002A2A00;
2576 #if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */
2577 /* for UNBUF DIMM */
2579 dwordx = 0x002f2f00;
2580 switch (meminfo->memclk_set) {
2581 case DCH_MemClkFreq_200MHz:
2582 if (dimm_mask == 0x03) {
2587 case DCH_MemClkFreq_266MHz:
2588 if (dimm_mask == 0x03) {
2591 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
2592 switch (meminfo->single_rank_mask) {
2594 dwordx = 0x00002f00; //x8 single Rank
2597 dwordx = 0x00342f00; //x8 double Rank
2600 dwordx = 0x00372f00; //x8 single Rank and double Rank mixed
2602 } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
2603 dwordx = 0x00382f00; //x8 Double Rank and x16 single Rank mixed
2604 } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
2605 dwordx = 0x00382f00; //x16 single Rank and x8 double Rank mixed
2609 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank
2610 dwordx = 0x002f2f00;
2612 dwordx = 0x002b2f00;
2616 case DCH_MemClkFreq_333MHz:
2617 dwordx = 0x00202220;
2618 if (dimm_mask == 0x03) {
2621 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
2622 switch (meminfo->single_rank_mask) {
2624 dwordx = 0x00302220; //x8 single Rank
2627 dwordx = 0x002b2220; //x8 double Rank
2630 dwordx = 0x002a2220; //x8 single Rank and double Rank mixed
2632 } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
2633 dwordx = 0x002c2220; //x8 Double Rank and x16 single Rank mixed
2634 } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
2635 dwordx = 0x002c2220; //x16 single Rank and x8 double Rank mixed
2639 case DCH_MemClkFreq_400MHz:
2640 dwordx = 0x00202520;
2642 if (dimm_mask == 0x03) {
2650 printk_raminit("\tdimm_mask = %08x\n", meminfo->dimm_mask);
2651 printk_raminit("\tx4_mask = %08x\n", meminfo->x4_mask);
2652 printk_raminit("\tx16_mask = %08x\n", meminfo->x16_mask);
2653 printk_raminit("\tsingle_rank_mask = %08x\n", meminfo->single_rank_mask);
2654 printk_raminit("\tODC = %08x\n", dword);
2655 printk_raminit("\tAddr Timing= %08x\n", dwordx);
2658 #if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
2659 if (SlowAccessMode) {
2660 set_SlowAccessMode(ctrl);
2664 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
2665 /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */
2666 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword);
2668 /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */
2669 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx);
2671 /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */
2672 pci_write_config32_index_wait(ctrl->f2, 0x98, 0, dword);
2673 if (meminfo->is_Width128) {
2674 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword);
2677 /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */
2678 pci_write_config32_index_wait(ctrl->f2, 0x98, 4, dwordx);
2679 if (meminfo->is_Width128) {
2680 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx);
2686 static void set_RDqsEn(const struct mem_controller *ctrl,
2687 const struct mem_param *param, struct mem_info *meminfo)
2689 #if CONFIG_CPU_SOCKET_TYPE==0x10
2690 //only need to set for reg and x8
2693 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2696 if ((!meminfo->x4_mask) && (!meminfo->x16_mask)) {
2700 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2704 static void set_idle_cycle_limit(const struct mem_controller *ctrl,
2705 const struct mem_param *param)
2708 /* AMD says to Hardcode this */
2709 dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
2710 dcm &= ~(DCM_ILD_lmt_MASK << DCM_ILD_lmt_SHIFT);
2711 dcm |= DCM_ILD_lmt_16 << DCM_ILD_lmt_SHIFT;
2713 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
2716 static void set_RdWrQByp(const struct mem_controller *ctrl,
2717 const struct mem_param *param)
2719 set_TT(ctrl, param, DRAM_CTRL_MISC, DCM_RdWrQByp_SHIFT, DCM_RdWrQByp_MASK,0, 0, 3, 2, "RdWrQByp");
2722 static long spd_set_dram_timing(const struct mem_controller *ctrl,
2723 const struct mem_param *param,
2724 struct mem_info *meminfo)
2728 for (i = 0; i < DIMM_SOCKETS; i++) {
2730 if (!(meminfo->dimm_mask & (1 << i)) &&
2731 !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) ) {
2734 printk_raminit("spd_set_dram_timing dimm socket: %08x\n", i);
2735 /* DRAM Timing Low Register */
2736 printk_raminit("\ttrc\n");
2737 if ((rc = update_dimm_Trc (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2739 printk_raminit("\ttrcd\n");
2740 if ((rc = update_dimm_Trcd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2742 printk_raminit("\ttrrd\n");
2743 if ((rc = update_dimm_Trrd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2745 printk_raminit("\ttras\n");
2746 if ((rc = update_dimm_Tras(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2748 printk_raminit("\ttrp\n");
2749 if ((rc = update_dimm_Trp (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2751 printk_raminit("\ttrtp\n");
2752 if ((rc = update_dimm_Trtp(ctrl, param, i, meminfo)) <= 0) goto dimm_err;
2754 printk_raminit("\ttwr\n");
2755 if ((rc = update_dimm_Twr (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2757 /* DRAM Timing High Register */
2758 printk_raminit("\ttref\n");
2759 if ((rc = update_dimm_Tref(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2761 printk_raminit("\ttwtr\n");
2762 if ((rc = update_dimm_Twtr(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2764 printk_raminit("\ttrfc\n");
2765 if ((rc = update_dimm_Trfc(ctrl, param, i, meminfo)) <= 0) goto dimm_err;
2767 /* DRAM Config Low */
2771 printk_debug("spd_set_dram_timing dimm_err!\n");
2775 meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo);
2778 get_extra_dimm_mask(ctrl, meminfo); // will be used by RDqsEn and dimm_x4
2779 /* DRAM Timing Low Register */
2781 /* DRAM Timing High Register */
2782 set_TrwtTO(ctrl, param);
2783 set_Twrrd (ctrl, param);
2784 set_Twrwr (ctrl, param);
2785 set_Trdrd (ctrl, param);
2787 set_4RankRDimm(ctrl, param, meminfo);
2789 /* DRAM Config High */
2790 set_Tfaw(ctrl, param, meminfo);
2791 set_DcqBypassMax(ctrl, param);
2792 set_max_async_latency(ctrl, param);
2793 set_RDqsEn(ctrl, param, meminfo);
2795 /* DRAM Config Low */
2796 set_ecc(ctrl, param, meminfo);
2797 set_dimm_x4(ctrl, param, meminfo);
2798 set_DramTerm(ctrl, param, meminfo);
2800 /* DRAM Control Misc */
2801 set_idle_cycle_limit(ctrl, param);
2802 set_RdWrQByp(ctrl, param);
2804 return meminfo->dimm_mask;
2807 static void sdram_set_spd_registers(const struct mem_controller *ctrl,
2808 struct sys_info *sysinfo)
2810 struct spd_set_memclk_result result;
2811 const struct mem_param *param;
2812 struct mem_param paramx;
2813 struct mem_info *meminfo;
2815 if (!sysinfo->ctrl_present[ctrl->node_id]) {
2819 meminfo = &sysinfo->meminfo[ctrl->node_id];
2821 printk_debug("sdram_set_spd_registers: paramx :%p\n", ¶mx);
2823 activate_spd_rom(ctrl);
2824 meminfo->dimm_mask = spd_detect_dimms(ctrl);
2826 printk_raminit("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask);
2828 if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1)))
2830 printk_debug("No memory for this cpu\n");
2833 meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo);
2834 printk_raminit("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask);
2835 if (meminfo->dimm_mask == -1)
2838 meminfo->dimm_mask = spd_set_ram_size(ctrl, meminfo);
2839 printk_raminit("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask);
2840 if (meminfo->dimm_mask == -1)
2843 meminfo->dimm_mask = spd_handle_unbuffered_dimms(ctrl, meminfo);
2844 printk_raminit("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask);
2845 if (meminfo->dimm_mask == -1)
2848 result = spd_set_memclk(ctrl, meminfo);
2849 param = result.param;
2850 meminfo->dimm_mask = result.dimm_mask;
2851 printk_raminit("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask);
2852 if (meminfo->dimm_mask == -1)
2855 //store memclk set to sysinfo, incase we need rebuilt param again
2856 meminfo->memclk_set = param->dch_memclk;
2858 memcpy(¶mx, param, sizeof(paramx));
2860 paramx.divisor = get_exact_divisor(param->dch_memclk, paramx.divisor);
2862 meminfo->dimm_mask = spd_set_dram_timing(ctrl, ¶mx, meminfo);
2863 printk_raminit("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask);
2864 if (meminfo->dimm_mask == -1)
2867 order_dimms(ctrl, meminfo);
2871 /* Unrecoverable error reading SPD data */
2872 die("Unrecoverable error reading SPD data. No qualified DIMMs?");
2876 #define TIMEOUT_LOOPS 300000
2878 #include "raminit_f_dqs.c"
2880 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
2881 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i)
2884 uint32_t carry_over;
2886 uint32_t base, limit;
2891 carry_over = (4*1024*1024) - hole_startk;
2893 for (ii=controllers - 1;ii>i;ii--) {
2894 base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
2895 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2898 limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
2899 limit += (carry_over << 2 );
2900 base += (carry_over << 2 );
2901 for (j = 0; j < controllers; j++) {
2902 pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit);
2903 pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base );
2906 limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
2907 limit += (carry_over << 2);
2908 for (j = 0; j < controllers; j++) {
2909 pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit);
2912 base = pci_read_config32(dev, 0x40 + (i << 3));
2913 basek = (base & 0xffff0000) >> 2;
2914 if (basek == hole_startk) {
2915 //don't need set memhole here, because hole off set will be 0, overflow
2916 //so need to change base reg instead, new basek will be 4*1024*1024
2918 base |= (4*1024*1024)<<2;
2919 for (j = 0; j < controllers; j++) {
2920 pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
2923 hoist = /* hole start address */
2924 ((hole_startk << 10) & 0xff000000) +
2925 /* hole address to memory controller address */
2926 (((basek + carry_over) >> 6) & 0x0000ff00) +
2929 pci_write_config32(dev, 0xf0, hoist);
2935 static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
2938 uint32_t hole_startk;
2941 hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
2943 printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk);
2944 #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
2945 /* We need to double check if the hole_startk is valid, if it is equal
2946 to basek, we need to decrease it some */
2948 for (i=0; i<controllers; i++) {
2951 base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
2952 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2955 base_k = (base & 0xffff0000) >> 2;
2956 if (base_k == hole_startk) {
2957 /* decrease mem hole startk to make sure it is
2958 on middle of previous node */
2959 hole_startk -= (base_k - basek_pri) >> 1;
2960 break; //only one hole
2964 printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
2966 /* find node index that need do set hole */
2967 for (i=0; i < controllers; i++) {
2968 uint32_t base, limit;
2969 unsigned base_k, limit_k;
2970 base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
2971 if ((base & ((1 << 1) | (1 << 0))) != ((1 << 1) | (1 << 0))) {
2974 limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
2975 base_k = (base & 0xffff0000) >> 2;
2976 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
2977 if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
2979 hoist_memory(controllers, ctrl, hole_startk, i);
2980 end_k = memory_end_k(ctrl, controllers);
2981 set_top_mem(end_k, hole_startk);
2982 break; //only one hole
2989 #include "exit_from_self.c"
2991 static void sdram_enable(int controllers, const struct mem_controller *ctrl,
2992 struct sys_info *sysinfo)
2995 #ifdef ACPI_IS_WAKEUP_EARLY
2996 int suspend = acpi_is_wakeup_early();
3001 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3002 unsigned cpu_f0_f1[8];
3003 /* FIXME: How about 32 node machine later? */
3006 printk_debug("sdram_enable: tsc0[8]: %p", &tsc0[0]);
3010 /* Error if I don't have memory */
3011 if (memory_end_k(ctrl, controllers) == 0) {
3015 /* Before enabling memory start the memory clocks */
3016 for (i = 0; i < controllers; i++) {
3018 if (!sysinfo->ctrl_present[ i ])
3020 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
3022 /* if no memory installed, disabled the interface */
3023 if (sysinfo->meminfo[i].dimm_mask==0x00){
3024 dch |= DCH_DisDramInterface;
3025 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
3028 dch |= DCH_MemClkFreqVal;
3029 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
3030 /* address timing and Output driver comp Control */
3031 set_misc_timing(ctrl+i, sysinfo->meminfo+i );
3035 /* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */
3036 memreset(controllers, ctrl);
3038 /* lets override the rest of the routine */
3040 printk_debug("Wakeup!\n");
3041 exit_from_self(controllers, ctrl, sysinfo);
3042 printk_debug("Mem running !\n");
3046 for (i = 0; i < controllers; i++) {
3048 if (!sysinfo->ctrl_present[ i ])
3050 /* Skip everything if I don't have any memory on this controller */
3051 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
3052 if (!(dch & DCH_MemClkFreqVal)) {
3057 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
3058 if (dcl & DCL_DimmEccEn) {
3060 printk_spew("ECC enabled\n");
3061 mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
3063 if (dcl & DCL_Width128) {
3064 mnc |= MNC_CHIPKILL_EN;
3066 pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
3069 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3070 cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i);
3072 //Rev F0/F1 workaround
3074 /* Set the DqsRcvEnTrain bit */
3075 dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
3076 dword |= DC_DqsRcvEnTrain;
3077 pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
3083 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
3084 dcl |= DCL_InitDram;
3085 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
3088 for (i = 0; i < controllers; i++) {
3090 if (!sysinfo->ctrl_present[ i ])
3092 /* Skip everything if I don't have any memory on this controller */
3093 if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
3095 printk_debug("Initializing memory: ");
3098 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
3100 if ((loops & 1023) == 0) {
3103 } while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS));
3104 if (loops >= TIMEOUT_LOOPS) {
3105 printk_debug(" failed\n");
3109 /* Wait until it is safe to touch memory */
3111 dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
3112 } while(((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ );
3114 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3118 print_debug_dqs_tsc("\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
3119 print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2);
3121 if (tsc.lo<tsc0[i].lo) {
3124 tsc.lo -= tsc0[i].lo;
3125 tsc.hi -= tsc0[i].hi;
3127 tsc0[i].lo = tsc.lo;
3128 tsc0[i].hi = tsc.hi;
3130 print_debug_dqs_tsc(" dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
3133 printk_debug(" done\n");
3136 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
3137 /* init hw mem hole here */
3138 /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
3139 set_hw_mem_hole(controllers, ctrl);
3142 /* store tom to sysinfo, and it will be used by dqs_timing */
3146 msr = rdmsr(TOP_MEM);
3147 sysinfo->tom_k = ((msr.hi<<24) | (msr.lo>>8))>>2;
3150 msr = rdmsr(TOP_MEM2);
3151 sysinfo->tom2_k = ((msr.hi<<24)| (msr.lo>>8))>>2;
3154 for (i = 0; i < controllers; i++) {
3155 sysinfo->mem_trained[i] = 0;
3157 if (!sysinfo->ctrl_present[ i ])
3160 /* Skip everything if I don't have any memory on this controller */
3161 if (sysinfo->meminfo[i].dimm_mask==0x00)
3164 sysinfo->mem_trained[i] = 0x80; // mem need to be trained
3168 #if CONFIG_MEM_TRAIN_SEQ == 0
3169 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3170 dqs_timing(controllers, ctrl, tsc0, sysinfo);
3172 dqs_timing(controllers, ctrl, sysinfo);
3176 #if CONFIG_MEM_TRAIN_SEQ == 2
3177 /* need to enable mtrr, so dqs training could access the test address */
3178 setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
3181 for (i = 0; i < controllers; i++) {
3182 /* Skip everything if I don't have any memory on this controller */
3183 if (sysinfo->mem_trained[i]!=0x80)
3186 dqs_timing(i, &ctrl[i], sysinfo, 1);
3188 #if CONFIG_MEM_TRAIN_SEQ == 1
3189 break; // only train the first node with ram
3193 #if CONFIG_MEM_TRAIN_SEQ == 2
3194 clear_mtrr_dqs(sysinfo->tom2_k);
3199 #if CONFIG_MEM_TRAIN_SEQ != 1
3200 wait_all_core0_mem_trained(sysinfo);
3205 static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
3206 const uint16_t *spd_addr)
3210 struct mem_controller *ctrl;
3211 for (i=0;i<controllers; i++) {
3214 ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
3215 ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
3216 ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
3217 ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
3219 if (spd_addr == (void *)0) continue;
3221 for (j=0;j<DIMM_SOCKETS;j++) {
3222 ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
3223 ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];