2 * This file is part of the coreboot project.
4 * Copyright (C) 2002 Linux Networx
5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
6 * Copyright (C) 2004 YingHai Lu
7 * Copyright (C) 2008 Advanced Micro Devices, Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <cpu/x86/cache.h>
24 #include <cpu/x86/mtrr.h>
25 #include <cpu/x86/tsc.h>
32 #ifndef QRANK_DIMM_SUPPORT
33 #define QRANK_DIMM_SUPPORT 0
36 #if CONFIG_DEBUG_RAM_SETUP
37 #define printk_raminit(fmt, arg...) printk(BIOS_DEBUG, fmt, arg)
39 #define printk_raminit(fmt, arg...)
43 #if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
44 # error "CONFIG_RAMTOP must be a power of 2"
47 #include "amdk8_f_pci.c"
50 /* for PCI_ADDR(0, 0x18, 2, 0x98) index,
51 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
54 [29: 0] DctOffset (Dram Controller Offset)
55 [30:30] DctAccessWrite (Dram Controller Read/Write Select)
58 [31:31] DctAccessDone (Dram Controller Access Done)
59 0 = Access in progress
60 1 = No access is progress
63 [31: 0] DctOffsetData (Dram Controller Offset Data)
66 - Write the register num to DctOffset with
68 - poll the DctAccessDone until it = 1
69 - Read the data from DctOffsetData
71 - Write the data to DctOffsetData
72 - Write register num to DctOffset with DctAccessWrite = 1
73 - poll the DctAccessDone untio it = 1
77 static void setup_resource_map(const unsigned int *register_values, int max)
80 for (i = 0; i < max; i += 3) {
84 dev = register_values[i] & ~0xff;
85 where = register_values[i] & 0xff;
86 reg = pci_read_config32(dev, where);
87 reg &= register_values[i+1];
88 reg |= register_values[i+2];
89 pci_write_config32(dev, where, reg);
93 static int controller_present(const struct mem_controller *ctrl)
95 return pci_read_config32(ctrl->f0, 0) == 0x11001022;
98 static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
100 static const unsigned int register_values[] = {
102 /* Careful set limit registers before base registers which
103 contain the enables */
104 /* DRAM Limit i Registers
113 * [ 2: 0] Destination Node ID
123 * [10: 8] Interleave select
124 * specifies the values of A[14:12] to use with interleave enable.
126 * [31:16] DRAM Limit Address i Bits 39-24
127 * This field defines the upper address bits of a 40 bit address
128 * that define the end of the DRAM region.
130 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
131 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
132 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
133 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
134 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
135 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
136 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
137 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
138 /* DRAM Base i Registers
147 * [ 0: 0] Read Enable
150 * [ 1: 1] Write Enable
151 * 0 = Writes Disabled
154 * [10: 8] Interleave Enable
155 * 000 = No interleave
156 * 001 = Interleave on A[12] (2 nodes)
158 * 011 = Interleave on A[12] and A[14] (4 nodes)
162 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
164 * [13:16] DRAM Base Address i Bits 39-24
165 * This field defines the upper address bits of a 40-bit address
166 * that define the start of the DRAM region.
168 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
169 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
170 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
171 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
172 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
173 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
174 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
175 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
177 /* DRAM CS Base Address i Registers
186 * [ 0: 0] Chip-Select Bank Enable
190 * [ 2: 2] Memory Test Failed
192 * [13: 5] Base Address (21-13)
193 * An optimization used when all DIMM are the same size...
195 * [28:19] Base Address (36-27)
196 * This field defines the top 11 addresses bit of a 40-bit
197 * address that define the memory address space. These
198 * bits decode 32-MByte blocks of memory.
201 PCI_ADDR(0, 0x18, 2, 0x40), 0xe007c018, 0x00000000,
202 PCI_ADDR(0, 0x18, 2, 0x44), 0xe007c018, 0x00000000,
203 PCI_ADDR(0, 0x18, 2, 0x48), 0xe007c018, 0x00000000,
204 PCI_ADDR(0, 0x18, 2, 0x4C), 0xe007c018, 0x00000000,
205 PCI_ADDR(0, 0x18, 2, 0x50), 0xe007c018, 0x00000000,
206 PCI_ADDR(0, 0x18, 2, 0x54), 0xe007c018, 0x00000000,
207 PCI_ADDR(0, 0x18, 2, 0x58), 0xe007c018, 0x00000000,
208 PCI_ADDR(0, 0x18, 2, 0x5C), 0xe007c018, 0x00000000,
209 /* DRAM CS Mask Address i Registers
214 * Select bits to exclude from comparison with the DRAM Base address register.
216 * [13: 5] Address Mask (21-13)
217 * Address to be excluded from the optimized case
219 * [28:19] Address Mask (36-27)
220 * The bits with an address mask of 1 are excluded from address comparison
224 PCI_ADDR(0, 0x18, 2, 0x60), 0xe007c01f, 0x00000000,
225 PCI_ADDR(0, 0x18, 2, 0x64), 0xe007c01f, 0x00000000,
226 PCI_ADDR(0, 0x18, 2, 0x68), 0xe007c01f, 0x00000000,
227 PCI_ADDR(0, 0x18, 2, 0x6C), 0xe007c01f, 0x00000000,
229 /* DRAM Control Register
231 * [ 3: 0] RdPtrInit ( Read Pointer Initial Value)
232 * 0x03-0x00: reserved
233 * [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO)
236 * 010 = 1.5 Memory Clocks
237 * 011 = 2 Memory Clocks
238 * 100 = 2.5 Memory Clocks
239 * 101 = 3 Memory Clocks
240 * 110 = 3.5 Memory Clocks
243 * [16:16] AltVidC3MemClkTriEn (AltVID Memory Clock Tristate Enable)
244 * Enables the DDR memory clocks to be tristated when alternate VID
245 * mode is enabled. This bit has no effect if the DisNbClkRamp bit
247 * [17:17] DllTempAdjTime (DLL Temperature Adjust Cycle Time)
250 * [18:18] DqsRcvEnTrain (DQS Receiver Enable Training Mode)
251 * 0 = Normal DQS Receiver enable operation
252 * 1 = DQS receiver enable training mode
255 PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6<<4)|(6<<0),
257 /* DRAM Initialization Register
259 * [15: 0] MrsAddress (Address for MRS/EMRS Commands)
260 * this field specifies the dsata driven on the DRAM address pins
261 * 15-0 for MRS and EMRS commands
262 * [18:16] MrsBank (Bank Address for MRS/EMRS Commands)
263 * this files specifies the data driven on the DRAM bank pins for
264 * the MRS and EMRS commands
266 * [24:24] SendPchgAll (Send Precharge All Command)
267 * Setting this bit causes the DRAM controller to send a precharge
268 * all command. This bit is cleared by the hardware after the
270 * [25:25] SendAutoRefresh (Send Auto Refresh Command)
271 * Setting this bit causes the DRAM controller to send an auto
272 * refresh command. This bit is cleared by the hardware after the
274 * [26:26] SendMrsCmd (Send MRS/EMRS Command)
275 * Setting this bit causes the DRAM controller to send the MRS or
276 * EMRS command defined by the MrsAddress and MrsBank fields. This
277 * bit is cleared by the hardware adter the commmand completes
278 * [27:27] DeassertMemRstX (De-assert Memory Reset)
279 * Setting this bit causes the DRAM controller to de-assert the
280 * memory reset pin. This bit cannot be used to assert the memory
282 * [28:28] AssertCke (Assert CKE)
283 * setting this bit causes the DRAM controller to assert the CKE
284 * pins. This bit cannot be used to de-assert the CKE pins
286 * [31:31] EnDramInit (Enable DRAM Initialization)
287 * Setting this bit puts the DRAM controller in a BIOS controlled
288 * DRAM initialization mode. BIOS must clear this bit aster DRAM
289 * initialization is complete.
291 // PCI_ADDR(0, 0x18, 2, 0x7C), 0x60f80000, 0,
294 /* DRAM Bank Address Mapping Register
296 * Specify the memory module size
316 PCI_ADDR(0, 0x18, 2, 0x80), 0xffff0000, 0x00000000,
317 /* DRAM Timing Low Register
319 * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid)
329 * [ 5: 4] Trcd (Ras#-active to Cas# read/write delay)
335 * [ 9: 8] Trp (Row Precharge Time, Precharge-to-Active or Auto-Refresh)
341 * [11:11] Trtp (Read to Precharge Time, read Cas# to precharge time)
342 * 0 = 2 clocks for Burst Length of 32 Bytes
343 * 4 clocks for Burst Length of 64 Bytes
344 * 1 = 3 clocks for Burst Length of 32 Bytes
345 * 5 clocks for Burst Length of 64 Bytes
346 * [15:12] Tras (Minimum Ras# Active Time)
349 * 0010 = 5 bus clocks
351 * 1111 = 18 bus clocks
352 * [19:16] Trc (Row Cycle Time, Ras#-active to Ras#-active or auto
353 * refresh of the same bank)
354 * 0000 = 11 bus clocks
355 * 0010 = 12 bus clocks
357 * 1110 = 25 bus clocks
358 * 1111 = 26 bus clocks
359 * [21:20] Twr (Write Recovery Time, From the last data to precharge,
360 * writes can go back-to-back)
365 * [23:22] Trrd (Active-to-active(Ras#-to-Ras#) Delay of different banks)
370 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A,
371 * BIOS should set it to reduce the power consumption)
372 * Bit F(1207) M2 Package S1g1 Package
374 * 1 N/A MA0_CLK1 MA0_CLK1
377 * 4 MA1_CLK MA1_CLK0 N/A
378 * 5 MA0_CLK MA0_CLK0 MA0_CLK0
380 * 7 N/A MA0_CLK2 MA0_CLK2
382 PCI_ADDR(0, 0x18, 2, 0x88), 0x000004c8, 0xff000002 /* 0x03623125 */ ,
383 /* DRAM Timing High Register
386 * [ 6: 4] TrwtTO (Read-to-Write Turnaround for Data, DQS Contention)
396 * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay,
397 * minium write-to-read delay when both access the same chip select)
402 * [11:10] Twrrd (Write to Read DIMM Termination Turnaround, minimum
403 * write-to-read delay when accessing two different DIMMs)
408 * [13:12] Twrwr (Write to Write Timing)
409 * 00 = 1 bus clocks ( 0 idle cycle on the bus)
410 * 01 = 2 bus clocks ( 1 idle cycle on the bus)
411 * 10 = 3 bus clocks ( 2 idle cycles on the bus)
413 * [15:14] Trdrd ( Read to Read Timing)
414 * 00 = 2 bus clocks ( 1 idle cycle on the bus)
415 * 01 = 3 bus clocks ( 2 idle cycles on the bus)
416 * 10 = 4 bus clocks ( 3 idle cycles on the bus)
417 * 11 = 5 bus clocks ( 4 idel cycles on the bus)
418 * [17:16] Tref (Refresh Rate)
419 * 00 = Undefined behavior
421 * 10 = Refresh interval of 7.8 microseconds
422 * 11 = Refresh interval of 3.9 microseconds
424 * [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0,
425 * based on DRAM density and speed)
426 * 000 = 75 ns (all speeds, 256Mbit)
427 * 001 = 105 ns (all speeds, 512Mbit)
428 * 010 = 127.5 ns (all speeds, 1Gbit)
429 * 011 = 195 ns (all speeds, 2Gbit)
430 * 100 = 327.5 ns (all speeds, 4Gbit)
434 * [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1,
435 * based on DRAM density and speed)
436 * [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2,
437 * based on DRAM density and speed)
438 * [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3,
439 * based on DRAM density and speed)
441 PCI_ADDR(0, 0x18, 2, 0x8c), 0x000c008f, (2 << 16)|(1 << 8),
442 /* DRAM Config Low Register
444 * [ 0: 0] InitDram (Initialize DRAM)
445 * 1 = write 1 cause DRAM controller to execute the DRAM
446 * initialization, when done it read to 0
447 * [ 1: 1] ExitSelfRef ( Exit Self Refresh Command )
448 * 1 = write 1 causes the DRAM controller to bring the DRAMs out
449 * for self refresh mode
451 * [ 5: 4] DramTerm (DRAM Termination)
452 * 00 = On die termination disabled
457 * [ 7: 7] DramDrvWeak ( DRAM Drivers Weak Mode)
458 * 0 = Normal drive strength mode.
459 * 1 = Weak drive strength mode
460 * [ 8: 8] ParEn (Parity Enable)
461 * 1 = Enable address parity computation output, PAR,
462 * and enables the parity error input, ERR
463 * [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable)
464 * 1 = Enable high temperature ( two times normal )
466 * [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes)
469 * [11:11] Width128 ( Width of DRAM interface)
470 * 0 = the controller DRAM interface is 64-bits wide
471 * 1 = the controller DRAM interface is 128-bits wide
472 * [12:12] X4Dimm (DIMM 0 is x4)
473 * [13:13] X4Dimm (DIMM 1 is x4)
474 * [14:14] X4Dimm (DIMM 2 is x4)
475 * [15:15] X4Dimm (DIMM 3 is x4)
477 * 1 = x4 DIMM present
478 * [16:16] UnBuffDimm ( Unbuffered DIMMs)
480 * 1 = Unbuffered DIMMs
482 * [19:19] DimmEccEn ( DIMM ECC Enable )
483 * 1 = ECC checking is being enabled for all DIMMs on the DRAM
484 * controller ( Through F3 0x44[EccEn])
487 PCI_ADDR(0, 0x18, 2, 0x90), 0xfff6004c, 0x00000010,
488 /* DRAM Config High Register
490 * [ 0: 2] MemClkFreq ( Memory Clock Frequency)
496 * [ 3: 3] MemClkFreqVal (Memory Clock Freqency Valid)
497 * 1 = BIOS need to set the bit when setting up MemClkFreq to
499 * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency)
504 * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8
505 * registered DIMMs are present in the system
506 * 0 = DM pins function as data mask pins
507 * 1 = DM pins function as read DQS pins
509 * [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit
510 * is set, the DRAM controller is disabled, and interface in low power
512 * 0 = Enabled (default)
514 * [15:15] PowerDownEn ( Power Down Mode Enable )
515 * 0 = Disabled (default)
517 * [16:16] PowerDown ( Power Down Mode )
518 * 0 = Channel CKE Control
519 * 1 = Chip Select CKE Control
520 * [17:17] FourRankSODimm (Four Rank SO-DIMM)
521 * 1 = this bit is set by BIOS to indicate that a four rank
523 * [18:18] FourRankRDimm (Four Rank Registered DIMM)
524 * 1 = this bit is set by BIOS to indicate that a four rank
525 * registered DIMM is present
527 * [20:20] SlowAccessMode (Slow Access Mode (2T Mode))
528 * 0 = DRAM address and control signals are driven for one
530 * 1 = One additional MEMCLK of setup time is provided on all
531 * DRAM address and control signals except CS, CKE, and ODT;
532 * i.e., these signals are drivern for two MEMCLK cycles
535 * [22:22] BankSwizzleMode ( Bank Swizzle Mode),
536 * 0 = Disabled (default)
539 * [27:24] DcqBypassMax ( DRAM Controller Queue Bypass Maximum)
540 * 0000 = No bypass; the oldest request is never bypassed
541 * 0001 = The oldest request may be bypassed no more than 1 time
543 * 1111 = The oldest request may be bypassed no more than 15\
545 * [31:28] FourActWindow ( Four Bank Activate Window) , not more than
546 * 4 banks in a 8 bank device are activated
547 * 0000 = No tFAW window restriction
548 * 0001 = 8 MEMCLK cycles
549 * 0010 = 9 MEMCLK cycles
551 * 1101 = 20 MEMCLK cycles
554 PCI_ADDR(0, 0x18, 2, 0x94), 0x00a82f00,0x00008000,
555 /* DRAM Delay Line Register
557 * [ 0: 0] MemClrStatus (Memory Clear Status) : Readonly
558 * when set, this bit indicates that the memory clear function
559 * is complete. Only clear by reset. BIOS should not write or
560 * read the DRAM until this bit is set by hardware
561 * [ 1: 1] DisableJitter ( Disable Jitter)
562 * When set the DDR compensation circuit will not change the
563 * values unless the change is more than one step from the
565 * [ 3: 2] RdWrQByp ( Read/Write Queue Bypass Count)
570 * [ 4: 4] Mode64BitMux (Mismatched DIMM Support Enable)
571 * 1 When bit enables support for mismatched DIMMs when using
572 * 128-bit DRAM interface, the Width128 no effect, only for
574 * [ 5: 5] DCC_EN ( Dynamica Idle Cycle Counter Enable)
575 * When set to 1, indicates that each entry in the page tables
576 * dynamically adjusts the idle cycle limit based on page
577 * Conflict/Page Miss (PC/PM) traffic
578 * [ 8: 6] ILD_lmt ( Idle Cycle Limit)
587 * [ 9: 9] DramEnabled ( DRAM Enabled)
588 * When Set, this bit indicates that the DRAM is enabled, this
589 * bit is set by hardware after DRAM initialization or on an exit
590 * from self refresh. The DRAM controller is intialized after the
591 * hardware-controlled initialization process ( initiated by the
592 * F2 0x90[DramInit]) completes or when the BIOS-controlled
593 * initialization process completes (F2 0x7c(EnDramInit] is
594 * written from 1 to 0)
596 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B,
597 * BIOS should set it to reduce the power consumption)
598 * Bit F(1207) M2 Package S1g1 Package
600 * 1 N/A MA0_CLK1 MA0_CLK1
603 * 4 MA1_CLK MA1_CLK0 N/A
604 * 5 MA0_CLK MA0_CLK0 MA0_CLK0
606 * 7 N/A MA0_CLK2 MA0_CLK2
608 PCI_ADDR(0, 0x18, 2, 0xa0), 0x00fffc00, 0xff000000,
610 /* DRAM Scrub Control Register
612 * [ 4: 0] DRAM Scrube Rate
614 * [12: 8] L2 Scrub Rate
616 * [20:16] Dcache Scrub
619 * 00000 = Do not scrub
641 * All Others = Reserved
643 PCI_ADDR(0, 0x18, 3, 0x58), 0xffe0e0e0, 0x00000000,
644 /* DRAM Scrub Address Low Register
646 * [ 0: 0] DRAM Scrubber Redirect Enable
648 * 1 = Scrubber Corrects errors found in normal operation
650 * [31: 6] DRAM Scrub Address 31-6
652 PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000,
653 /* DRAM Scrub Address High Register
655 * [ 7: 0] DRAM Scrubb Address 39-32
658 PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
660 /* for PCI_ADDR(0, 0x18, 2, 0x98) index,
661 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
664 [29: 0] DctOffset (Dram Controller Offset)
665 [30:30] DctAccessWrite (Dram Controller Read/Write Select)
668 [31:31] DctAccessDone (Dram Controller Access Done)
669 0 = Access in progress
670 1 = No access is progress
673 [31: 0] DctOffsetData (Dram Controller Offset Data)
676 - Write the register num to DctOffset with DctAccessWrite = 0
677 - poll the DctAccessDone until it = 1
678 - Read the data from DctOffsetData
680 - Write the data to DctOffsetData
681 - Write register num to DctOffset with DctAccessWrite = 1
682 - poll the DctAccessDone untio it = 1
688 if (!controller_present(ctrl)) {
689 sysinfo->ctrl_present[ctrl->node_id] = 0;
692 sysinfo->ctrl_present[ctrl->node_id] = 1;
694 printk(BIOS_SPEW, "setting up CPU %02x northbridge registers\n", ctrl->node_id);
695 max = ARRAY_SIZE(register_values);
696 for (i = 0; i < max; i += 3) {
700 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
701 where = register_values[i] & 0xff;
702 reg = pci_read_config32(dev, where);
703 reg &= register_values[i+1];
704 reg |= register_values[i+2];
705 pci_write_config32(dev, where, reg);
707 printk(BIOS_SPEW, "done.\n");
711 static int is_dual_channel(const struct mem_controller *ctrl)
714 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
715 return dcl & DCL_Width128;
719 static int is_opteron(const struct mem_controller *ctrl)
721 /* Test to see if I am an Opteron. M2 and S1G1 support dual
722 * channel, too, but only support unbuffered DIMMs so we need a
723 * better test for Opterons.
724 * However, all code uses is_opteron() to find out whether to
725 * use dual channel, so if we really check for opteron here, we
726 * need to fix up all code using this function, too.
730 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
731 return !!(nbcap & NBCAP_128Bit);
735 static int is_registered(const struct mem_controller *ctrl)
737 /* Test to see if we are dealing with registered SDRAM.
738 * If we are not registered we are unbuffered.
739 * This function must be called after spd_handle_unbuffered_dimms.
742 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
743 return !(dcl & DCL_UnBuffDimm);
747 static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
749 /* Calculate the log base 2 size of a DIMM in bits */
756 value = spd_read_byte(device, SPD_ROW_NUM); /* rows */
757 if (value < 0) goto hw_err;
758 if ((value & 0xff) == 0) goto val_err; /* max is 16 ? */
759 sz->per_rank += value & 0xff;
760 sz->rows = value & 0xff;
762 value = spd_read_byte(device, SPD_COL_NUM); /* columns */
763 if (value < 0) goto hw_err;
764 if ((value & 0xff) == 0) goto val_err; /* max is 11 */
765 sz->per_rank += value & 0xff;
766 sz->col = value & 0xff;
768 value = spd_read_byte(device, SPD_BANK_NUM); /* banks */
769 if (value < 0) goto hw_err;
770 if ((value & 0xff) == 0) goto val_err;
771 sz->bank = log2(value & 0xff); // convert 4 to 2, and 8 to 3
772 sz->per_rank += sz->bank;
774 /* Get the module data width and convert it to a power of two */
775 value = spd_read_byte(device, SPD_DATA_WIDTH);
776 if (value < 0) goto hw_err;
778 if ((value != 72) && (value != 64)) goto val_err;
779 sz->per_rank += log2(value) - 3; //64 bit So another 3 lines
781 /* How many ranks? */
782 /* number of physical banks */
783 value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK);
784 if (value < 0) goto hw_err;
785 /* value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT; */
786 value &= SPD_MOD_ATTRIB_RANK_NUM_MASK;
787 value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4
789 rank == 1 only one rank or say one side
790 rank == 2 two side , and two ranks
791 rank == 4 two side , and four ranks total
792 Some one side two ranks, because of stacked
794 if ((value != 1) && (value != 2) && (value != 4 )) {
799 /* verify if per_rank is equal byte 31
800 it has the DIMM size as a multiple of 128MB.
802 value = spd_read_byte(device, SPD_RANK_SIZE);
803 if (value < 0) goto hw_err;
806 if (value <=4 ) value += 8; // add back to 1G to high
807 value += (27-5); // make 128MB to the real lines
808 if ( value != (sz->per_rank)) {
809 printk(BIOS_ERR, "Bad RANK Size --\n");
816 die("Bad SPD value\n");
817 /* If an hw_error occurs report that I have no memory */
829 static void set_dimm_size(const struct mem_controller *ctrl,
830 struct dimm_size *sz, unsigned index,
831 struct mem_info *meminfo)
833 uint32_t base0, base1;
835 /* For each base register.
836 * Place the dimm size in 32 MB quantities in the bits 31 - 21.
837 * The initialize dimm size is in bits.
838 * Set the base enable bit0.
843 /* Make certain side1 of the dimm is at least 128MB */
844 if (sz->per_rank >= 27) {
845 base0 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
848 /* Make certain side2 of the dimm is at least 128MB */
849 if (sz->rank > 1) { // 2 ranks or 4 ranks
850 base1 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
853 /* Double the size if we are using dual channel memory */
854 if (meminfo->is_Width128) {
855 base0 = (base0 << 1) | (base0 & 1);
856 base1 = (base1 << 1) | (base1 & 1);
859 /* Clear the reserved bits */
860 base0 &= ~0xe007fffe;
861 base1 &= ~0xe007fffe;
863 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
864 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
865 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
867 /* Set the appropriate DIMM base address register */
868 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0);
869 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1);
870 #if QRANK_DIMM_SUPPORT == 1
872 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
873 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
878 /* Enable the memory clocks for this DIMM by Clear the MemClkDis bit*/
882 #if CONFIG_CPU_SOCKET_TYPE == 0x10 /* L1 */
883 ClkDis0 = DTL_MemClkDis0;
884 #elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM2 */
885 ClkDis0 = DTL_MemClkDis0_AM2;
886 #elif CONFIG_CPU_SOCKET_TYPE == 0x12 /* S1G1 */
887 ClkDis0 = DTL_MemClkDis0_S1g1;
890 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
891 dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
892 dword &= ~(ClkDis0 >> index);
893 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
896 dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
897 dword &= ~(ClkDis0 >> index);
898 #if QRANK_DIMM_SUPPORT == 1
900 dword &= ~(ClkDis0 >> (index+2));
903 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dword);
905 if (meminfo->is_Width128) { // ChannelA+B
906 dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
907 dword &= ~(ClkDis0 >> index);
908 #if QRANK_DIMM_SUPPORT == 1
910 dword &= ~(ClkDis0 >> (index+2));
913 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
920 /* row col bank for 64 bit
936 static void set_dimm_cs_map(const struct mem_controller *ctrl,
937 struct dimm_size *sz, unsigned index,
938 struct mem_info *meminfo)
940 static const uint8_t cs_map_aaa[24] = {
941 /* (bank=2, row=13, col=9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */
956 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
959 map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
960 map &= ~(0xf << (index * 4));
961 #if QRANK_DIMM_SUPPORT == 1
963 map &= ~(0xf << ( (index + 2) * 4));
967 /* Make certain side1 of the dimm is at least 128MB */
968 if (sz->per_rank >= 27) {
970 temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ];
971 map |= temp_map << (index*4);
972 #if QRANK_DIMM_SUPPORT == 1
974 map |= temp_map << ( (index + 2) * 4);
979 pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
984 static long spd_set_ram_size(const struct mem_controller *ctrl,
985 struct mem_info *meminfo)
989 for (i = 0; i < DIMM_SOCKETS; i++) {
990 struct dimm_size *sz = &(meminfo->sz[i]);
991 u32 spd_device = ctrl->channel0[i];
993 if (!(meminfo->dimm_mask & (1 << i))) {
994 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
995 spd_device = ctrl->channel1[i];
1001 spd_get_dimm_size(spd_device, sz);
1002 if (sz->per_rank == 0) {
1003 return -1; /* Report SPD error */
1005 set_dimm_size(ctrl, sz, i, meminfo);
1006 set_dimm_cs_map(ctrl, sz, i, meminfo);
1008 return meminfo->dimm_mask;
1011 static void route_dram_accesses(const struct mem_controller *ctrl,
1012 unsigned long base_k, unsigned long limit_k)
1014 /* Route the addresses to the controller node */
1019 unsigned limit_reg, base_reg;
1022 node_id = ctrl->node_id;
1023 index = (node_id << 3);
1024 limit = (limit_k << 2);
1025 limit &= 0xffff0000;
1026 limit -= 0x00010000;
1027 limit |= ( 0 << 8) | (node_id << 0);
1028 base = (base_k << 2);
1030 base |= (0 << 8) | (1<<1) | (1<<0);
1032 limit_reg = 0x44 + index;
1033 base_reg = 0x40 + index;
1034 for (device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1);
1035 device += PCI_DEV(0, 1, 0)) {
1036 pci_write_config32(device, limit_reg, limit);
1037 pci_write_config32(device, base_reg, base);
1041 static void set_top_mem(unsigned tom_k, unsigned hole_startk)
1043 /* Error if I don't have memory */
1048 /* Report the amount of memory. */
1049 printk(BIOS_DEBUG, "RAM end at 0x%08x kB\n", tom_k);
1051 /* Now set top of memory */
1053 if (tom_k > (4*1024*1024)) {
1054 printk_raminit("Handling memory mapped above 4 GB\n");
1055 printk_raminit("Upper RAM end at 0x%08x kB\n", tom_k);
1056 msr.lo = (tom_k & 0x003fffff) << 10;
1057 msr.hi = (tom_k & 0xffc00000) >> 22;
1058 wrmsr(TOP_MEM2, msr);
1059 printk_raminit("Correcting memory amount mapped below 4 GB\n");
1062 /* Leave a 64M hole between TOP_MEM and TOP_MEM2
1063 * so I can see my rom chip and other I/O devices.
1065 if (tom_k >= 0x003f0000) {
1066 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
1067 if (hole_startk != 0) {
1068 tom_k = hole_startk;
1072 printk_raminit("Adjusting lower RAM end\n");
1074 printk_raminit("Lower RAM end at 0x%08x kB\n", tom_k);
1075 msr.lo = (tom_k & 0x003fffff) << 10;
1076 msr.hi = (tom_k & 0xffc00000) >> 22;
1077 wrmsr(TOP_MEM, msr);
1080 static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, int is_Width128)
1084 static const uint8_t csbase_low_f0_shift[] = {
1085 /* 128MB */ (14 - (13-5)),
1086 /* 256MB */ (15 - (13-5)),
1087 /* 512MB */ (15 - (13-5)),
1088 /* 512MB */ (16 - (13-5)),
1089 /* 512MB */ (16 - (13-5)),
1090 /* 1GB */ (16 - (13-5)),
1091 /* 1GB */ (16 - (13-5)),
1092 /* 2GB */ (16 - (13-5)),
1093 /* 2GB */ (17 - (13-5)),
1094 /* 4GB */ (17 - (13-5)),
1095 /* 4GB */ (16 - (13-5)),
1096 /* 8GB */ (17 - (13-5)),
1099 /* cs_base_high is not changed */
1101 uint32_t csbase_inc;
1102 int chip_selects, index;
1104 unsigned common_size;
1105 unsigned common_cs_mode;
1106 uint32_t csbase, csmask;
1108 /* See if all of the memory chip selects are the same size
1109 * and if so count them.
1113 common_cs_mode = 0xff;
1114 for (index = 0; index < 8; index++) {
1119 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1121 /* Is it enabled? */
1126 size = (value >> 19) & 0x3ff;
1127 if (common_size == 0) {
1130 /* The size differed fail */
1131 if (common_size != size) {
1135 value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
1136 cs_mode =( value >> ((index>>1)*4)) & 0xf;
1137 if (common_cs_mode == 0xff) {
1138 common_cs_mode = cs_mode;
1140 /* The cs_mode differed fail */
1141 if (common_cs_mode != cs_mode) {
1146 /* Chip selects can only be interleaved when there is
1147 * more than one and their is a power of two of them.
1149 bits = log2(chip_selects);
1150 if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) {
1151 //chip_selects max = 8
1155 /* Find the bits of csbase that we need to interleave on */
1156 csbase_inc = 1 << (csbase_low_f0_shift[common_cs_mode]);
1161 /* Compute the initial values for csbase and csbask.
1162 * In csbase just set the enable bit and the base to zero.
1163 * In csmask set the mask bits for the size and page level interleave.
1166 csmask = (((common_size << bits) - 1) << 19);
1167 csmask |= 0x3fe0 & ~((csbase_inc << bits) - csbase_inc);
1168 for (index = 0; index < 8; index++) {
1171 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1172 /* Is it enabled? */
1176 pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
1177 if ((index & 1) == 0) { //only have 4 CSMASK
1178 pci_write_config32(ctrl->f2, DRAM_CSMASK + ((index>>1) << 2), csmask);
1180 csbase += csbase_inc;
1183 printk(BIOS_DEBUG, "Interleaved\n");
1185 /* Return the memory size in K */
1186 return common_size << ((27-10) + bits);
1189 static unsigned long order_chip_selects(const struct mem_controller *ctrl)
1193 /* Remember which registers we have used in the high 8 bits of tom */
1196 /* Find the largest remaining canidate */
1197 unsigned index, canidate;
1198 uint32_t csbase, csmask;
1202 for (index = 0; index < 8; index++) {
1204 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1206 /* Is it enabled? */
1211 /* Is it greater? */
1212 if (value <= csbase) {
1216 /* Has it already been selected */
1217 if (tom & (1 << (index + 24))) {
1220 /* I have a new canidate */
1225 /* See if I have found a new canidate */
1230 /* Remember the dimm size */
1231 size = csbase >> 19;
1233 /* Remember I have used this register */
1234 tom |= (1 << (canidate + 24));
1236 /* Recompute the cs base register value */
1237 csbase = (tom << 19) | 1;
1239 /* Increment the top of memory */
1242 /* Compute the memory mask */
1243 csmask = ((size -1) << 19);
1244 csmask |= 0x3fe0; /* For now don't optimize */
1246 /* Write the new base register */
1247 pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
1248 /* Write the new mask register */
1249 if ((canidate & 1) == 0) { //only have 4 CSMASK
1250 pci_write_config32(ctrl->f2, DRAM_CSMASK + ((canidate >> 1) << 2), csmask);
1254 /* Return the memory size in K */
1255 return (tom & ~0xff000000) << (27-10);
1258 static unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
1262 /* Find the last memory address used */
1264 for (node_id = 0; node_id < max_node_id; node_id++) {
1265 uint32_t limit, base;
1267 index = node_id << 3;
1268 base = pci_read_config32(ctrl->f1, 0x40 + index);
1269 /* Only look at the limit if the base is enabled */
1270 if ((base & 3) == 3) {
1271 limit = pci_read_config32(ctrl->f1, 0x44 + index);
1272 end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
1278 static void order_dimms(const struct mem_controller *ctrl,
1279 struct mem_info *meminfo)
1281 unsigned long tom_k, base_k;
1283 if (read_option(CMOS_VSTART_interleave_chip_selects,
1284 CMOS_VLEN_interleave_chip_selects, 1) != 0) {
1285 tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
1287 printk(BIOS_DEBUG, "Interleaving disabled\n");
1292 tom_k = order_chip_selects(ctrl);
1295 /* Compute the memory base address */
1296 base_k = memory_end_k(ctrl, ctrl->node_id);
1298 route_dram_accesses(ctrl, base_k, tom_k);
1299 set_top_mem(tom_k, 0);
1302 static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
1303 struct mem_info *meminfo)
1305 printk(BIOS_DEBUG, "disabling dimm %02x\n", index);
1306 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
1307 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
1308 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
1310 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0);
1311 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0);
1312 #if QRANK_DIMM_SUPPORT == 1
1313 if (meminfo->sz[index].rank == 4) {
1314 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
1315 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
1320 meminfo->dimm_mask &= ~(1 << index);
1321 return meminfo->dimm_mask;
1324 static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
1325 struct mem_info *meminfo)
1328 uint32_t registered;
1331 for (i = 0; (i < DIMM_SOCKETS); i++) {
1333 u32 spd_device = ctrl->channel0[i];
1334 if (!(meminfo->dimm_mask & (1 << i))) {
1335 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1336 spd_device = ctrl->channel1[i];
1341 value = spd_read_byte(spd_device, SPD_DIMM_TYPE);
1346 /* Registered dimm ? */
1348 if ((value == SPD_DIMM_TYPE_RDIMM) || (value == SPD_DIMM_TYPE_mRDIMM)) {
1349 //check SPD_MOD_ATTRIB to verify it is SPD_MOD_ATTRIB_REGADC (0x11)?
1350 registered |= (1<<i);
1354 if (is_opteron(ctrl)) {
1356 if ( registered != (meminfo->dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) {
1357 meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffed dimm
1358 // die("Mixed buffered and registered dimms not supported");
1360 //By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM
1362 die("Unbuffered Dimms not supported on Opteron");
1368 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1369 dcl &= ~DCL_UnBuffDimm;
1370 meminfo->is_registered = 1;
1372 dcl |= DCL_UnBuffDimm;
1373 meminfo->is_registered = 0;
1375 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1377 if (meminfo->is_registered) {
1378 printk(BIOS_SPEW, "Registered\n");
1380 printk(BIOS_SPEW, "Unbuffered\n");
1382 return meminfo->dimm_mask;
1385 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
1390 for (i = 0; i < DIMM_SOCKETS; i++) {
1393 device = ctrl->channel0[i];
1394 printk_raminit("DIMM socket %i, channel 0 SPD device is 0x%02x\n", i, device);
1396 byte = spd_read_byte(ctrl->channel0[i], SPD_MEM_TYPE); /* Type */
1397 if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
1398 dimm_mask |= (1 << i);
1401 device = ctrl->channel1[i];
1402 printk_raminit("DIMM socket %i, channel 1 SPD device is 0x%02x\n", i, device);
1404 byte = spd_read_byte(ctrl->channel1[i], SPD_MEM_TYPE);
1405 if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
1406 dimm_mask |= (1 << (i + DIMM_SOCKETS));
1413 static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_info *meminfo)
1417 /* SPD addresses to verify are identical */
1418 static const uint8_t addresses[] = {
1419 2, /* Type should be DDR2 SDRAM */
1420 3, /* *Row addresses */
1421 4, /* *Column addresses */
1422 5, /* *Number of DIMM Ranks */
1423 6, /* *Module Data Width*/
1424 11, /* *DIMM Conf Type */
1425 13, /* *Pri SDRAM Width */
1426 17, /* *Logical Banks */
1427 20, /* *DIMM Type Info */
1428 21, /* *SDRAM Module Attributes */
1429 27, /* *tRP Row precharge time */
1430 28, /* *Minimum Row Active to Row Active Delay (tRRD) */
1431 29, /* *tRCD RAS to CAS */
1432 30, /* *tRAS Activate to Precharge */
1433 36, /* *Write recovery time (tWR) */
1434 37, /* *Internal write to read command delay (tRDP) */
1435 38, /* *Internal read to precharge command delay (tRTP) */
1436 40, /* *Extension of Byte 41 tRC and Byte 42 tRFC */
1437 41, /* *Minimum Active to Active/Auto Refresh Time(Trc) */
1438 42, /* *Minimum Auto Refresh Command Time(Trfc) */
1439 /* The SPD addresses 18, 9, 23, 26 need special treatment like
1440 * in spd_set_memclk. Right now they cause many false negatives.
1441 * Keep them at the end to see other mismatches (if any).
1443 18, /* *Supported CAS Latencies */
1444 9, /* *Cycle time at highest CAS Latency CL=X */
1445 23, /* *Cycle time at CAS Latency (CLX - 1) */
1446 26, /* *Cycle time at CAS Latency (CLX - 2) */
1451 /* S1G1 and AM2 sockets are Mod64BitMux capable. */
1452 #if CONFIG_CPU_SOCKET_TYPE == 0x11 || CONFIG_CPU_SOCKET_TYPE == 0x12
1458 /* If the dimms are not in pairs do not do dual channels */
1459 if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
1460 ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1461 goto single_channel;
1463 /* If the cpu is not capable of doing dual channels don't do dual channels */
1464 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1465 if (!(nbcap & NBCAP_128Bit)) {
1466 goto single_channel;
1468 for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
1469 unsigned device0, device1;
1472 /* If I don't have a dimm skip this one */
1473 if (!(meminfo->dimm_mask & (1 << i))) {
1476 device0 = ctrl->channel0[i];
1477 device1 = ctrl->channel1[i];
1478 /* Abort if the chips don't support a common CAS latency. */
1479 common_cl = spd_read_byte(device0, 18) & spd_read_byte(device1, 18);
1481 printk(BIOS_DEBUG, "No common CAS latency supported\n");
1482 goto single_channel;
1484 printk_raminit("Common CAS latency bitfield: 0x%02x\n", common_cl);
1486 for (j = 0; j < ARRAY_SIZE(addresses); j++) {
1488 addr = addresses[j];
1489 value0 = spd_read_byte(device0, addr);
1493 value1 = spd_read_byte(device1, addr);
1497 if (value0 != value1) {
1498 printk_raminit("SPD values differ between channel 0/1 for byte %i\n", addr);
1499 goto single_channel;
1503 printk(BIOS_SPEW, "Enabling dual channel memory\n");
1504 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1505 dcl &= ~DCL_BurstLength32; /* 32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses
1506 32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode */
1507 dcl |= DCL_Width128;
1508 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1509 meminfo->is_Width128 = 1;
1510 return meminfo->dimm_mask;
1513 meminfo->is_Width128 = 0;
1514 meminfo->is_64MuxMode = 0;
1517 if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
1518 ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1519 if (((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1520 /* mux capable and single dimm in channelB */
1522 printk(BIOS_SPEW, "Enable 64MuxMode & BurstLength32\n");
1523 dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
1524 dcm |= DCM_Mode64BitMux;
1525 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
1526 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1527 //dcl |= DCL_BurstLength32; /* 32byte mode for channelB only */
1528 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1529 meminfo->is_64MuxMode = 1;
1531 meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
1534 } else { /* unmatched dual dimms ? */
1535 /* unmatched dual dimms not supported by meminit code. Use single channelA dimm. */
1536 meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
1537 printk(BIOS_SPEW, "Unmatched dual dimms. Use single channelA dimm.\n");
1539 return meminfo->dimm_mask;
1543 uint16_t cycle_time;
1544 uint8_t divisor; /* In 1/40 ns increments */
1549 uint8_t DcqByPassMax;
1550 uint32_t dch_memclk;
1554 static const struct mem_param speed[] = {
1557 .cycle_time = 0x500,
1558 .divisor = 200, // how many 1/40ns per clock
1559 .dch_memclk = DCH_MemClkFreq_200MHz, //0
1569 .cycle_time = 0x375,
1570 .divisor = 150, //????
1571 .dch_memclk = DCH_MemClkFreq_266MHz, //1
1580 .cycle_time = 0x300,
1582 .dch_memclk = DCH_MemClkFreq_333MHz, //2
1592 .cycle_time = 0x250,
1594 .dch_memclk = DCH_MemClkFreq_400MHz,//3
1602 .cycle_time = 0x000,
1606 static const struct mem_param *get_mem_param(unsigned min_cycle_time)
1609 const struct mem_param *param;
1610 for (param = &speed[0]; param->cycle_time ; param++) {
1611 if (min_cycle_time > (param+1)->cycle_time) {
1615 if (!param->cycle_time) {
1616 die("min_cycle_time to low");
1618 printk(BIOS_SPEW, "%s\n", param->name);
1622 static uint8_t get_exact_divisor(int i, uint8_t divisor)
1624 //input divisor could be 200(200), 150(266), 120(333), 100 (400)
1625 static const uint8_t dv_a[] = {
1626 /* 200 266 333 400 */
1627 /*4 */ 250, 250, 250, 250,
1628 /*5 */ 200, 200, 200, 100,
1629 /*6 */ 200, 166, 166, 100,
1630 /*7 */ 200, 171, 142, 100,
1632 /*8 */ 200, 150, 125, 100,
1633 /*9 */ 200, 156, 133, 100,
1634 /*10*/ 200, 160, 120, 100,
1635 /*11*/ 200, 163, 127, 100,
1637 /*12*/ 200, 150, 133, 100,
1638 /*13*/ 200, 153, 123, 100,
1639 /*14*/ 200, 157, 128, 100,
1640 /*15*/ 200, 160, 120, 100,
1647 /* Check for FID control support */
1648 struct cpuid_result cpuid1;
1649 cpuid1 = cpuid(0x80000007);
1650 if( cpuid1.edx & 0x02 ) {
1651 /* Use current FID */
1653 msr = rdmsr(0xc0010042);
1654 fid_cur = msr.lo & 0x3f;
1658 /* Use startup FID */
1660 msr = rdmsr(0xc0010015);
1661 fid_start = (msr.lo & (0x3f << 24));
1663 index = fid_start>>25;
1666 if (index>12) return divisor;
1668 if (i>3) return divisor;
1670 return dv_a[index * 4+i];
1675 struct spd_set_memclk_result {
1676 const struct mem_param *param;
1681 static unsigned convert_to_linear(unsigned value)
1683 static const unsigned fraction[] = { 0x25, 0x33, 0x66, 0x75 };
1686 /* We need to convert value to more readable */
1687 if ((value & 0xf) < 10) { //no .25, .33, .66, .75
1690 valuex = ((value & 0xf0) << 4) | fraction [(value & 0xf)-10];
1696 static const uint8_t latency_indicies[] = { 25, 23, 9 };
1698 static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time)
1700 int new_cycle_time, new_latency;
1705 /* First find the supported CAS latencies
1706 * Byte 18 for DDR SDRAM is interpreted:
1707 * bit 3 == CAS Latency = 3
1708 * bit 4 == CAS Latency = 4
1709 * bit 5 == CAS Latency = 5
1710 * bit 6 == CAS Latency = 6
1712 new_cycle_time = 0x500;
1715 latencies = spd_read_byte(spd_device, SPD_CAS_LAT);
1719 printk_raminit("\tlatencies: %08x\n", latencies);
1720 /* Compute the lowest cas latency which can be expressed in this
1721 * particular SPD EEPROM. You can store at most settings for 3
1722 * contiguous CAS latencies, so by taking the highest CAS
1723 * latency maked as supported in the SPD and subtracting 2 you
1724 * get the lowest expressable CAS latency. That latency is not
1725 * necessarily supported, but a (maybe invalid) entry exists
1728 latency = log2(latencies) - 2;
1730 /* Loop through and find a fast clock with a low latency */
1731 for (index = 0; index < 3; index++, latency++) {
1733 if ((latency < 3) || (latency > 6) ||
1734 (!(latencies & (1 << latency)))) {
1737 value = spd_read_byte(spd_device, latency_indicies[index]);
1742 printk_raminit("\tindex: %08x\n", index);
1743 printk_raminit("\t\tlatency: %08x\n", latency);
1744 printk_raminit("\t\tvalue1: %08x\n", value);
1746 value = convert_to_linear(value);
1748 printk_raminit("\t\tvalue2: %08x\n", value);
1750 /* Only increase the latency if we decrease the clock */
1751 if (value >= *min_cycle_time ) {
1752 if (value < new_cycle_time) {
1753 new_cycle_time = value;
1754 new_latency = latency;
1755 } else if (value == new_cycle_time) {
1756 if (new_latency > latency) {
1757 new_latency = latency;
1761 printk_raminit("\t\tnew_cycle_time: %08x\n", new_cycle_time);
1762 printk_raminit("\t\tnew_latency: %08x\n", new_latency);
1766 if (new_latency > 6){
1770 /* Does min_latency need to be increased? */
1771 if (new_cycle_time > *min_cycle_time) {
1772 *min_cycle_time = new_cycle_time;
1775 /* Does min_cycle_time need to be increased? */
1776 if (new_latency > *min_latency) {
1777 *min_latency = new_latency;
1780 printk_raminit("2 min_cycle_time: %08x\n", *min_cycle_time);
1781 printk_raminit("2 min_latency: %08x\n", *min_latency);
1786 static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, struct mem_info *meminfo)
1788 /* Compute the minimum cycle time for these dimms */
1789 struct spd_set_memclk_result result;
1790 unsigned min_cycle_time, min_latency, bios_cycle_time;
1794 static const uint16_t min_cycle_times[] = { // use full speed to compare
1795 [NBCAP_MEMCLK_NOLIMIT] = 0x250, /*2.5ns */
1796 [NBCAP_MEMCLK_333MHZ] = 0x300, /* 3.0ns */
1797 [NBCAP_MEMCLK_266MHZ] = 0x375, /* 3.75ns */
1798 [NBCAP_MEMCLK_200MHZ] = 0x500, /* 5.0s */
1802 value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1803 min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
1804 bios_cycle_time = min_cycle_times[
1805 read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
1806 if (bios_cycle_time > min_cycle_time) {
1807 min_cycle_time = bios_cycle_time;
1811 printk_raminit("1 min_cycle_time: %08x\n", min_cycle_time);
1813 /* Compute the least latency with the fastest clock supported
1814 * by both the memory controller and the dimms.
1816 for (i = 0; i < DIMM_SOCKETS; i++) {
1819 printk_raminit("1.1 dimm_mask: %08x\n", meminfo->dimm_mask);
1820 printk_raminit("i: %08x\n",i);
1822 if (meminfo->dimm_mask & (1 << i)) {
1823 spd_device = ctrl->channel0[i];
1824 printk_raminit("Channel 0 settings:\n");
1826 switch (find_optimum_spd_latency(spd_device, &min_latency, &min_cycle_time)) {
1834 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) {
1835 spd_device = ctrl->channel1[i];
1836 printk_raminit("Channel 1 settings:\n");
1838 switch (find_optimum_spd_latency(spd_device, &min_latency, &min_cycle_time)) {
1848 /* Make a second pass through the dimms and disable
1849 * any that cannot support the selected memclk and cas latency.
1852 printk_raminit("3 min_cycle_time: %08x\n", min_cycle_time);
1853 printk_raminit("3 min_latency: %08x\n", min_latency);
1855 for (i = 0; (i < DIMM_SOCKETS); i++) {
1860 u32 spd_device = ctrl->channel0[i];
1862 if (!(meminfo->dimm_mask & (1 << i))) {
1863 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1864 spd_device = ctrl->channel1[i];
1870 latencies = spd_read_byte(spd_device, SPD_CAS_LAT);
1871 if (latencies < 0) goto hw_error;
1872 if (latencies == 0) {
1876 /* Compute the lowest cas latency supported */
1877 latency = log2(latencies) -2;
1879 /* Walk through searching for the selected latency */
1880 for (index = 0; index < 3; index++, latency++) {
1881 if (!(latencies & (1 << latency))) {
1884 if (latency == min_latency)
1887 /* If I can't find the latency or my index is bad error */
1888 if ((latency != min_latency) || (index >= 3)) {
1892 /* Read the min_cycle_time for this latency */
1893 val = spd_read_byte(spd_device, latency_indicies[index]);
1894 if (val < 0) goto hw_error;
1896 val = convert_to_linear(val);
1897 /* All is good if the selected clock speed
1898 * is what I need or slower.
1900 if (val <= min_cycle_time) {
1903 /* Otherwise I have an error, disable the dimm */
1905 meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo);
1908 printk_raminit("4 min_cycle_time: %08x\n", min_cycle_time);
1910 /* Now that I know the minimum cycle time lookup the memory parameters */
1911 result.param = get_mem_param(min_cycle_time);
1913 /* Update DRAM Config High with our selected memory speed */
1914 value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
1915 value &= ~(DCH_MemClkFreq_MASK << DCH_MemClkFreq_SHIFT);
1917 value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT;
1918 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
1920 printk(BIOS_DEBUG, "%s\n", result.param->name);
1922 /* Update DRAM Timing Low with our selected cas latency */
1923 value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1924 value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
1925 value |= (min_latency - DTL_TCL_BASE) << DTL_TCL_SHIFT;
1926 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
1928 result.dimm_mask = meminfo->dimm_mask;
1931 result.param = (const struct mem_param *)0;
1932 result.dimm_mask = -1;
1936 static unsigned convert_to_1_4(unsigned value)
1938 static const uint8_t fraction[] = { 0, 1, 2, 2, 3, 3, 0 };
1941 /* We need to convert value to more readable */
1942 valuex = fraction [value & 0x7];
1946 static int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param)
1951 value = spd_read_byte(spd_device, SPD_TRC);
1954 printk_raminit("update_dimm_Trc: tRC (41) = %08x\n", value);
1956 value2 = spd_read_byte(spd_device, SPD_TRC -1);
1958 value += convert_to_1_4(value2>>4);
1961 printk_raminit("update_dimm_Trc: tRC final value = %i\n", value);
1963 clocks = (value + param->divisor - 1)/param->divisor;
1964 printk_raminit("update_dimm_Trc: clocks = %i\n", clocks);
1966 if (clocks < DTL_TRC_MIN) {
1967 // We might want to die here instead or (at least|better) disable this bank.
1968 printk(BIOS_NOTICE, "update_dimm_Trc: Can't refresh fast enough, "
1969 "want %i clocks, minimum is %i clocks.\n", clocks, DTL_TRC_MIN);
1970 clocks = DTL_TRC_MIN;
1975 static int update_dimm_Trc(const struct mem_controller *ctrl,
1976 const struct mem_param *param,
1977 int i, long dimm_mask)
1979 int clocks, old_clocks;
1981 u32 spd_device = ctrl->channel0[i];
1983 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
1984 spd_device = ctrl->channel1[i];
1987 clocks = get_dimm_Trc_clocks(spd_device, param);
1990 if (clocks > DTL_TRC_MAX) {
1993 printk_raminit("update_dimm_Trc: clocks after adjustment = %i\n", clocks);
1995 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1996 old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
1997 if (old_clocks >= clocks) { //?? someone did it
1998 // clocks = old_clocks;
2001 dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
2002 dtl |= ((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
2003 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
2007 static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i, struct mem_info *meminfo)
2009 unsigned clocks, old_clocks;
2013 u32 spd_device = ctrl->channel0[i];
2015 if (!(meminfo->dimm_mask & (1 << i)) && (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2016 spd_device = ctrl->channel1[i];
2017 ch_b = 2; /* offset to channelB trfc setting */
2020 //get the cs_size --> logic dimm size
2021 value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
2026 value = 6 - log2(value); //4-->4, 8-->3, 16-->2
2028 clocks = meminfo->sz[i].per_rank - 27 + 2 - value;
2030 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
2032 old_clocks = ((dth >> (DTH_TRFC0_SHIFT + ((i + ch_b) * 3))) & DTH_TRFC_MASK);
2034 if (old_clocks >= clocks) { // some one did it?
2037 dth &= ~(DTH_TRFC_MASK << (DTH_TRFC0_SHIFT + ((i + ch_b) * 3)));
2038 dth |= clocks << (DTH_TRFC0_SHIFT + ((i + ch_b) * 3));
2039 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2043 static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask,
2045 unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX )
2047 unsigned clocks, old_clocks;
2050 u32 spd_device = ctrl->channel0[i];
2052 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2053 spd_device = ctrl->channel1[i];
2056 value = spd_read_byte(spd_device, SPD_TT); //already in 1/4 ns
2057 if (value < 0) return -1;
2059 clocks = (value + param->divisor -1)/param->divisor;
2060 if (clocks < TT_MIN) {
2064 if (clocks > TT_MAX) {
2065 printk(BIOS_INFO, "warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
2069 dtl = pci_read_config32(ctrl->f2, TT_REG);
2071 old_clocks = ((dtl >> TT_SHIFT) & TT_MASK) + TT_BASE;
2072 if (old_clocks >= clocks) { //some one did it?
2073 // clocks = old_clocks;
2076 dtl &= ~(TT_MASK << TT_SHIFT);
2077 dtl |= ((clocks - TT_BASE) << TT_SHIFT);
2078 pci_write_config32(ctrl->f2, TT_REG, dtl);
2082 static int update_dimm_Trcd(const struct mem_controller *ctrl,
2083 const struct mem_param *param, int i, long dimm_mask)
2085 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRCD, DTL_TRCD_SHIFT, DTL_TRCD_MASK, DTL_TRCD_BASE, DTL_TRCD_MIN, DTL_TRCD_MAX);
2088 static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2090 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRRD, DTL_TRRD_SHIFT, DTL_TRRD_MASK, DTL_TRRD_BASE, DTL_TRRD_MIN, DTL_TRRD_MAX);
2093 static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2095 unsigned clocks, old_clocks;
2098 u32 spd_device = ctrl->channel0[i];
2100 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2101 spd_device = ctrl->channel1[i];
2104 value = spd_read_byte(spd_device, SPD_TRAS); //in 1 ns
2105 if (value < 0) return -1;
2106 printk_raminit("update_dimm_Tras: 0 value= %08x\n", value);
2108 value <<= 2; //convert it to in 1/4ns
2111 printk_raminit("update_dimm_Tras: 1 value= %08x\n", value);
2113 clocks = (value + param->divisor - 1)/param->divisor;
2114 printk_raminit("update_dimm_Tras: divisor= %08x\n", param->divisor);
2115 printk_raminit("update_dimm_Tras: clocks= %08x\n", clocks);
2116 if (clocks < DTL_TRAS_MIN) {
2117 clocks = DTL_TRAS_MIN;
2119 if (clocks > DTL_TRAS_MAX) {
2122 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
2123 old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
2124 if (old_clocks >= clocks) { // someone did it?
2127 dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
2128 dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
2129 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
2133 static int update_dimm_Trp(const struct mem_controller *ctrl,
2134 const struct mem_param *param, int i, long dimm_mask)
2136 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRP, DTL_TRP_SHIFT, DTL_TRP_MASK, DTL_TRP_BASE, DTL_TRP_MIN, DTL_TRP_MAX);
2140 static int update_dimm_Trtp(const struct mem_controller *ctrl,
2141 const struct mem_param *param, int i, struct mem_info *meminfo)
2143 /* need to figure if it is 32 byte burst or 64 bytes burst */
2145 if (!meminfo->is_Width128) {
2147 dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2148 if ((dword & DCL_BurstLength32)) offset = 0;
2150 return update_dimm_TT_1_4(ctrl, param, i, meminfo->dimm_mask, DRAM_TIMING_LOW, SPD_TRTP, DTL_TRTP_SHIFT, DTL_TRTP_MASK, DTL_TRTP_BASE+offset, DTL_TRTP_MIN+offset, DTL_TRTP_MAX+offset);
2154 static int update_dimm_Twr(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2156 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TWR, DTL_TWR_SHIFT, DTL_TWR_MASK, DTL_TWR_BASE, DTL_TWR_MIN, DTL_TWR_MAX);
2160 static int update_dimm_Tref(const struct mem_controller *ctrl,
2161 const struct mem_param *param, int i, long dimm_mask)
2163 uint32_t dth, dth_old;
2165 u32 spd_device = ctrl->channel0[i];
2167 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2168 spd_device = ctrl->channel1[i];
2171 value = spd_read_byte(spd_device, SPD_TREF); // 0: 15.625us, 1: 3.9us 2: 7.8 us....
2172 if (value < 0) return -1;
2180 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
2183 dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
2184 dth |= (value << DTH_TREF_SHIFT);
2185 if (dth_old != dth) {
2186 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2191 static void set_4RankRDimm(const struct mem_controller *ctrl,
2192 const struct mem_param *param, struct mem_info *meminfo)
2194 #if QRANK_DIMM_SUPPORT == 1
2197 long dimm_mask = meminfo->dimm_mask;
2200 if (!(meminfo->is_registered)) return;
2204 for (i = 0; i < DIMM_SOCKETS; i++) {
2205 if (!(dimm_mask & (1 << i))) {
2209 if (meminfo->sz[i].rank == 4) {
2217 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2218 dch |= DCH_FourRankRDimm;
2219 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2224 static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
2225 struct mem_info *meminfo)
2231 uint32_t mask_single_rank;
2232 uint32_t mask_page_1k;
2234 #if QRANK_DIMM_SUPPORT == 1
2238 long dimm_mask = meminfo->dimm_mask;
2243 mask_single_rank = 0;
2246 for (i = 0; i < DIMM_SOCKETS; i++) {
2247 u32 spd_device = ctrl->channel0[i];
2248 if (!(dimm_mask & (1 << i))) {
2249 if (dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
2250 spd_device = ctrl->channel1[i];
2256 if (meminfo->sz[i].rank == 1) {
2257 mask_single_rank |= 1<<i;
2260 if (meminfo->sz[i].col==10) {
2261 mask_page_1k |= 1<<i;
2265 value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
2267 #if QRANK_DIMM_SUPPORT == 1
2268 rank = meminfo->sz[i].rank;
2273 #if QRANK_DIMM_SUPPORT == 1
2275 mask_x4 |= 1<<(i+2);
2278 } else if (value==16) {
2280 #if QRANK_DIMM_SUPPORT == 1
2282 mask_x16 |= 1<<(i+2);
2289 meminfo->x4_mask= mask_x4;
2290 meminfo->x16_mask = mask_x16;
2292 meminfo->single_rank_mask = mask_single_rank;
2293 meminfo->page_1k_mask = mask_page_1k;
2300 static void set_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2303 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2304 dcl &= ~(DCL_X4Dimm_MASK<<DCL_X4Dimm_SHIFT);
2305 dcl |= ((meminfo->x4_mask) & 0xf) << (DCL_X4Dimm_SHIFT);
2306 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2310 static int count_ones(uint32_t dimm_mask)
2315 for (index = 0; index < (2 * DIMM_SOCKETS); index++, dimm_mask >>= 1) {
2316 if (dimm_mask & 1) {
2324 static void set_DramTerm(const struct mem_controller *ctrl,
2325 const struct mem_param *param, struct mem_info *meminfo)
2331 if (param->divisor == 100) { //DDR2 800
2332 if (meminfo->is_Width128) {
2333 if (count_ones(meminfo->dimm_mask & 0x0f)==2) {
2341 #if CONFIG_DIMM_SUPPORT == 0x0204
2342 odt = 0x2; /* 150 ohms */
2345 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2346 dcl &= ~(DCL_DramTerm_MASK<<DCL_DramTerm_SHIFT);
2347 dcl |= (odt & DCL_DramTerm_MASK) << (DCL_DramTerm_SHIFT);
2348 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2351 static void set_ecc(const struct mem_controller *ctrl,
2352 const struct mem_param *param, struct mem_info *meminfo)
2357 uint32_t dcl, nbcap;
2358 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
2359 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2360 dcl &= ~DCL_DimmEccEn;
2361 if (nbcap & NBCAP_ECC) {
2362 dcl |= DCL_DimmEccEn;
2364 if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
2365 dcl &= ~DCL_DimmEccEn;
2367 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2369 meminfo->is_ecc = 1;
2370 if (!(dcl & DCL_DimmEccEn)) {
2371 meminfo->is_ecc = 0;
2372 return; // already disabled the ECC, so don't need to read SPD any more
2375 for (i = 0; i < DIMM_SOCKETS; i++) {
2376 u32 spd_device = ctrl->channel0[i];
2377 if (!(meminfo->dimm_mask & (1 << i))) {
2378 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
2379 spd_device = ctrl->channel1[i];
2380 printk(BIOS_DEBUG, "set_ecc spd_device: 0x%x\n", spd_device);
2386 value = spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONF_TYPE);
2388 if (!(value & SPD_DIMM_CONF_TYPE_ECC)) {
2389 dcl &= ~DCL_DimmEccEn;
2390 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2391 meminfo->is_ecc = 0;
2399 static int update_dimm_Twtr(const struct mem_controller *ctrl,
2400 const struct mem_param *param, int i, long dimm_mask)
2402 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_HIGH, SPD_TWTR, DTH_TWTR_SHIFT, DTH_TWTR_MASK, DTH_TWTR_BASE, DTH_TWTR_MIN, DTH_TWTR_MAX);
2405 static void set_TT(const struct mem_controller *ctrl,
2406 const struct mem_param *param, unsigned TT_REG, unsigned TT_SHIFT,
2407 unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX,
2408 unsigned val, const char *str)
2412 if ((val < TT_MIN) || (val > TT_MAX)) {
2413 printk(BIOS_ERR, str);
2417 reg = pci_read_config32(ctrl->f2, TT_REG);
2418 reg &= ~(TT_MASK << TT_SHIFT);
2419 reg |= ((val - TT_BASE) << TT_SHIFT);
2420 pci_write_config32(ctrl->f2, TT_REG, reg);
2425 static void set_TrwtTO(const struct mem_controller *ctrl,
2426 const struct mem_param *param)
2428 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRWTTO_SHIFT, DTH_TRWTTO_MASK,DTH_TRWTTO_BASE, DTH_TRWTTO_MIN, DTH_TRWTTO_MAX, param->TrwtTO, "TrwtTO");
2432 static void set_Twrrd(const struct mem_controller *ctrl, const struct mem_param *param)
2434 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRRD_SHIFT, DTH_TWRRD_MASK,DTH_TWRRD_BASE, DTH_TWRRD_MIN, DTH_TWRRD_MAX, param->Twrrd, "Twrrd");
2438 static void set_Twrwr(const struct mem_controller *ctrl, const struct mem_param *param)
2440 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRWR_SHIFT, DTH_TWRWR_MASK,DTH_TWRWR_BASE, DTH_TWRWR_MIN, DTH_TWRWR_MAX, param->Twrwr, "Twrwr");
2443 static void set_Trdrd(const struct mem_controller *ctrl, const struct mem_param *param)
2445 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRDRD_SHIFT, DTH_TRDRD_MASK,DTH_TRDRD_BASE, DTH_TRDRD_MIN, DTH_TRDRD_MAX, param->Trdrd, "Trdrd");
2448 static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem_param *param)
2450 set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS
2453 static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2455 static const uint8_t faw_1k[] = {8, 10, 13, 14};
2456 static const uint8_t faw_2k[] = {10, 14, 17, 18};
2457 unsigned memclkfreq_index;
2461 memclkfreq_index = param->dch_memclk;
2463 if (meminfo->page_1k_mask != 0) { //1k page
2464 faw = faw_1k[memclkfreq_index];
2466 faw = faw_2k[memclkfreq_index];
2469 set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_FourActWindow_SHIFT, DCH_FourActWindow_MASK, DCH_FourActWindow_BASE, DCH_FourActWindow_MIN, DCH_FourActWindow_MAX, faw, "FourActWindow");
2472 static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
2478 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2479 dch &= ~(DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT);
2481 //FIXME: We need to use Max of DqsRcvEnDelay + 6ns here: After trainning and get that from index reg 0x10, 0x13, 0x16, 0x19, 0x30, 0x33, 0x36, 0x39
2485 dch |= ((async_lat - DCH_MaxAsyncLat_BASE) << DCH_MaxAsyncLat_SHIFT);
2486 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2489 #if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
2490 static void set_SlowAccessMode(const struct mem_controller *ctrl)
2494 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2498 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2503 DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20
2504 DRAM_ADDR_TIMING_CTRL 04, 0x24
2506 static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *meminfo)
2510 #if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
2511 unsigned SlowAccessMode = 0;
2514 long dimm_mask = meminfo->dimm_mask & 0x0f;
2516 #if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */
2519 dwordx = 0x002f0000;
2520 switch (meminfo->memclk_set) {
2521 case DCH_MemClkFreq_266MHz:
2522 if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
2523 dwordx = 0x002f2700;
2526 case DCH_MemClkFreq_333MHz:
2527 if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
2528 if ((meminfo->single_rank_mask & 0x03)!=0x03) { //any double rank there?
2529 dwordx = 0x002f2f00;
2533 case DCH_MemClkFreq_400MHz:
2534 dwordx = 0x002f3300;
2540 #if CONFIG_DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */
2542 dwordx = 0x002F2F00;
2544 switch (meminfo->memclk_set) {
2545 case DCH_MemClkFreq_200MHz: /* nothing to be set here */
2547 case DCH_MemClkFreq_266MHz:
2548 if ((meminfo->single_rank_mask == 0)
2549 && (meminfo->x4_mask == 0) && (meminfo->x16_mask))
2550 dwordx = 0x002C2C00; /* Double rank x8 */
2551 /* else SRx16, SRx8, DRx16 == 0x002F2F00 */
2553 case DCH_MemClkFreq_333MHz:
2554 if ((meminfo->single_rank_mask == 1)
2555 && (meminfo->x16_mask == 1)) /* SR x16 */
2556 dwordx = 0x00272700;
2557 else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
2558 && (meminfo->single_rank_mask == 0)) { /* DR x8 */
2560 dwordx = 0x00002800;
2561 } else { /* SR x8, DR x16 */
2562 dwordx = 0x002A2A00;
2565 case DCH_MemClkFreq_400MHz:
2566 if ((meminfo->single_rank_mask == 1)
2567 && (meminfo->x16_mask == 1)) /* SR x16 */
2568 dwordx = 0x00292900;
2569 else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
2570 && (meminfo->single_rank_mask == 0)) { /* DR x8 */
2572 dwordx = 0x00002A00;
2573 } else { /* SR x8, DR x16 */
2574 dwordx = 0x002A2A00;
2580 #if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */
2581 /* for UNBUF DIMM */
2583 dwordx = 0x002f2f00;
2584 switch (meminfo->memclk_set) {
2585 case DCH_MemClkFreq_200MHz:
2586 if (dimm_mask == 0x03) {
2591 case DCH_MemClkFreq_266MHz:
2592 if (dimm_mask == 0x03) {
2595 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
2596 switch (meminfo->single_rank_mask) {
2598 dwordx = 0x00002f00; //x8 single Rank
2601 dwordx = 0x00342f00; //x8 double Rank
2604 dwordx = 0x00372f00; //x8 single Rank and double Rank mixed
2606 } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
2607 dwordx = 0x00382f00; //x8 Double Rank and x16 single Rank mixed
2608 } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
2609 dwordx = 0x00382f00; //x16 single Rank and x8 double Rank mixed
2613 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank
2614 dwordx = 0x002f2f00;
2616 dwordx = 0x002b2f00;
2620 case DCH_MemClkFreq_333MHz:
2621 dwordx = 0x00202220;
2622 if (dimm_mask == 0x03) {
2625 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
2626 switch (meminfo->single_rank_mask) {
2628 dwordx = 0x00302220; //x8 single Rank
2631 dwordx = 0x002b2220; //x8 double Rank
2634 dwordx = 0x002a2220; //x8 single Rank and double Rank mixed
2636 } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
2637 dwordx = 0x002c2220; //x8 Double Rank and x16 single Rank mixed
2638 } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
2639 dwordx = 0x002c2220; //x16 single Rank and x8 double Rank mixed
2643 case DCH_MemClkFreq_400MHz:
2644 dwordx = 0x00202520;
2646 if (dimm_mask == 0x03) {
2654 printk_raminit("\tdimm_mask = %08x\n", meminfo->dimm_mask);
2655 printk_raminit("\tx4_mask = %08x\n", meminfo->x4_mask);
2656 printk_raminit("\tx16_mask = %08x\n", meminfo->x16_mask);
2657 printk_raminit("\tsingle_rank_mask = %08x\n", meminfo->single_rank_mask);
2658 printk_raminit("\tODC = %08x\n", dword);
2659 printk_raminit("\tAddr Timing= %08x\n", dwordx);
2662 #if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
2663 if (SlowAccessMode) {
2664 set_SlowAccessMode(ctrl);
2668 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
2669 /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */
2670 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword);
2672 /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */
2673 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx);
2675 /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */
2676 pci_write_config32_index_wait(ctrl->f2, 0x98, 0, dword);
2677 if (meminfo->is_Width128) {
2678 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword);
2681 /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */
2682 pci_write_config32_index_wait(ctrl->f2, 0x98, 4, dwordx);
2683 if (meminfo->is_Width128) {
2684 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx);
2690 static void set_RDqsEn(const struct mem_controller *ctrl,
2691 const struct mem_param *param, struct mem_info *meminfo)
2693 #if CONFIG_CPU_SOCKET_TYPE==0x10
2694 //only need to set for reg and x8
2697 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2700 if ((!meminfo->x4_mask) && (!meminfo->x16_mask)) {
2704 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2708 static void set_idle_cycle_limit(const struct mem_controller *ctrl,
2709 const struct mem_param *param)
2712 /* AMD says to Hardcode this */
2713 dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
2714 dcm &= ~(DCM_ILD_lmt_MASK << DCM_ILD_lmt_SHIFT);
2715 dcm |= DCM_ILD_lmt_16 << DCM_ILD_lmt_SHIFT;
2717 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
2720 static void set_RdWrQByp(const struct mem_controller *ctrl,
2721 const struct mem_param *param)
2723 set_TT(ctrl, param, DRAM_CTRL_MISC, DCM_RdWrQByp_SHIFT, DCM_RdWrQByp_MASK,0, 0, 3, 2, "RdWrQByp");
2726 static long spd_set_dram_timing(const struct mem_controller *ctrl,
2727 const struct mem_param *param,
2728 struct mem_info *meminfo)
2732 for (i = 0; i < DIMM_SOCKETS; i++) {
2734 if (!(meminfo->dimm_mask & (1 << i)) &&
2735 !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) ) {
2738 printk_raminit("spd_set_dram_timing dimm socket: %08x\n", i);
2739 /* DRAM Timing Low Register */
2740 printk_raminit("\ttrc\n");
2741 if ((rc = update_dimm_Trc (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2743 printk_raminit("\ttrcd\n");
2744 if ((rc = update_dimm_Trcd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2746 printk_raminit("\ttrrd\n");
2747 if ((rc = update_dimm_Trrd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2749 printk_raminit("\ttras\n");
2750 if ((rc = update_dimm_Tras(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2752 printk_raminit("\ttrp\n");
2753 if ((rc = update_dimm_Trp (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2755 printk_raminit("\ttrtp\n");
2756 if ((rc = update_dimm_Trtp(ctrl, param, i, meminfo)) <= 0) goto dimm_err;
2758 printk_raminit("\ttwr\n");
2759 if ((rc = update_dimm_Twr (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2761 /* DRAM Timing High Register */
2762 printk_raminit("\ttref\n");
2763 if ((rc = update_dimm_Tref(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2765 printk_raminit("\ttwtr\n");
2766 if ((rc = update_dimm_Twtr(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2768 printk_raminit("\ttrfc\n");
2769 if ((rc = update_dimm_Trfc(ctrl, param, i, meminfo)) <= 0) goto dimm_err;
2771 /* DRAM Config Low */
2775 printk(BIOS_DEBUG, "spd_set_dram_timing dimm_err!\n");
2779 meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo);
2782 get_extra_dimm_mask(ctrl, meminfo); // will be used by RDqsEn and dimm_x4
2783 /* DRAM Timing Low Register */
2785 /* DRAM Timing High Register */
2786 set_TrwtTO(ctrl, param);
2787 set_Twrrd (ctrl, param);
2788 set_Twrwr (ctrl, param);
2789 set_Trdrd (ctrl, param);
2791 set_4RankRDimm(ctrl, param, meminfo);
2793 /* DRAM Config High */
2794 set_Tfaw(ctrl, param, meminfo);
2795 set_DcqBypassMax(ctrl, param);
2796 set_max_async_latency(ctrl, param);
2797 set_RDqsEn(ctrl, param, meminfo);
2799 /* DRAM Config Low */
2800 set_ecc(ctrl, param, meminfo);
2801 set_dimm_x4(ctrl, param, meminfo);
2802 set_DramTerm(ctrl, param, meminfo);
2804 /* DRAM Control Misc */
2805 set_idle_cycle_limit(ctrl, param);
2806 set_RdWrQByp(ctrl, param);
2808 return meminfo->dimm_mask;
2811 static void sdram_set_spd_registers(const struct mem_controller *ctrl,
2812 struct sys_info *sysinfo)
2814 struct spd_set_memclk_result result;
2815 const struct mem_param *param;
2816 struct mem_param paramx;
2817 struct mem_info *meminfo;
2819 if (!sysinfo->ctrl_present[ctrl->node_id]) {
2823 meminfo = &sysinfo->meminfo[ctrl->node_id];
2825 printk(BIOS_DEBUG, "sdram_set_spd_registers: paramx :%p\n", ¶mx);
2827 activate_spd_rom(ctrl);
2828 meminfo->dimm_mask = spd_detect_dimms(ctrl);
2830 printk_raminit("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask);
2832 if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1)))
2834 printk(BIOS_DEBUG, "No memory for this cpu\n");
2837 meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo);
2838 printk_raminit("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask);
2839 if (meminfo->dimm_mask == -1)
2842 meminfo->dimm_mask = spd_set_ram_size(ctrl, meminfo);
2843 printk_raminit("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask);
2844 if (meminfo->dimm_mask == -1)
2847 meminfo->dimm_mask = spd_handle_unbuffered_dimms(ctrl, meminfo);
2848 printk_raminit("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask);
2849 if (meminfo->dimm_mask == -1)
2852 result = spd_set_memclk(ctrl, meminfo);
2853 param = result.param;
2854 meminfo->dimm_mask = result.dimm_mask;
2855 printk_raminit("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask);
2856 if (meminfo->dimm_mask == -1)
2859 //store memclk set to sysinfo, incase we need rebuilt param again
2860 meminfo->memclk_set = param->dch_memclk;
2862 memcpy(¶mx, param, sizeof(paramx));
2864 paramx.divisor = get_exact_divisor(param->dch_memclk, paramx.divisor);
2866 meminfo->dimm_mask = spd_set_dram_timing(ctrl, ¶mx, meminfo);
2867 printk_raminit("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask);
2868 if (meminfo->dimm_mask == -1)
2871 order_dimms(ctrl, meminfo);
2875 /* Unrecoverable error reading SPD data */
2876 die("Unrecoverable error reading SPD data. No qualified DIMMs?");
2880 #define TIMEOUT_LOOPS 300000
2882 #include "raminit_f_dqs.c"
2884 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
2885 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i)
2888 uint32_t carry_over;
2890 uint32_t base, limit;
2895 carry_over = (4*1024*1024) - hole_startk;
2897 for (ii=controllers - 1;ii>i;ii--) {
2898 base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
2899 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2902 limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
2903 limit += (carry_over << 2 );
2904 base += (carry_over << 2 );
2905 for (j = 0; j < controllers; j++) {
2906 pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit);
2907 pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base );
2910 limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
2911 limit += (carry_over << 2);
2912 for (j = 0; j < controllers; j++) {
2913 pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit);
2916 base = pci_read_config32(dev, 0x40 + (i << 3));
2917 basek = (base & 0xffff0000) >> 2;
2918 if (basek == hole_startk) {
2919 //don't need set memhole here, because hole off set will be 0, overflow
2920 //so need to change base reg instead, new basek will be 4*1024*1024
2922 base |= (4*1024*1024)<<2;
2923 for (j = 0; j < controllers; j++) {
2924 pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
2927 hoist = /* hole start address */
2928 ((hole_startk << 10) & 0xff000000) +
2929 /* hole address to memory controller address */
2930 (((basek + carry_over) >> 6) & 0x0000ff00) +
2933 pci_write_config32(dev, 0xf0, hoist);
2939 static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
2942 uint32_t hole_startk;
2945 hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
2947 printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk);
2948 #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
2949 /* We need to double check if the hole_startk is valid, if it is equal
2950 to basek, we need to decrease it some */
2952 for (i=0; i<controllers; i++) {
2955 base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
2956 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2959 base_k = (base & 0xffff0000) >> 2;
2960 if (base_k == hole_startk) {
2961 /* decrease mem hole startk to make sure it is
2962 on middle of previous node */
2963 hole_startk -= (base_k - basek_pri) >> 1;
2964 break; //only one hole
2968 printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
2970 /* find node index that need do set hole */
2971 for (i=0; i < controllers; i++) {
2972 uint32_t base, limit;
2973 unsigned base_k, limit_k;
2974 base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
2975 if ((base & ((1 << 1) | (1 << 0))) != ((1 << 1) | (1 << 0))) {
2978 limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
2979 base_k = (base & 0xffff0000) >> 2;
2980 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
2981 if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
2983 hoist_memory(controllers, ctrl, hole_startk, i);
2984 end_k = memory_end_k(ctrl, controllers);
2985 set_top_mem(end_k, hole_startk);
2986 break; //only one hole
2993 #include "exit_from_self.c"
2995 static void sdram_enable(int controllers, const struct mem_controller *ctrl,
2996 struct sys_info *sysinfo)
2999 #ifdef ACPI_IS_WAKEUP_EARLY
3000 int suspend = acpi_is_wakeup_early();
3005 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3006 unsigned cpu_f0_f1[8];
3007 /* FIXME: How about 32 node machine later? */
3010 printk(BIOS_DEBUG, "sdram_enable: tsc0[8]: %p", &tsc0[0]);
3014 /* Error if I don't have memory */
3015 if (memory_end_k(ctrl, controllers) == 0) {
3019 /* Before enabling memory start the memory clocks */
3020 for (i = 0; i < controllers; i++) {
3022 if (!sysinfo->ctrl_present[ i ])
3024 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
3026 /* if no memory installed, disabled the interface */
3027 if (sysinfo->meminfo[i].dimm_mask==0x00){
3028 dch |= DCH_DisDramInterface;
3029 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
3032 dch |= DCH_MemClkFreqVal;
3033 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
3034 /* address timing and Output driver comp Control */
3035 set_misc_timing(ctrl+i, sysinfo->meminfo+i );
3039 /* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */
3040 memreset(controllers, ctrl);
3042 /* lets override the rest of the routine */
3044 printk(BIOS_DEBUG, "Wakeup!\n");
3045 exit_from_self(controllers, ctrl, sysinfo);
3046 printk(BIOS_DEBUG, "Mem running !\n");
3050 for (i = 0; i < controllers; i++) {
3052 if (!sysinfo->ctrl_present[ i ])
3054 /* Skip everything if I don't have any memory on this controller */
3055 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
3056 if (!(dch & DCH_MemClkFreqVal)) {
3061 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
3062 if (dcl & DCL_DimmEccEn) {
3064 printk(BIOS_SPEW, "ECC enabled\n");
3065 mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
3067 if (dcl & DCL_Width128) {
3068 mnc |= MNC_CHIPKILL_EN;
3070 pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
3073 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3074 cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i);
3076 //Rev F0/F1 workaround
3078 /* Set the DqsRcvEnTrain bit */
3079 dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
3080 dword |= DC_DqsRcvEnTrain;
3081 pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
3087 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
3088 dcl |= DCL_InitDram;
3089 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
3092 for (i = 0; i < controllers; i++) {
3094 if (!sysinfo->ctrl_present[ i ])
3096 /* Skip everything if I don't have any memory on this controller */
3097 if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
3099 printk(BIOS_DEBUG, "Initializing memory: ");
3102 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
3104 if ((loops & 1023) == 0) {
3105 printk(BIOS_DEBUG, ".");
3107 } while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS));
3108 if (loops >= TIMEOUT_LOOPS) {
3109 printk(BIOS_DEBUG, " failed\n");
3113 /* Wait until it is safe to touch memory */
3115 dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
3116 } while(((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ );
3118 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3122 print_debug_dqs_tsc("\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
3123 print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2);
3125 if (tsc.lo<tsc0[i].lo) {
3128 tsc.lo -= tsc0[i].lo;
3129 tsc.hi -= tsc0[i].hi;
3131 tsc0[i].lo = tsc.lo;
3132 tsc0[i].hi = tsc.hi;
3134 print_debug_dqs_tsc(" dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
3137 printk(BIOS_DEBUG, " done\n");
3140 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
3141 /* init hw mem hole here */
3142 /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
3143 set_hw_mem_hole(controllers, ctrl);
3146 /* store tom to sysinfo, and it will be used by dqs_timing */
3150 msr = rdmsr(TOP_MEM);
3151 sysinfo->tom_k = ((msr.hi<<24) | (msr.lo>>8))>>2;
3154 msr = rdmsr(TOP_MEM2);
3155 sysinfo->tom2_k = ((msr.hi<<24)| (msr.lo>>8))>>2;
3158 for (i = 0; i < controllers; i++) {
3159 sysinfo->mem_trained[i] = 0;
3161 if (!sysinfo->ctrl_present[ i ])
3164 /* Skip everything if I don't have any memory on this controller */
3165 if (sysinfo->meminfo[i].dimm_mask==0x00)
3168 sysinfo->mem_trained[i] = 0x80; // mem need to be trained
3172 #if CONFIG_MEM_TRAIN_SEQ == 0
3173 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3174 dqs_timing(controllers, ctrl, tsc0, sysinfo);
3176 dqs_timing(controllers, ctrl, sysinfo);
3180 #if CONFIG_MEM_TRAIN_SEQ == 2
3181 /* need to enable mtrr, so dqs training could access the test address */
3182 setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
3185 for (i = 0; i < controllers; i++) {
3186 /* Skip everything if I don't have any memory on this controller */
3187 if (sysinfo->mem_trained[i]!=0x80)
3190 dqs_timing(i, &ctrl[i], sysinfo, 1);
3192 #if CONFIG_MEM_TRAIN_SEQ == 1
3193 break; // only train the first node with ram
3197 #if CONFIG_MEM_TRAIN_SEQ == 2
3198 clear_mtrr_dqs(sysinfo->tom2_k);
3203 #if CONFIG_MEM_TRAIN_SEQ != 1
3204 wait_all_core0_mem_trained(sysinfo);
3209 static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
3210 const uint16_t *spd_addr)
3214 struct mem_controller *ctrl;
3215 for (i=0;i<controllers; i++) {
3218 ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
3219 ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
3220 ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
3221 ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
3223 if (spd_addr == (void *)0) continue;
3225 for (j=0;j<DIMM_SOCKETS;j++) {
3226 ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
3227 ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];