2 * This file is part of the coreboot project.
4 * Copyright (C) 2002 Linux Networx
5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
6 * Copyright (C) 2004 YingHai Lu
7 * Copyright (C) 2008 Advanced Micro Devices, Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <cpu/x86/mem.h>
24 #include <cpu/x86/cache.h>
25 #include <cpu/x86/mtrr.h>
26 #include <cpu/x86/tsc.h>
33 #ifndef QRANK_DIMM_SUPPORT
34 #define QRANK_DIMM_SUPPORT 0
37 static inline void print_raminit(const char *strval, uint32_t val)
39 #if CONFIG_USE_PRINTK_IN_CAR
40 printk_debug("%s%08x\r\n", strval, val);
42 print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
46 #define RAM_TIMING_DEBUG 0
48 static inline void print_tx(const char *strval, uint32_t val)
50 #if RAM_TIMING_DEBUG == 1
51 print_raminit(strval, val);
56 static inline void print_t(const char *strval)
58 #if RAM_TIMING_DEBUG == 1
65 #if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
66 # error "CONFIG_LB_MEM_TOPK must be a power of 2"
69 #include "amdk8_f_pci.c"
72 /* for PCI_ADDR(0, 0x18, 2, 0x98) index,
73 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
76 [29: 0] DctOffset (Dram Controller Offset)
77 [30:30] DctAccessWrite (Dram Controller Read/Write Select)
80 [31:31] DctAccessDone (Dram Controller Access Done)
81 0 = Access in progress
82 1 = No access is progress
85 [31: 0] DctOffsetData (Dram Controller Offset Data)
88 - Write the register num to DctOffset with
90 - poll the DctAccessDone until it = 1
91 - Read the data from DctOffsetData
93 - Write the data to DctOffsetData
94 - Write register num to DctOffset with DctAccessWrite = 1
95 - poll the DctAccessDone untio it = 1
99 static void setup_resource_map(const unsigned int *register_values, int max)
102 for (i = 0; i < max; i += 3) {
106 dev = register_values[i] & ~0xff;
107 where = register_values[i] & 0xff;
108 reg = pci_read_config32(dev, where);
109 reg &= register_values[i+1];
110 reg |= register_values[i+2];
111 pci_write_config32(dev, where, reg);
115 static int controller_present(const struct mem_controller *ctrl)
117 return pci_read_config32(ctrl->f0, 0) == 0x11001022;
120 static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
122 static const unsigned int register_values[] = {
124 /* Careful set limit registers before base registers which
125 contain the enables */
126 /* DRAM Limit i Registers
135 * [ 2: 0] Destination Node ID
145 * [10: 8] Interleave select
146 * specifies the values of A[14:12] to use with interleave enable.
148 * [31:16] DRAM Limit Address i Bits 39-24
149 * This field defines the upper address bits of a 40 bit address
150 * that define the end of the DRAM region.
152 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
153 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
154 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
155 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
156 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
157 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
158 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
159 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
160 /* DRAM Base i Registers
169 * [ 0: 0] Read Enable
172 * [ 1: 1] Write Enable
173 * 0 = Writes Disabled
176 * [10: 8] Interleave Enable
177 * 000 = No interleave
178 * 001 = Interleave on A[12] (2 nodes)
180 * 011 = Interleave on A[12] and A[14] (4 nodes)
184 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
186 * [13:16] DRAM Base Address i Bits 39-24
187 * This field defines the upper address bits of a 40-bit address
188 * that define the start of the DRAM region.
190 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
191 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
192 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
193 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
194 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
195 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
196 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
197 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
199 /* DRAM CS Base Address i Registers
208 * [ 0: 0] Chip-Select Bank Enable
212 * [ 2: 2] Memory Test Failed
214 * [13: 5] Base Address (21-13)
215 * An optimization used when all DIMM are the same size...
217 * [28:19] Base Address (36-27)
218 * This field defines the top 11 addresses bit of a 40-bit
219 * address that define the memory address space. These
220 * bits decode 32-MByte blocks of memory.
223 PCI_ADDR(0, 0x18, 2, 0x40), 0xe007c018, 0x00000000,
224 PCI_ADDR(0, 0x18, 2, 0x44), 0xe007c018, 0x00000000,
225 PCI_ADDR(0, 0x18, 2, 0x48), 0xe007c018, 0x00000000,
226 PCI_ADDR(0, 0x18, 2, 0x4C), 0xe007c018, 0x00000000,
227 PCI_ADDR(0, 0x18, 2, 0x50), 0xe007c018, 0x00000000,
228 PCI_ADDR(0, 0x18, 2, 0x54), 0xe007c018, 0x00000000,
229 PCI_ADDR(0, 0x18, 2, 0x58), 0xe007c018, 0x00000000,
230 PCI_ADDR(0, 0x18, 2, 0x5C), 0xe007c018, 0x00000000,
231 /* DRAM CS Mask Address i Registers
236 * Select bits to exclude from comparison with the DRAM Base address register.
238 * [13: 5] Address Mask (21-13)
239 * Address to be excluded from the optimized case
241 * [28:19] Address Mask (36-27)
242 * The bits with an address mask of 1 are excluded from address comparison
246 PCI_ADDR(0, 0x18, 2, 0x60), 0xe007c01f, 0x00000000,
247 PCI_ADDR(0, 0x18, 2, 0x64), 0xe007c01f, 0x00000000,
248 PCI_ADDR(0, 0x18, 2, 0x68), 0xe007c01f, 0x00000000,
249 PCI_ADDR(0, 0x18, 2, 0x6C), 0xe007c01f, 0x00000000,
251 /* DRAM Control Register
253 * [ 3: 0] RdPtrInit ( Read Pointer Initial Value)
254 * 0x03-0x00: reserved
255 * [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO)
258 * 010 = 1.5 Memory Clocks
259 * 011 = 2 Memory Clocks
260 * 100 = 2.5 Memory Clocks
261 * 101 = 3 Memory Clocks
262 * 110 = 3.5 Memory Clocks
265 * [16:16] AltVidC3MemClkTriEn (AltVID Memory Clock Tristate Enable)
266 * Enables the DDR memory clocks to be tristated when alternate VID
267 * mode is enabled. This bit has no effect if the DisNbClkRamp bit
269 * [17:17] DllTempAdjTime (DLL Temperature Adjust Cycle Time)
272 * [18:18] DqsRcvEnTrain (DQS Receiver Enable Training Mode)
273 * 0 = Normal DQS Receiver enable operation
274 * 1 = DQS receiver enable training mode
277 PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6<<4)|(6<<0),
279 /* DRAM Initialization Register
281 * [15: 0] MrsAddress (Address for MRS/EMRS Commands)
282 * this field specifies the dsata driven on the DRAM address pins
283 * 15-0 for MRS and EMRS commands
284 * [18:16] MrsBank (Bank Address for MRS/EMRS Commands)
285 * this files specifies the data driven on the DRAM bank pins for
286 * the MRS and EMRS commands
288 * [24:24] SendPchgAll (Send Precharge All Command)
289 * Setting this bit causes the DRAM controller to send a precharge
290 * all command. This bit is cleared by the hardware after the
292 * [25:25] SendAutoRefresh (Send Auto Refresh Command)
293 * Setting this bit causes the DRAM controller to send an auto
294 * refresh command. This bit is cleared by the hardware after the
296 * [26:26] SendMrsCmd (Send MRS/EMRS Command)
297 * Setting this bit causes the DRAM controller to send the MRS or
298 * EMRS command defined by the MrsAddress and MrsBank fields. This
299 * bit is cleared by the hardware adter the commmand completes
300 * [27:27] DeassertMemRstX (De-assert Memory Reset)
301 * Setting this bit causes the DRAM controller to de-assert the
302 * memory reset pin. This bit cannot be used to assert the memory
304 * [28:28] AssertCke (Assert CKE)
305 * setting this bit causes the DRAM controller to assert the CKE
306 * pins. This bit cannot be used to de-assert the CKE pins
308 * [31:31] EnDramInit (Enable DRAM Initialization)
309 * Setting this bit puts the DRAM controller in a BIOS controlled
310 * DRAM initialization mode. BIOS must clear this bit aster DRAM
311 * initialization is complete.
313 // PCI_ADDR(0, 0x18, 2, 0x7C), 0x60f80000, 0,
316 /* DRAM Bank Address Mapping Register
318 * Specify the memory module size
338 PCI_ADDR(0, 0x18, 2, 0x80), 0xffff0000, 0x00000000,
339 /* DRAM Timing Low Register
341 * [ 2: 0] Tcl (Cas# Latency, Cas# to read-data-valid)
351 * [ 5: 4] Trcd (Ras#-active to Cas# read/write delay)
357 * [ 9: 8] Trp (Row Precharge Time, Precharge-to-Active or Auto-Refresh)
363 * [11:11] Trtp (Read to Precharge Time, read Cas# to precharge time)
364 * 0 = 2 clocks for Burst Length of 32 Bytes
365 * 4 clocks for Burst Length of 64 Bytes
366 * 1 = 3 clocks for Burst Length of 32 Bytes
367 * 5 clocks for Burst Length of 64 Bytes
368 * [15:12] Tras (Minimum Ras# Active Time)
371 * 0010 = 5 bus clocks
373 * 1111 = 18 bus clocks
374 * [19:16] Trc (Row Cycle Time, Ras#-active to Ras#-active or auto
375 * refresh of the same bank)
376 * 0000 = 11 bus clocks
377 * 0010 = 12 bus clocks
379 * 1110 = 25 bus clocks
380 * 1111 = 26 bus clocks
381 * [21:20] Twr (Write Recovery Time, From the last data to precharge,
382 * writes can go back-to-back)
387 * [23:22] Trrd (Active-to-active(Ras#-to-Ras#) Delay of different banks)
392 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A,
393 * BIOS should set it to reduce the power consumption)
394 * Bit F(1207) M2 Package S1g1 Package
396 * 1 N/A MA0_CLK1 MA0_CLK1
399 * 4 MA1_CLK MA1_CLK0 N/A
400 * 5 MA0_CLK MA0_CLK0 MA0_CLK0
402 * 7 N/A MA0_CLK2 MA0_CLK2
404 PCI_ADDR(0, 0x18, 2, 0x88), 0x000004c8, 0xff000002 /* 0x03623125 */ ,
405 /* DRAM Timing High Register
408 * [ 6: 4] TrwtTO (Read-to-Write Turnaround for Data, DQS Contention)
418 * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay,
419 * minium write-to-read delay when both access the same chip select)
424 * [11:10] Twrrd (Write to Read DIMM Termination Turnaround, minimum
425 * write-to-read delay when accessing two different DIMMs)
430 * [13:12] Twrwr (Write to Write Timing)
431 * 00 = 1 bus clocks ( 0 idle cycle on the bus)
432 * 01 = 2 bus clocks ( 1 idle cycle on the bus)
433 * 10 = 3 bus clocks ( 2 idle cycles on the bus)
435 * [15:14] Trdrd ( Read to Read Timing)
436 * 00 = 2 bus clocks ( 1 idle cycle on the bus)
437 * 01 = 3 bus clocks ( 2 idle cycles on the bus)
438 * 10 = 4 bus clocks ( 3 idle cycles on the bus)
439 * 11 = 5 bus clocks ( 4 idel cycles on the bus)
440 * [17:16] Tref (Refresh Rate)
441 * 00 = Undefined behavior
443 * 10 = Refresh interval of 7.8 microseconds
444 * 11 = Refresh interval of 3.9 microseconds
446 * [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0,
447 * based on DRAM density and speed)
448 * 000 = 75 ns (all speeds, 256Mbit)
449 * 001 = 105 ns (all speeds, 512Mbit)
450 * 010 = 127.5 ns (all speeds, 1Gbit)
451 * 011 = 195 ns (all speeds, 2Gbit)
452 * 100 = 327.5 ns (all speeds, 4Gbit)
456 * [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1,
457 * based on DRAM density and speed)
458 * [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2,
459 * based on DRAM density and speed)
460 * [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3,
461 * based on DRAM density and speed)
463 PCI_ADDR(0, 0x18, 2, 0x8c), 0x000c008f, (2 << 16)|(1 << 8),
464 /* DRAM Config Low Register
466 * [ 0: 0] InitDram (Initialize DRAM)
467 * 1 = write 1 cause DRAM controller to execute the DRAM
468 * initialization, when done it read to 0
469 * [ 1: 1] ExitSelfRef ( Exit Self Refresh Command )
470 * 1 = write 1 causes the DRAM controller to bring the DRAMs out
471 * for self refresh mode
473 * [ 5: 4] DramTerm (DRAM Termination)
474 * 00 = On die termination disabled
479 * [ 7: 7] DramDrvWeak ( DRAM Drivers Weak Mode)
480 * 0 = Normal drive strength mode.
481 * 1 = Weak drive strength mode
482 * [ 8: 8] ParEn (Parity Enable)
483 * 1 = Enable address parity computation output, PAR,
484 * and enables the parity error input, ERR
485 * [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable)
486 * 1 = Enable high temperature ( two times normal )
488 * [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes)
491 * [11:11] Width128 ( Width of DRAM interface)
492 * 0 = the controller DRAM interface is 64-bits wide
493 * 1 = the controller DRAM interface is 128-bits wide
494 * [12:12] X4Dimm (DIMM 0 is x4)
495 * [13:13] X4Dimm (DIMM 1 is x4)
496 * [14:14] X4Dimm (DIMM 2 is x4)
497 * [15:15] X4Dimm (DIMM 3 is x4)
499 * 1 = x4 DIMM present
500 * [16:16] UnBuffDimm ( Unbuffered DIMMs)
502 * 1 = Unbuffered DIMMs
504 * [19:19] DimmEccEn ( DIMM ECC Enable )
505 * 1 = ECC checking is being enabled for all DIMMs on the DRAM
506 * controller ( Through F3 0x44[EccEn])
509 PCI_ADDR(0, 0x18, 2, 0x90), 0xfff6004c, 0x00000010,
510 /* DRAM Config High Register
512 * [ 0: 2] MemClkFreq ( Memory Clock Frequency)
518 * [ 3: 3] MemClkFreqVal (Memory Clock Freqency Valid)
519 * 1 = BIOS need to set the bit when setting up MemClkFreq to
521 * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency)
526 * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8
527 * registered DIMMs are present in the system
528 * 0 = DM pins function as data mask pins
529 * 1 = DM pins function as read DQS pins
531 * [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit
532 * is set, the DRAM controller is disabled, and interface in low power
534 * 0 = Enabled (default)
536 * [15:15] PowerDownEn ( Power Down Mode Enable )
537 * 0 = Disabled (default)
539 * [16:16] PowerDown ( Power Down Mode )
540 * 0 = Channel CKE Control
541 * 1 = Chip Select CKE Control
542 * [17:17] FourRankSODimm (Four Rank SO-DIMM)
543 * 1 = this bit is set by BIOS to indicate that a four rank
545 * [18:18] FourRankRDimm (Four Rank Registered DIMM)
546 * 1 = this bit is set by BIOS to indicate that a four rank
547 * registered DIMM is present
549 * [20:20] SlowAccessMode (Slow Access Mode (2T Mode))
550 * 0 = DRAM address and control signals are driven for one
552 * 1 = One additional MEMCLK of setup time is provided on all
553 * DRAM address and control signals except CS, CKE, and ODT;
554 * i.e., these signals are drivern for two MEMCLK cycles
557 * [22:22] BankSwizzleMode ( Bank Swizzle Mode),
558 * 0 = Disabled (default)
561 * [27:24] DcqBypassMax ( DRAM Controller Queue Bypass Maximum)
562 * 0000 = No bypass; the oldest request is never bypassed
563 * 0001 = The oldest request may be bypassed no more than 1 time
565 * 1111 = The oldest request may be bypassed no more than 15\
567 * [31:28] FourActWindow ( Four Bank Activate Window) , not more than
568 * 4 banks in a 8 bank device are activated
569 * 0000 = No tFAW window restriction
570 * 0001 = 8 MEMCLK cycles
571 * 0010 = 9 MEMCLK cycles
573 * 1101 = 20 MEMCLK cycles
576 PCI_ADDR(0, 0x18, 2, 0x94), 0x00a82f00,0x00008000,
577 /* DRAM Delay Line Register
579 * [ 0: 0] MemClrStatus (Memory Clear Status) : Readonly
580 * when set, this bit indicates that the memory clear function
581 * is complete. Only clear by reset. BIOS should not write or
582 * read the DRAM until this bit is set by hardware
583 * [ 1: 1] DisableJitter ( Disable Jitter)
584 * When set the DDR compensation circuit will not change the
585 * values unless the change is more than one step from the
587 * [ 3: 2] RdWrQByp ( Read/Write Queue Bypass Count)
592 * [ 4: 4] Mode64BitMux (Mismatched DIMM Support Enable)
593 * 1 When bit enables support for mismatched DIMMs when using
594 * 128-bit DRAM interface, the Width128 no effect, only for
596 * [ 5: 5] DCC_EN ( Dynamica Idle Cycle Counter Enable)
597 * When set to 1, indicates that each entry in the page tables
598 * dynamically adjusts the idle cycle limit based on page
599 * Conflict/Page Miss (PC/PM) traffic
600 * [ 8: 6] ILD_lmt ( Idle Cycle Limit)
609 * [ 9: 9] DramEnabled ( DRAM Enabled)
610 * When Set, this bit indicates that the DRAM is enabled, this
611 * bit is set by hardware after DRAM initialization or on an exit
612 * from self refresh. The DRAM controller is intialized after the
613 * hardware-controlled initialization process ( initiated by the
614 * F2 0x90[DramInit]) completes or when the BIOS-controlled
615 * initialization process completes (F2 0x7c(EnDramInit] is
616 * written from 1 to 0)
618 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B,
619 * BIOS should set it to reduce the power consumption)
620 * Bit F(1207) M2 Package S1g1 Package
622 * 1 N/A MA0_CLK1 MA0_CLK1
625 * 4 MA1_CLK MA1_CLK0 N/A
626 * 5 MA0_CLK MA0_CLK0 MA0_CLK0
628 * 7 N/A MA0_CLK2 MA0_CLK2
630 PCI_ADDR(0, 0x18, 2, 0xa0), 0x00fffc00, 0xff000000,
632 /* DRAM Scrub Control Register
634 * [ 4: 0] DRAM Scrube Rate
636 * [12: 8] L2 Scrub Rate
638 * [20:16] Dcache Scrub
641 * 00000 = Do not scrub
663 * All Others = Reserved
665 PCI_ADDR(0, 0x18, 3, 0x58), 0xffe0e0e0, 0x00000000,
666 /* DRAM Scrub Address Low Register
668 * [ 0: 0] DRAM Scrubber Redirect Enable
670 * 1 = Scrubber Corrects errors found in normal operation
672 * [31: 6] DRAM Scrub Address 31-6
674 PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000,
675 /* DRAM Scrub Address High Register
677 * [ 7: 0] DRAM Scrubb Address 39-32
680 PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
682 /* for PCI_ADDR(0, 0x18, 2, 0x98) index,
683 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
686 [29: 0] DctOffset (Dram Controller Offset)
687 [30:30] DctAccessWrite (Dram Controller Read/Write Select)
690 [31:31] DctAccessDone (Dram Controller Access Done)
691 0 = Access in progress
692 1 = No access is progress
695 [31: 0] DctOffsetData (Dram Controller Offset Data)
698 - Write the register num to DctOffset with DctAccessWrite = 0
699 - poll the DctAccessDone until it = 1
700 - Read the data from DctOffsetData
702 - Write the data to DctOffsetData
703 - Write register num to DctOffset with DctAccessWrite = 1
704 - poll the DctAccessDone untio it = 1
710 if (!controller_present(ctrl)) {
711 sysinfo->ctrl_present[ctrl->node_id] = 0;
714 sysinfo->ctrl_present[ctrl->node_id] = 1;
716 print_spew("setting up CPU");
717 print_spew_hex8(ctrl->node_id);
718 print_spew(" northbridge registers\r\n");
719 max = ARRAY_SIZE(register_values);
720 for (i = 0; i < max; i += 3) {
724 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
725 where = register_values[i] & 0xff;
726 reg = pci_read_config32(dev, where);
727 reg &= register_values[i+1];
728 reg |= register_values[i+2];
729 pci_write_config32(dev, where, reg);
732 print_spew("done.\r\n");
736 static int is_dual_channel(const struct mem_controller *ctrl)
739 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
740 return dcl & DCL_Width128;
744 static int is_opteron(const struct mem_controller *ctrl)
746 /* Test to see if I am an Opteron.
747 * FIXME Testing dual channel capability is correct for now
748 * but a better test is probably required.
749 * m2 and s1g1 support dual channel too. but only support unbuffered dimm
751 #warning "FIXME implement a better test for opterons"
753 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
754 return !!(nbcap & NBCAP_128Bit);
758 static int is_registered(const struct mem_controller *ctrl)
760 /* Test to see if we are dealing with registered SDRAM.
761 * If we are not registered we are unbuffered.
762 * This function must be called after spd_handle_unbuffered_dimms.
765 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
766 return !(dcl & DCL_UnBuffDimm);
770 static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
772 /* Calculate the log base 2 size of a DIMM in bits */
779 value = spd_read_byte(device, SPD_ROW_NUM); /* rows */
780 if (value < 0) goto hw_err;
781 if ((value & 0xff) == 0) goto val_err; /* max is 16 ? */
782 sz->per_rank += value & 0xff;
783 sz->rows = value & 0xff;
785 value = spd_read_byte(device, SPD_COL_NUM); /* columns */
786 if (value < 0) goto hw_err;
787 if ((value & 0xff) == 0) goto val_err; /* max is 11 */
788 sz->per_rank += value & 0xff;
789 sz->col = value & 0xff;
791 value = spd_read_byte(device, SPD_BANK_NUM); /* banks */
792 if (value < 0) goto hw_err;
793 if ((value & 0xff) == 0) goto val_err;
794 sz->bank = log2(value & 0xff); // convert 4 to 2, and 8 to 3
795 sz->per_rank += sz->bank;
797 /* Get the module data width and convert it to a power of two */
798 value = spd_read_byte(device, SPD_DATA_WIDTH);
799 if (value < 0) goto hw_err;
801 if ((value != 72) && (value != 64)) goto val_err;
802 sz->per_rank += log2(value) - 3; //64 bit So another 3 lines
804 /* How many ranks? */
805 /* number of physical banks */
806 value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK);
807 if (value < 0) goto hw_err;
808 /* value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT; */
809 value &= SPD_MOD_ATTRIB_RANK_NUM_MASK;
810 value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4
812 rank == 1 only one rank or say one side
813 rank == 2 two side , and two ranks
814 rank == 4 two side , and four ranks total
815 Some one side two ranks, because of stacked
817 if ((value != 1) && (value != 2) && (value != 4 )) {
822 /* verify if per_rank is equal byte 31
823 it has the DIMM size as a multiple of 128MB.
825 value = spd_read_byte(device, SPD_RANK_SIZE);
826 if (value < 0) goto hw_err;
829 if (value <=4 ) value += 8; // add back to 1G to high
830 value += (27-5); // make 128MB to the real lines
831 if ( value != (sz->per_rank)) {
832 print_err("Bad RANK Size --\r\n");
839 die("Bad SPD value\r\n");
840 /* If an hw_error occurs report that I have no memory */
852 static void set_dimm_size(const struct mem_controller *ctrl,
853 struct dimm_size *sz, unsigned index, struct mem_info *meminfo)
855 uint32_t base0, base1;
857 /* For each base register.
858 * Place the dimm size in 32 MB quantities in the bits 31 - 21.
859 * The initialize dimm size is in bits.
860 * Set the base enable bit0.
865 /* Make certain side1 of the dimm is at least 128MB */
866 if (sz->per_rank >= 27) {
867 base0 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
870 /* Make certain side2 of the dimm is at least 128MB */
871 if (sz->rank > 1) { // 2 ranks or 4 ranks
872 base1 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
875 /* Double the size if we are using dual channel memory */
876 if (meminfo->is_Width128) {
877 base0 = (base0 << 1) | (base0 & 1);
878 base1 = (base1 << 1) | (base1 & 1);
881 /* Clear the reserved bits */
882 base0 &= ~0xe007fffe;
883 base1 &= ~0xe007fffe;
885 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
886 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
887 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
889 /* Set the appropriate DIMM base address register */
890 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0);
891 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1);
892 #if QRANK_DIMM_SUPPORT == 1
894 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
895 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
900 /* Enable the memory clocks for this DIMM by Clear the MemClkDis bit*/
904 #if CPU_SOCKET_TYPE == 0x10 /* L1 */
905 ClkDis0 = DTL_MemClkDis0;
906 #elif CPU_SOCKET_TYPE == 0x11 /* AM2 */
907 ClkDis0 = DTL_MemClkDis0_AM2;
908 #elif CPU_SOCKET_TYPE == 0x12 /* S1G1 */
909 ClkDis0 = DTL_MemClkDis0_S1g1;
912 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
913 dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
914 dword &= ~(ClkDis0 >> index);
915 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
918 dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
919 dword &= ~(ClkDis0 >> index);
920 #if QRANK_DIMM_SUPPORT == 1
922 dword &= ~(ClkDis0 >> (index+2));
925 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dword);
927 if (meminfo->is_Width128) { // ChannelA+B
928 dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
929 dword &= ~(ClkDis0 >> index);
930 #if QRANK_DIMM_SUPPORT == 1
932 dword &= ~(ClkDis0 >> (index+2));
935 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
942 /* row col bank for 64 bit
958 static void set_dimm_cs_map(const struct mem_controller *ctrl,
959 struct dimm_size *sz, unsigned index,
960 struct mem_info *meminfo)
962 static const uint8_t cs_map_aaa[24] = {
963 /* (bank=2, row=13, col=9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */
978 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
981 map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
982 map &= ~(0xf << (index * 4));
983 #if QRANK_DIMM_SUPPORT == 1
985 map &= ~(0xf << ( (index + 2) * 4));
989 /* Make certain side1 of the dimm is at least 128MB */
990 if (sz->per_rank >= 27) {
992 temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ];
993 map |= temp_map << (index*4);
994 #if QRANK_DIMM_SUPPORT == 1
996 map |= temp_map << ( (index + 2) * 4);
1001 pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
1006 static long spd_set_ram_size(const struct mem_controller *ctrl,
1007 struct mem_info *meminfo)
1011 for (i = 0; i < DIMM_SOCKETS; i++) {
1012 struct dimm_size *sz = &(meminfo->sz[i]);
1013 u32 spd_device = ctrl->channel0[i];
1015 if (!(meminfo->dimm_mask & (1 << i))) {
1016 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1017 spd_device = ctrl->channel1[i];
1023 spd_get_dimm_size(spd_device, sz);
1024 if (sz->per_rank == 0) {
1025 return -1; /* Report SPD error */
1027 set_dimm_size(ctrl, sz, i, meminfo);
1028 set_dimm_cs_map (ctrl, sz, i, meminfo);
1030 return meminfo->dimm_mask;
1034 static void route_dram_accesses(const struct mem_controller *ctrl,
1035 unsigned long base_k, unsigned long limit_k)
1037 /* Route the addresses to the controller node */
1042 unsigned limit_reg, base_reg;
1045 node_id = ctrl->node_id;
1046 index = (node_id << 3);
1047 limit = (limit_k << 2);
1048 limit &= 0xffff0000;
1049 limit -= 0x00010000;
1050 limit |= ( 0 << 8) | (node_id << 0);
1051 base = (base_k << 2);
1053 base |= (0 << 8) | (1<<1) | (1<<0);
1055 limit_reg = 0x44 + index;
1056 base_reg = 0x40 + index;
1057 for (device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1);
1058 device += PCI_DEV(0, 1, 0)) {
1059 pci_write_config32(device, limit_reg, limit);
1060 pci_write_config32(device, base_reg, base);
1065 static void set_top_mem(unsigned tom_k, unsigned hole_startk)
1067 /* Error if I don't have memory */
1072 /* Report the amount of memory. */
1073 print_debug("RAM: 0x");
1074 print_debug_hex32(tom_k);
1075 print_debug(" KB\r\n");
1078 if (tom_k > (4*1024*1024)) {
1079 /* Now set top of memory */
1080 msr.lo = (tom_k & 0x003fffff) << 10;
1081 msr.hi = (tom_k & 0xffc00000) >> 22;
1082 wrmsr(TOP_MEM2, msr);
1085 /* Leave a 64M hole between TOP_MEM and TOP_MEM2
1086 * so I can see my rom chip and other I/O devices.
1088 if (tom_k >= 0x003f0000) {
1089 #if HW_MEM_HOLE_SIZEK != 0
1090 if (hole_startk != 0) {
1091 tom_k = hole_startk;
1096 msr.lo = (tom_k & 0x003fffff) << 10;
1097 msr.hi = (tom_k & 0xffc00000) >> 22;
1098 wrmsr(TOP_MEM, msr);
1101 static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, int is_Width128)
1105 static const uint8_t csbase_low_f0_shift[] = {
1106 /* 128MB */ (14 - (13-5)),
1107 /* 256MB */ (15 - (13-5)),
1108 /* 512MB */ (15 - (13-5)),
1109 /* 512MB */ (16 - (13-5)),
1110 /* 512MB */ (16 - (13-5)),
1111 /* 1GB */ (16 - (13-5)),
1112 /* 1GB */ (16 - (13-5)),
1113 /* 2GB */ (16 - (13-5)),
1114 /* 2GB */ (17 - (13-5)),
1115 /* 4GB */ (17 - (13-5)),
1116 /* 4GB */ (16 - (13-5)),
1117 /* 8GB */ (17 - (13-5)),
1120 /* cs_base_high is not changed */
1122 uint32_t csbase_inc;
1123 int chip_selects, index;
1125 unsigned common_size;
1126 unsigned common_cs_mode;
1127 uint32_t csbase, csmask;
1129 /* See if all of the memory chip selects are the same size
1130 * and if so count them.
1134 common_cs_mode = 0xff;
1135 for (index = 0; index < 8; index++) {
1140 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1142 /* Is it enabled? */
1147 size = (value >> 19) & 0x3ff;
1148 if (common_size == 0) {
1151 /* The size differed fail */
1152 if (common_size != size) {
1156 value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
1157 cs_mode =( value >> ((index>>1)*4)) & 0xf;
1158 if (common_cs_mode == 0xff) {
1159 common_cs_mode = cs_mode;
1161 /* The cs_mode differed fail */
1162 if (common_cs_mode != cs_mode) {
1167 /* Chip selects can only be interleaved when there is
1168 * more than one and their is a power of two of them.
1170 bits = log2(chip_selects);
1171 if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) {
1172 //chip_selects max = 8
1176 /* Find the bits of csbase that we need to interleave on */
1177 csbase_inc = 1 << (csbase_low_f0_shift[common_cs_mode]);
1183 /* Compute the initial values for csbase and csbask.
1184 * In csbase just set the enable bit and the base to zero.
1185 * In csmask set the mask bits for the size and page level interleave.
1188 csmask = (((common_size << bits) - 1) << 19);
1189 csmask |= 0x3fe0 & ~((csbase_inc << bits) - csbase_inc);
1190 for (index = 0; index < 8; index++) {
1193 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1194 /* Is it enabled? */
1198 pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
1199 if ((index & 1) == 0) { //only have 4 CSMASK
1200 pci_write_config32(ctrl->f2, DRAM_CSMASK + ((index>>1) << 2), csmask);
1202 csbase += csbase_inc;
1205 print_debug("Interleaved\r\n");
1207 /* Return the memory size in K */
1208 return common_size << ((27-10) + bits);
1210 static unsigned long order_chip_selects(const struct mem_controller *ctrl)
1214 /* Remember which registers we have used in the high 8 bits of tom */
1217 /* Find the largest remaining canidate */
1218 unsigned index, canidate;
1219 uint32_t csbase, csmask;
1223 for (index = 0; index < 8; index++) {
1225 value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
1227 /* Is it enabled? */
1232 /* Is it greater? */
1233 if (value <= csbase) {
1237 /* Has it already been selected */
1238 if (tom & (1 << (index + 24))) {
1241 /* I have a new canidate */
1246 /* See if I have found a new canidate */
1251 /* Remember the dimm size */
1252 size = csbase >> 19;
1254 /* Remember I have used this register */
1255 tom |= (1 << (canidate + 24));
1257 /* Recompute the cs base register value */
1258 csbase = (tom << 19) | 1;
1260 /* Increment the top of memory */
1263 /* Compute the memory mask */
1264 csmask = ((size -1) << 19);
1265 csmask |= 0x3fe0; /* For now don't optimize */
1267 /* Write the new base register */
1268 pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
1269 /* Write the new mask register */
1270 if ((canidate & 1) == 0) { //only have 4 CSMASK
1271 pci_write_config32(ctrl->f2, DRAM_CSMASK + ((canidate >> 1) << 2), csmask);
1275 /* Return the memory size in K */
1276 return (tom & ~0xff000000) << (27-10);
1279 unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
1283 /* Find the last memory address used */
1285 for (node_id = 0; node_id < max_node_id; node_id++) {
1286 uint32_t limit, base;
1288 index = node_id << 3;
1289 base = pci_read_config32(ctrl->f1, 0x40 + index);
1290 /* Only look at the limit if the base is enabled */
1291 if ((base & 3) == 3) {
1292 limit = pci_read_config32(ctrl->f1, 0x44 + index);
1293 end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
1300 static void order_dimms(const struct mem_controller *ctrl,
1301 struct mem_info *meminfo)
1303 unsigned long tom_k, base_k;
1305 if (read_option(CMOS_VSTART_interleave_chip_selects,
1306 CMOS_VLEN_interleave_chip_selects, 1) != 0) {
1307 tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
1309 print_debug("Interleaving disabled\r\n");
1314 tom_k = order_chip_selects(ctrl);
1317 /* Compute the memory base address */
1318 base_k = memory_end_k(ctrl, ctrl->node_id);
1320 route_dram_accesses(ctrl, base_k, tom_k);
1321 set_top_mem(tom_k, 0);
1325 static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
1326 struct mem_info *meminfo)
1328 print_debug("disabling dimm");
1329 print_debug_hex8(index);
1330 print_debug("\r\n");
1331 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
1332 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
1333 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
1335 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0);
1336 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0);
1337 #if QRANK_DIMM_SUPPORT == 1
1338 if (meminfo->sz[index].rank == 4) {
1339 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
1340 pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
1345 meminfo->dimm_mask &= ~(1 << index);
1346 return meminfo->dimm_mask;
1350 static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
1351 struct mem_info *meminfo)
1354 uint32_t registered;
1357 for (i = 0; (i < DIMM_SOCKETS); i++) {
1359 u32 spd_device = ctrl->channel0[i];
1360 if (!(meminfo->dimm_mask & (1 << i))) {
1361 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1362 spd_device = ctrl->channel1[i];
1367 value = spd_read_byte(spd_device, SPD_DIMM_TYPE);
1372 /* Registered dimm ? */
1374 if ((value == SPD_DIMM_TYPE_RDIMM) || (value == SPD_DIMM_TYPE_mRDIMM)) {
1375 //check SPD_MOD_ATTRIB to verify it is SPD_MOD_ATTRIB_REGADC (0x11)?
1376 registered |= (1<<i);
1380 if (is_opteron(ctrl)) {
1382 if ( registered != (meminfo->dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) {
1383 meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffed dimm
1384 // die("Mixed buffered and registered dimms not supported");
1386 //By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM
1388 die("Unbuffered Dimms not supported on Opteron");
1394 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1395 dcl &= ~DCL_UnBuffDimm;
1396 meminfo->is_registered = 1;
1398 dcl |= DCL_UnBuffDimm;
1399 meminfo->is_registered = 0;
1401 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1404 if (meminfo->is_registered) {
1405 print_debug("Registered\r\n");
1407 print_debug("Unbuffered\r\n");
1410 return meminfo->dimm_mask;
1414 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
1419 for (i = 0; i < DIMM_SOCKETS; i++) {
1422 device = ctrl->channel0[i];
1424 byte = spd_read_byte(ctrl->channel0[i], SPD_MEM_TYPE); /* Type */
1425 if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
1426 dimm_mask |= (1 << i);
1429 device = ctrl->channel1[i];
1431 byte = spd_read_byte(ctrl->channel1[i], SPD_MEM_TYPE);
1432 if (byte == SPD_MEM_TYPE_SDRAM_DDR2) {
1433 dimm_mask |= (1 << (i + DIMM_SOCKETS));
1440 static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_info *meminfo)
1444 /* SPD addresses to verify are identical */
1445 static const uint8_t addresses[] = {
1446 2, /* Type should be DDR2 SDRAM */
1447 3, /* *Row addresses */
1448 4, /* *Column addresses */
1449 5, /* *Number of DIMM Ranks */
1450 6, /* *Module Data Width*/
1451 9, /* *Cycle time at highest CAS Latency CL=X */
1452 11, /* *DIMM Conf Type */
1453 13, /* *Pri SDRAM Width */
1454 17, /* *Logical Banks */
1455 18, /* *Supported CAS Latencies */
1456 20, /* *DIMM Type Info */
1457 21, /* *SDRAM Module Attributes */
1458 23, /* *Cycle time at CAS Latnecy (CLX - 1) */
1459 26, /* *Cycle time at CAS Latnecy (CLX - 2) */
1460 27, /* *tRP Row precharge time */
1461 28, /* *Minimum Row Active to Row Active Delay (tRRD) */
1462 29, /* *tRCD RAS to CAS */
1463 30, /* *tRAS Activate to Precharge */
1464 36, /* *Write recovery time (tWR) */
1465 37, /* *Internal write to read command delay (tRDP) */
1466 38, /* *Internal read to precharge commanfd delay (tRTP) */
1467 41, /* *Extension of Byte 41 tRC and Byte 42 tRFC */
1468 41, /* *Minimum Active to Active/Auto Refresh Time(Trc) */
1469 42, /* *Minimum Auto Refresh Command Time(Trfc) */
1473 /* S1G1 and AM2 sockets are Mod64BitMux capable. */
1474 #if CPU_SOCKET_TYPE == 0x11 || CPU_SOCKET_TYPE == 0x12
1480 /* If the dimms are not in pairs do not do dual channels */
1481 if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
1482 ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1483 goto single_channel;
1485 /* If the cpu is not capable of doing dual channels don't do dual channels */
1486 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1487 if (!(nbcap & NBCAP_128Bit)) {
1488 goto single_channel;
1490 for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
1491 unsigned device0, device1;
1494 /* If I don't have a dimm skip this one */
1495 if (!(meminfo->dimm_mask & (1 << i))) {
1498 device0 = ctrl->channel0[i];
1499 device1 = ctrl->channel1[i];
1500 for (j = 0; j < ARRAY_SIZE(addresses); j++) {
1502 addr = addresses[j];
1503 value0 = spd_read_byte(device0, addr);
1507 value1 = spd_read_byte(device1, addr);
1511 if (value0 != value1) {
1512 goto single_channel;
1516 print_spew("Enabling dual channel memory\r\n");
1517 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1518 dcl &= ~DCL_BurstLength32; /* 32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses
1519 32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode */
1520 dcl |= DCL_Width128;
1521 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1522 meminfo->is_Width128 = 1;
1523 return meminfo->dimm_mask;
1526 meminfo->is_Width128 = 0;
1527 meminfo->is_64MuxMode = 0;
1530 if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
1531 ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1532 if (((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
1533 /* mux capable and single dimm in channelB */
1535 printk_spew("Enable 64MuxMode & BurstLength32\n");
1536 dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
1537 dcm |= DCM_Mode64BitMux;
1538 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
1539 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
1540 //dcl |= DCL_BurstLength32; /* 32byte mode for channelB only */
1541 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
1542 meminfo->is_64MuxMode = 1;
1544 meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
1547 } else { /* unmatched dual dimms ? */
1548 /* unmatched dual dimms not supported by meminit code. Use single channelA dimm. */
1549 meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
1550 printk_spew("Unmatched dual dimms. Use single channelA dimm.\n");
1552 return meminfo->dimm_mask;
1556 uint16_t cycle_time;
1557 uint8_t divisor; /* In 1/40 ns increments */
1562 uint8_t DcqByPassMax;
1563 uint32_t dch_memclk;
1567 static const struct mem_param speed[] = {
1569 .name = "200Mhz\r\n",
1570 .cycle_time = 0x500,
1571 .divisor = 200, // how many 1/40ns per clock
1572 .dch_memclk = DCH_MemClkFreq_200MHz, //0
1581 .name = "266Mhz\r\n",
1582 .cycle_time = 0x375,
1583 .divisor = 150, //????
1584 .dch_memclk = DCH_MemClkFreq_266MHz, //1
1592 .name = "333Mhz\r\n",
1593 .cycle_time = 0x300,
1595 .dch_memclk = DCH_MemClkFreq_333MHz, //2
1604 .name = "400Mhz\r\n",
1605 .cycle_time = 0x250,
1607 .dch_memclk = DCH_MemClkFreq_400MHz,//3
1615 .cycle_time = 0x000,
1619 static const struct mem_param *get_mem_param(unsigned min_cycle_time)
1622 const struct mem_param *param;
1623 for (param = &speed[0]; param->cycle_time ; param++) {
1624 if (min_cycle_time > (param+1)->cycle_time) {
1628 if (!param->cycle_time) {
1629 die("min_cycle_time to low");
1631 print_spew(param->name);
1632 #ifdef DRAM_MIN_CYCLE_TIME
1633 print_debug(param->name);
1638 static uint8_t get_exact_divisor(int i, uint8_t divisor)
1640 //input divisor could be 200(200), 150(266), 120(333), 100 (400)
1641 static const uint8_t dv_a[] = {
1642 /* 200 266 333 400 */
1643 /*4 */ 250, 250, 250, 250,
1644 /*5 */ 200, 200, 200, 100,
1645 /*6 */ 200, 166, 166, 100,
1646 /*7 */ 200, 171, 142, 100,
1648 /*8 */ 200, 150, 125, 100,
1649 /*9 */ 200, 156, 133, 100,
1650 /*10*/ 200, 160, 120, 100,
1651 /*11*/ 200, 163, 127, 100,
1653 /*12*/ 200, 150, 133, 100,
1654 /*13*/ 200, 153, 123, 100,
1655 /*14*/ 200, 157, 128, 100,
1656 /*15*/ 200, 160, 120, 100,
1663 /* Check for FID control support */
1664 struct cpuid_result cpuid1;
1665 cpuid1 = cpuid(0x8000007);
1666 if( cpuid1.edx & 0x02 ) {
1667 /* Use current FID */
1669 msr = rdmsr(0xc0010042);
1670 fid_cur = msr.lo & 0x3f;
1674 /* Use startup FID */
1676 msr = rdmsr(0xc0010015);
1677 fid_start = (msr.lo & (0x3f << 24));
1679 index = fid_start>>25;
1682 if (index>12) return divisor;
1684 if (i>3) return divisor;
1686 return dv_a[index * 4+i];
1691 struct spd_set_memclk_result {
1692 const struct mem_param *param;
1697 static unsigned convert_to_linear(unsigned value)
1699 static const unsigned fraction[] = { 0x25, 0x33, 0x66, 0x75 };
1702 /* We need to convert value to more readable */
1703 if ((value & 0xf) < 10) { //no .25, .33, .66, .75
1706 valuex = ((value & 0xf0) << 4) | fraction [(value & 0xf)-10];
1712 static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, struct mem_info *meminfo)
1714 /* Compute the minimum cycle time for these dimms */
1715 struct spd_set_memclk_result result;
1716 unsigned min_cycle_time, min_latency, bios_cycle_time;
1720 static const uint8_t latency_indicies[] = { 25, 23, 9 };
1722 static const uint16_t min_cycle_times[] = { // use full speed to compare
1723 [NBCAP_MEMCLK_NOLIMIT] = 0x250, /*2.5ns */
1724 [NBCAP_MEMCLK_333MHZ] = 0x300, /* 3.0ns */
1725 [NBCAP_MEMCLK_266MHZ] = 0x375, /* 3.75ns */
1726 [NBCAP_MEMCLK_200MHZ] = 0x500, /* 5.0s */
1730 value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
1731 min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
1732 bios_cycle_time = min_cycle_times[
1733 read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
1734 if (bios_cycle_time > min_cycle_time) {
1735 min_cycle_time = bios_cycle_time;
1739 print_tx("1 min_cycle_time:", min_cycle_time);
1741 /* Compute the least latency with the fastest clock supported
1742 * by both the memory controller and the dimms.
1744 for (i = 0; i < DIMM_SOCKETS; i++) {
1745 int new_cycle_time, new_latency;
1749 u32 spd_device = ctrl->channel0[i];
1751 print_tx("1.1 dimm_mask:", meminfo->dimm_mask);
1752 if (!(meminfo->dimm_mask & (1 << i))) {
1753 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1754 spd_device = ctrl->channel1[i];
1760 /* First find the supported CAS latencies
1761 * Byte 18 for DDR SDRAM is interpreted:
1762 * bit 3 == CAS Latency = 3
1763 * bit 4 == CAS Latency = 4
1764 * bit 5 == CAS Latency = 5
1765 * bit 6 == CAS Latency = 6
1767 new_cycle_time = 0x500;
1770 latencies = spd_read_byte(spd_device, SPD_CAS_LAT);
1771 if (latencies <= 0) continue;
1774 print_tx("\tlatencies:", latencies);
1775 /* Compute the lowest cas latency supported */
1776 latency = log2(latencies) - 2;
1778 /* Loop through and find a fast clock with a low latency */
1779 for (index = 0; index < 3; index++, latency++) {
1781 if ((latency < 3) || (latency > 6) ||
1782 (!(latencies & (1 << latency)))) {
1785 value = spd_read_byte(spd_device, latency_indicies[index]);
1790 print_tx("\tindex:", index);
1791 print_tx("\t\tlatency:", latency);
1792 print_tx("\t\tvalue1:", value);
1794 value = convert_to_linear(value);
1796 print_tx("\t\tvalue2:", value);
1798 /* Only increase the latency if we decreas the clock */
1799 if (value >= min_cycle_time ) {
1800 if (value < new_cycle_time) {
1801 new_cycle_time = value;
1802 new_latency = latency;
1803 } else if (value == new_cycle_time) {
1804 if (new_latency > latency) {
1805 new_latency = latency;
1809 print_tx("\t\tnew_cycle_time:", new_cycle_time);
1810 print_tx("\t\tnew_latency:", new_latency);
1814 if (new_latency > 6){
1818 /* Does min_latency need to be increased? */
1819 if (new_cycle_time > min_cycle_time) {
1820 min_cycle_time = new_cycle_time;
1823 /* Does min_cycle_time need to be increased? */
1824 if (new_latency > min_latency) {
1825 min_latency = new_latency;
1828 print_tx("2 min_cycle_time:", min_cycle_time);
1829 print_tx("2 min_latency:", min_latency);
1831 /* Make a second pass through the dimms and disable
1832 * any that cannot support the selected memclk and cas latency.
1835 print_tx("3 min_cycle_time:", min_cycle_time);
1836 print_tx("3 min_latency:", min_latency);
1838 for (i = 0; (i < DIMM_SOCKETS); i++) {
1843 u32 spd_device = ctrl->channel0[i];
1845 if (!(meminfo->dimm_mask & (1 << i))) {
1846 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
1847 spd_device = ctrl->channel1[i];
1853 latencies = spd_read_byte(spd_device, SPD_CAS_LAT);
1854 if (latencies < 0) goto hw_error;
1855 if (latencies == 0) {
1859 /* Compute the lowest cas latency supported */
1860 latency = log2(latencies) -2;
1862 /* Walk through searching for the selected latency */
1863 for (index = 0; index < 3; index++, latency++) {
1864 if (!(latencies & (1 << latency))) {
1867 if (latency == min_latency)
1870 /* If I can't find the latency or my index is bad error */
1871 if ((latency != min_latency) || (index >= 3)) {
1875 /* Read the min_cycle_time for this latency */
1876 value = spd_read_byte(spd_device, latency_indicies[index]);
1877 if (value < 0) goto hw_error;
1879 value = convert_to_linear(value);
1880 /* All is good if the selected clock speed
1881 * is what I need or slower.
1883 if (value <= min_cycle_time) {
1886 /* Otherwise I have an error, disable the dimm */
1888 meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo);
1891 print_tx("4 min_cycle_time:", min_cycle_time);
1893 /* Now that I know the minimum cycle time lookup the memory parameters */
1894 result.param = get_mem_param(min_cycle_time);
1896 /* Update DRAM Config High with our selected memory speed */
1897 value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
1898 value &= ~(DCH_MemClkFreq_MASK << DCH_MemClkFreq_SHIFT);
1900 value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT;
1901 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
1903 print_debug(result.param->name);
1905 /* Update DRAM Timing Low with our selected cas latency */
1906 value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1907 value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
1908 value |= (min_latency - DTL_TCL_BASE) << DTL_TCL_SHIFT;
1909 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
1911 result.dimm_mask = meminfo->dimm_mask;
1914 result.param = (const struct mem_param *)0;
1915 result.dimm_mask = -1;
1919 static unsigned convert_to_1_4(unsigned value)
1921 static const uint8_t fraction[] = { 0, 1, 2, 2, 3, 3, 0 };
1924 /* We need to convert value to more readable */
1925 valuex = fraction [value & 0x7];
1928 static int update_dimm_Trc(const struct mem_controller *ctrl,
1929 const struct mem_param *param,
1930 int i, long dimm_mask)
1932 unsigned clocks, old_clocks;
1936 u32 spd_device = ctrl->channel0[i];
1938 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
1939 spd_device = ctrl->channel1[i];
1942 value = spd_read_byte(spd_device, SPD_TRC);
1943 if (value < 0) return -1;
1945 value2 = spd_read_byte(spd_device, SPD_TRC -1);
1947 value += convert_to_1_4(value2>>4);
1951 clocks = (value + param->divisor - 1)/param->divisor;
1953 if (clocks < DTL_TRC_MIN) {
1954 clocks = DTL_TRC_MIN;
1956 if (clocks > DTL_TRC_MAX) {
1960 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
1961 old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
1962 if (old_clocks >= clocks) { //?? someone did it
1963 // clocks = old_clocks;
1966 dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
1967 dtl |= ((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
1968 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
1972 static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i, struct mem_info *meminfo)
1974 unsigned clocks, old_clocks;
1978 u32 spd_device = ctrl->channel0[i];
1980 if (!(meminfo->dimm_mask & (1 << i)) && (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
1981 spd_device = ctrl->channel1[i];
1982 ch_b = 2; /* offset to channelB trfc setting */
1985 //get the cs_size --> logic dimm size
1986 value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
1991 value = 6 - log2(value); //4-->4, 8-->3, 16-->2
1993 clocks = meminfo->sz[i].per_rank - 27 + 2 - value;
1995 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
1997 old_clocks = ((dth >> (DTH_TRFC0_SHIFT + ((i + ch_b) * 3))) & DTH_TRFC_MASK);
1999 if (old_clocks >= clocks) { // some one did it?
2002 dth &= ~(DTH_TRFC_MASK << (DTH_TRFC0_SHIFT + ((i + ch_b) * 3)));
2003 dth |= clocks << (DTH_TRFC0_SHIFT + ((i + ch_b) * 3));
2004 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2008 static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask,
2010 unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX )
2012 unsigned clocks, old_clocks;
2015 u32 spd_device = ctrl->channel0[i];
2017 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2018 spd_device = ctrl->channel1[i];
2021 value = spd_read_byte(spd_device, SPD_TT); //already in 1/4 ns
2022 if (value < 0) return -1;
2024 clocks = (value + param->divisor -1)/param->divisor;
2025 if (clocks < TT_MIN) {
2029 if (clocks > TT_MAX) {
2033 dtl = pci_read_config32(ctrl->f2, TT_REG);
2035 old_clocks = ((dtl >> TT_SHIFT) & TT_MASK) + TT_BASE;
2036 if (old_clocks >= clocks) { //some one did it?
2037 // clocks = old_clocks;
2040 dtl &= ~(TT_MASK << TT_SHIFT);
2041 dtl |= ((clocks - TT_BASE) << TT_SHIFT);
2042 pci_write_config32(ctrl->f2, TT_REG, dtl);
2047 static int update_dimm_Trcd(const struct mem_controller *ctrl,
2048 const struct mem_param *param, int i, long dimm_mask)
2050 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRCD, DTL_TRCD_SHIFT, DTL_TRCD_MASK, DTL_TRCD_BASE, DTL_TRCD_MIN, DTL_TRCD_MAX);
2053 static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2055 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRRD, DTL_TRRD_SHIFT, DTL_TRRD_MASK, DTL_TRRD_BASE, DTL_TRRD_MIN, DTL_TRRD_MAX);
2058 static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2060 unsigned clocks, old_clocks;
2063 u32 spd_device = ctrl->channel0[i];
2065 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2066 spd_device = ctrl->channel1[i];
2069 value = spd_read_byte(spd_device, SPD_TRAS); //in 1 ns
2070 if (value < 0) return -1;
2071 print_tx("update_dimm_Tras: 0 value=", value);
2073 value <<= 2; //convert it to in 1/4ns
2076 print_tx("update_dimm_Tras: 1 value=", value);
2078 clocks = (value + param->divisor - 1)/param->divisor;
2079 print_tx("update_dimm_Tras: divisor=", param->divisor);
2080 print_tx("update_dimm_Tras: clocks=", clocks);
2081 if (clocks < DTL_TRAS_MIN) {
2082 clocks = DTL_TRAS_MIN;
2085 if (clocks > DTL_TRAS_MAX) {
2089 dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
2090 old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
2091 if (old_clocks >= clocks) { // someone did it?
2095 dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
2096 dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
2097 pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
2101 static int update_dimm_Trp(const struct mem_controller *ctrl,
2102 const struct mem_param *param, int i, long dimm_mask)
2104 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRP, DTL_TRP_SHIFT, DTL_TRP_MASK, DTL_TRP_BASE, DTL_TRP_MIN, DTL_TRP_MAX);
2108 static int update_dimm_Trtp(const struct mem_controller *ctrl,
2109 const struct mem_param *param, int i, struct mem_info *meminfo)
2111 /* need to figure if it is 32 byte burst or 64 bytes burst */
2113 if (!meminfo->is_Width128) {
2115 dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2116 if ((dword & DCL_BurstLength32)) offset = 0;
2118 return update_dimm_TT_1_4(ctrl, param, i, meminfo->dimm_mask, DRAM_TIMING_LOW, SPD_TRTP, DTL_TRTP_SHIFT, DTL_TRTP_MASK, DTL_TRTP_BASE+offset, DTL_TRTP_MIN+offset, DTL_TRTP_MAX+offset);
2122 static int update_dimm_Twr(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
2124 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TWR, DTL_TWR_SHIFT, DTL_TWR_MASK, DTL_TWR_BASE, DTL_TWR_MIN, DTL_TWR_MAX);
2128 static int update_dimm_Tref(const struct mem_controller *ctrl,
2129 const struct mem_param *param, int i, long dimm_mask)
2131 uint32_t dth, dth_old;
2133 u32 spd_device = ctrl->channel0[i];
2135 if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
2136 spd_device = ctrl->channel1[i];
2139 value = spd_read_byte(spd_device, SPD_TREF); // 0: 15.625us, 1: 3.9us 2: 7.8 us....
2140 if (value < 0) return -1;
2148 dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
2151 dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
2152 dth |= (value << DTH_TREF_SHIFT);
2153 if (dth_old != dth) {
2154 pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
2160 static void set_4RankRDimm(const struct mem_controller *ctrl,
2161 const struct mem_param *param, struct mem_info *meminfo)
2163 #if QRANK_DIMM_SUPPRT == 1
2168 if (!(meminfo->is_registered)) return;
2172 for (i = 0; i < DIMM_SOCKETS; i++) {
2173 if (!(dimm_mask & (1 << i))) {
2177 if (meminfo->sz.rank == 4) {
2185 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2186 dch |= DCH_FourRankRDimm;
2187 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2193 static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
2194 struct mem_info *meminfo)
2200 uint32_t mask_single_rank;
2201 uint32_t mask_page_1k;
2203 #if QRANK_DIMM_SUPPORT == 1
2207 long dimm_mask = meminfo->dimm_mask;
2212 mask_single_rank = 0;
2215 for (i = 0; i < DIMM_SOCKETS; i++) {
2216 u32 spd_device = ctrl->channel0[i];
2217 if (!(dimm_mask & (1 << i))) {
2218 if (dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
2219 spd_device = ctrl->channel1[i];
2225 if (meminfo->sz[i].rank == 1) {
2226 mask_single_rank |= 1<<i;
2229 if (meminfo->sz[i].col==10) {
2230 mask_page_1k |= 1<<i;
2234 value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
2236 #if QRANK_DIMM_SUPPORT == 1
2237 rank = meminfo->sz[i].rank;
2242 #if QRANK_DIMM_SUPPORT == 1
2244 mask_x4 |= 1<<(i+2);
2247 } else if (value==16) {
2249 #if QRANK_DIMM_SUPPORT == 1
2251 mask_x16 |= 1<<(i+2);
2258 meminfo->x4_mask= mask_x4;
2259 meminfo->x16_mask = mask_x16;
2261 meminfo->single_rank_mask = mask_single_rank;
2262 meminfo->page_1k_mask = mask_page_1k;
2269 static void set_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2272 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2273 dcl &= ~(DCL_X4Dimm_MASK<<DCL_X4Dimm_SHIFT);
2274 dcl |= ((meminfo->x4_mask) & 0xf) << (DCL_X4Dimm_SHIFT);
2275 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2279 static int count_ones(uint32_t dimm_mask)
2284 for (index = 0; index < (2 * DIMM_SOCKETS); index++, dimm_mask >>= 1) {
2285 if (dimm_mask & 1) {
2293 static void set_DramTerm(const struct mem_controller *ctrl,
2294 const struct mem_param *param, struct mem_info *meminfo)
2300 if (param->divisor == 100) { //DDR2 800
2301 if (meminfo->is_Width128) {
2302 if (count_ones(meminfo->dimm_mask & 0x0f)==2) {
2310 #if DIMM_SUPPORT == 0x0204
2311 odt = 0x2; /* 150 ohms */
2314 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2315 dcl &= ~(DCL_DramTerm_MASK<<DCL_DramTerm_SHIFT);
2316 dcl |= (odt & DCL_DramTerm_MASK) << (DCL_DramTerm_SHIFT);
2317 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2321 static void set_ecc(const struct mem_controller *ctrl,
2322 const struct mem_param *param, struct mem_info *meminfo)
2327 uint32_t dcl, nbcap;
2328 nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
2329 dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
2330 dcl &= ~DCL_DimmEccEn;
2331 if (nbcap & NBCAP_ECC) {
2332 dcl |= DCL_DimmEccEn;
2334 if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
2335 dcl &= ~DCL_DimmEccEn;
2337 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2339 meminfo->is_ecc = 1;
2340 if (!(dcl & DCL_DimmEccEn)) {
2341 meminfo->is_ecc = 0;
2342 return; // already disabled the ECC, so don't need to read SPD any more
2345 for (i = 0; i < DIMM_SOCKETS; i++) {
2346 u32 spd_device = ctrl->channel0[i];
2347 if (!(meminfo->dimm_mask & (1 << i))) {
2348 if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
2349 spd_device = ctrl->channel1[i];
2350 printk_debug("set_ecc spd_device: 0x%x\n", spd_device);
2356 value = spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONF_TYPE);
2358 if (!(value & SPD_DIMM_CONF_TYPE_ECC)) {
2359 dcl &= ~DCL_DimmEccEn;
2360 pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
2361 meminfo->is_ecc = 0;
2369 static int update_dimm_Twtr(const struct mem_controller *ctrl,
2370 const struct mem_param *param, int i, long dimm_mask)
2372 return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_HIGH, SPD_TWTR, DTH_TWTR_SHIFT, DTH_TWTR_MASK, DTH_TWTR_BASE, DTH_TWTR_MIN, DTH_TWTR_MAX);
2375 static void set_TT(const struct mem_controller *ctrl,
2376 const struct mem_param *param, unsigned TT_REG, unsigned TT_SHIFT,
2377 unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX,
2378 unsigned val, const char *str)
2382 if ((val < TT_MIN) || (val > TT_MAX)) {
2384 die(" Unknown\r\n");
2387 reg = pci_read_config32(ctrl->f2, TT_REG);
2388 reg &= ~(TT_MASK << TT_SHIFT);
2389 reg |= ((val - TT_BASE) << TT_SHIFT);
2390 pci_write_config32(ctrl->f2, TT_REG, reg);
2395 static void set_TrwtTO(const struct mem_controller *ctrl,
2396 const struct mem_param *param)
2398 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRWTTO_SHIFT, DTH_TRWTTO_MASK,DTH_TRWTTO_BASE, DTH_TRWTTO_MIN, DTH_TRWTTO_MAX, param->TrwtTO, "TrwtTO");
2402 static void set_Twrrd(const struct mem_controller *ctrl, const struct mem_param *param)
2404 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRRD_SHIFT, DTH_TWRRD_MASK,DTH_TWRRD_BASE, DTH_TWRRD_MIN, DTH_TWRRD_MAX, param->Twrrd, "Twrrd");
2408 static void set_Twrwr(const struct mem_controller *ctrl, const struct mem_param *param)
2410 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRWR_SHIFT, DTH_TWRWR_MASK,DTH_TWRWR_BASE, DTH_TWRWR_MIN, DTH_TWRWR_MAX, param->Twrwr, "Twrwr");
2414 static void set_Trdrd(const struct mem_controller *ctrl, const struct mem_param *param)
2416 set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRDRD_SHIFT, DTH_TRDRD_MASK,DTH_TRDRD_BASE, DTH_TRDRD_MIN, DTH_TRDRD_MAX, param->Trdrd, "Trdrd");
2420 static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem_param *param)
2422 set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS
2426 static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
2428 static const uint8_t faw_1k[] = {8, 10, 13, 14};
2429 static const uint8_t faw_2k[] = {10, 14, 17, 18};
2430 unsigned memclkfreq_index;
2434 memclkfreq_index = param->dch_memclk;
2436 if (meminfo->page_1k_mask != 0) { //1k page
2437 faw = faw_1k[memclkfreq_index];
2439 faw = faw_2k[memclkfreq_index];
2442 set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_FourActWindow_SHIFT, DCH_FourActWindow_MASK, DCH_FourActWindow_BASE, DCH_FourActWindow_MIN, DCH_FourActWindow_MAX, faw, "FourActWindow");
2447 static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
2453 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2454 dch &= ~(DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT);
2456 //FIXME: We need to use Max of DqsRcvEnDelay + 6ns here: After trainning and get that from index reg 0x10, 0x13, 0x16, 0x19, 0x30, 0x33, 0x36, 0x39
2460 dch |= ((async_lat - DCH_MaxAsyncLat_BASE) << DCH_MaxAsyncLat_SHIFT);
2461 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2465 static void set_SlowAccessMode(const struct mem_controller *ctrl)
2469 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2473 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2478 DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20
2479 DRAM_ADDR_TIMING_CTRL 04, 0x24
2481 static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *meminfo)
2485 unsigned SlowAccessMode = 0;
2487 long dimm_mask = meminfo->dimm_mask & 0x0f;
2489 #if DIMM_SUPPORT==0x0104 /* DDR2 and REG */
2492 dwordx = 0x002f0000;
2493 switch (meminfo->memclk_set) {
2494 case DCH_MemClkFreq_266MHz:
2495 if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
2496 dwordx = 0x002f2700;
2499 case DCH_MemClkFreq_333MHz:
2500 if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
2501 if ((meminfo->single_rank_mask & 0x03)!=0x03) { //any double rank there?
2502 dwordx = 0x002f2f00;
2506 case DCH_MemClkFreq_400MHz:
2507 dwordx = 0x002f3300;
2513 #if DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */
2515 dwordx = 0x002F2F00;
2517 switch (meminfo->memclk_set) {
2518 case DCH_MemClkFreq_200MHz: /* nothing to be set here */
2520 case DCH_MemClkFreq_266MHz:
2521 if ((meminfo->single_rank_mask == 0)
2522 && (meminfo->x4_mask == 0) && (meminfo->x16_mask))
2523 dwordx = 0x002C2C00; /* Double rank x8 */
2524 /* else SRx16, SRx8, DRx16 == 0x002F2F00 */
2526 case DCH_MemClkFreq_333MHz:
2527 if ((meminfo->single_rank_mask == 1)
2528 && (meminfo->x16_mask == 1)) /* SR x16 */
2529 dwordx = 0x00272700;
2530 else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
2531 && (meminfo->single_rank_mask == 0)) { /* DR x8 */
2533 dwordx = 0x00002800;
2534 } else { /* SR x8, DR x16 */
2535 dwordx = 0x002A2A00;
2538 case DCH_MemClkFreq_400MHz:
2539 if ((meminfo->single_rank_mask == 1)
2540 && (meminfo->x16_mask == 1)) /* SR x16 */
2541 dwordx = 0x00292900;
2542 else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
2543 && (meminfo->single_rank_mask == 0)) { /* DR x8 */
2545 dwordx = 0x00002A00;
2546 } else { /* SR x8, DR x16 */
2547 dwordx = 0x002A2A00;
2553 #if DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */
2554 /* for UNBUF DIMM */
2556 dwordx = 0x002f2f00;
2557 switch (meminfo->memclk_set) {
2558 case DCH_MemClkFreq_200MHz:
2559 if (dimm_mask == 0x03) {
2564 case DCH_MemClkFreq_266MHz:
2565 if (dimm_mask == 0x03) {
2568 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
2569 switch (meminfo->single_rank_mask) {
2571 dwordx = 0x00002f00; //x8 single Rank
2574 dwordx = 0x00342f00; //x8 double Rank
2577 dwordx = 0x00372f00; //x8 single Rank and double Rank mixed
2579 } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
2580 dwordx = 0x00382f00; //x8 Double Rank and x16 single Rank mixed
2581 } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
2582 dwordx = 0x00382f00; //x16 single Rank and x8 double Rank mixed
2586 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank
2587 dwordx = 0x002f2f00;
2589 dwordx = 0x002b2f00;
2593 case DCH_MemClkFreq_333MHz:
2594 dwordx = 0x00202220;
2595 if (dimm_mask == 0x03) {
2598 if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
2599 switch (meminfo->single_rank_mask) {
2601 dwordx = 0x00302220; //x8 single Rank
2604 dwordx = 0x002b2220; //x8 double Rank
2607 dwordx = 0x002a2220; //x8 single Rank and double Rank mixed
2609 } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
2610 dwordx = 0x002c2220; //x8 Double Rank and x16 single Rank mixed
2611 } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
2612 dwordx = 0x002c2220; //x16 single Rank and x8 double Rank mixed
2616 case DCH_MemClkFreq_400MHz:
2617 dwordx = 0x00202520;
2619 if (dimm_mask == 0x03) {
2627 print_raminit("\tdimm_mask = ", meminfo->dimm_mask);
2628 print_raminit("\tx4_mask = ", meminfo->x4_mask);
2629 print_raminit("\tx16_mask = ", meminfo->x16_mask);
2630 print_raminit("\tsingle_rank_mask = ", meminfo->single_rank_mask);
2631 print_raminit("\tODC = ", dword);
2632 print_raminit("\tAddr Timing= ", dwordx);
2635 #if (DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
2636 if (SlowAccessMode) {
2637 set_SlowAccessMode(ctrl);
2641 if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
2642 /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */
2643 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword);
2645 /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */
2646 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx);
2648 /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */
2649 pci_write_config32_index_wait(ctrl->f2, 0x98, 0, dword);
2650 if (meminfo->is_Width128) {
2651 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword);
2654 /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */
2655 pci_write_config32_index_wait(ctrl->f2, 0x98, 4, dwordx);
2656 if (meminfo->is_Width128) {
2657 pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx);
2663 static void set_RDqsEn(const struct mem_controller *ctrl,
2664 const struct mem_param *param, struct mem_info *meminfo)
2666 #if CPU_SOCKET_TYPE==0x10
2667 //only need to set for reg and x8
2670 dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
2673 if ((!meminfo->x4_mask) && (!meminfo->x16_mask)) {
2677 pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
2682 static void set_idle_cycle_limit(const struct mem_controller *ctrl,
2683 const struct mem_param *param)
2686 /* AMD says to Hardcode this */
2687 dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
2688 dcm &= ~(DCM_ILD_lmt_MASK << DCM_ILD_lmt_SHIFT);
2689 dcm |= DCM_ILD_lmt_16 << DCM_ILD_lmt_SHIFT;
2691 pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
2695 static void set_RdWrQByp(const struct mem_controller *ctrl,
2696 const struct mem_param *param)
2698 set_TT(ctrl, param, DRAM_CTRL_MISC, DCM_RdWrQByp_SHIFT, DCM_RdWrQByp_MASK,0, 0, 3, 2, "RdWrQByp");
2702 static long spd_set_dram_timing(const struct mem_controller *ctrl,
2703 const struct mem_param *param,
2704 struct mem_info *meminfo)
2708 for (i = 0; i < DIMM_SOCKETS; i++) {
2710 if (!(meminfo->dimm_mask & (1 << i)) &&
2711 !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) ) {
2714 print_tx("spd_set_dram_timing dimm socket: ", i);
2715 /* DRAM Timing Low Register */
2716 print_t("\ttrc\r\n");
2717 if ((rc = update_dimm_Trc (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2719 print_t("\ttrcd\r\n");
2720 if ((rc = update_dimm_Trcd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2722 print_t("\ttrrd\r\n");
2723 if ((rc = update_dimm_Trrd(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2725 print_t("\ttras\r\n");
2726 if ((rc = update_dimm_Tras(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2728 print_t("\ttrp\r\n");
2729 if ((rc = update_dimm_Trp (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2731 print_t("\ttrtp\r\n");
2732 if ((rc = update_dimm_Trtp(ctrl, param, i, meminfo)) <= 0) goto dimm_err;
2734 print_t("\ttwr\r\n");
2735 if ((rc = update_dimm_Twr (ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2737 /* DRAM Timing High Register */
2738 print_t("\ttref\r\n");
2739 if ((rc = update_dimm_Tref(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2741 print_t("\ttwtr\r\n");
2742 if ((rc = update_dimm_Twtr(ctrl, param, i, meminfo->dimm_mask)) <= 0) goto dimm_err;
2744 print_t("\ttrfc\r\n");
2745 if ((rc = update_dimm_Trfc(ctrl, param, i, meminfo)) <= 0) goto dimm_err;
2747 /* DRAM Config Low */
2751 printk_debug("spd_set_dram_timing dimm_err!\n");
2755 meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo);
2758 get_extra_dimm_mask(ctrl, meminfo); // will be used by RDqsEn and dimm_x4
2759 /* DRAM Timing Low Register */
2761 /* DRAM Timing High Register */
2762 set_TrwtTO(ctrl, param);
2763 set_Twrrd (ctrl, param);
2764 set_Twrwr (ctrl, param);
2765 set_Trdrd (ctrl, param);
2767 set_4RankRDimm(ctrl, param, meminfo);
2769 /* DRAM Config High */
2770 set_Tfaw(ctrl, param, meminfo);
2771 set_DcqBypassMax(ctrl, param);
2772 set_max_async_latency(ctrl, param);
2773 set_RDqsEn(ctrl, param, meminfo);
2775 /* DRAM Config Low */
2776 set_ecc(ctrl, param, meminfo);
2777 set_dimm_x4(ctrl, param, meminfo);
2778 set_DramTerm(ctrl, param, meminfo);
2780 /* DRAM Control Misc */
2781 set_idle_cycle_limit(ctrl, param);
2782 set_RdWrQByp(ctrl, param);
2784 return meminfo->dimm_mask;
2787 static void sdram_set_spd_registers(const struct mem_controller *ctrl,
2788 struct sys_info *sysinfo)
2790 struct spd_set_memclk_result result;
2791 const struct mem_param *param;
2792 struct mem_param paramx;
2793 struct mem_info *meminfo;
2795 if (!sysinfo->ctrl_present[ctrl->node_id]) {
2799 meminfo = &sysinfo->meminfo[ctrl->node_id];
2801 print_debug_addr("sdram_set_spd_registers: paramx :", ¶mx);
2803 activate_spd_rom(ctrl);
2804 meminfo->dimm_mask = spd_detect_dimms(ctrl);
2806 print_tx("sdram_set_spd_registers: dimm_mask=0x%x\n", meminfo->dimm_mask);
2808 if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1)))
2810 print_debug("No memory for this cpu\r\n");
2813 meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo);
2814 print_tx("spd_enable_2channels: dimm_mask=0x%x\n", meminfo->dimm_mask);
2815 if (meminfo->dimm_mask == -1)
2818 meminfo->dimm_mask = spd_set_ram_size(ctrl, meminfo);
2819 print_tx("spd_set_ram_size: dimm_mask=0x%x\n", meminfo->dimm_mask);
2820 if (meminfo->dimm_mask == -1)
2823 meminfo->dimm_mask = spd_handle_unbuffered_dimms(ctrl, meminfo);
2824 print_tx("spd_handle_unbuffered_dimms: dimm_mask=0x%x\n", meminfo->dimm_mask);
2825 if (meminfo->dimm_mask == -1)
2828 result = spd_set_memclk(ctrl, meminfo);
2829 param = result.param;
2830 meminfo->dimm_mask = result.dimm_mask;
2831 print_tx("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask);
2832 if (meminfo->dimm_mask == -1)
2835 //store memclk set to sysinfo, incase we need rebuilt param again
2836 meminfo->memclk_set = param->dch_memclk;
2838 memcpy(¶mx, param, sizeof(paramx));
2840 paramx.divisor = get_exact_divisor(param->dch_memclk, paramx.divisor);
2842 meminfo->dimm_mask = spd_set_dram_timing(ctrl, ¶mx, meminfo);
2843 print_tx("spd_set_dram_timing: dimm_mask=0x%x\n", meminfo->dimm_mask);
2844 if (meminfo->dimm_mask == -1)
2847 order_dimms(ctrl, meminfo);
2851 /* Unrecoverable error reading SPD data */
2852 die("Unrecoverable error reading SPD data. No qualified DIMMs?");
2856 #define TIMEOUT_LOOPS 300000
2858 #include "raminit_f_dqs.c"
2860 #if HW_MEM_HOLE_SIZEK != 0
2861 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i)
2864 uint32_t carry_over;
2866 uint32_t base, limit;
2871 carry_over = (4*1024*1024) - hole_startk;
2873 for (ii=controllers - 1;ii>i;ii--) {
2874 base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
2875 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2878 limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
2879 limit += (carry_over << 2 );
2880 base += (carry_over << 2 );
2881 for (j = 0; j < controllers; j++) {
2882 pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit);
2883 pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base );
2886 limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
2887 limit += (carry_over << 2);
2888 for (j = 0; j < controllers; j++) {
2889 pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit);
2892 base = pci_read_config32(dev, 0x40 + (i << 3));
2893 basek = (base & 0xffff0000) >> 2;
2894 if (basek == hole_startk) {
2895 //don't need set memhole here, because hole off set will be 0, overflow
2896 //so need to change base reg instead, new basek will be 4*1024*1024
2898 base |= (4*1024*1024)<<2;
2899 for (j = 0; j < controllers; j++) {
2900 pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
2903 hoist = /* hole start address */
2904 ((hole_startk << 10) & 0xff000000) +
2905 /* hole address to memory controller address */
2906 (((basek + carry_over) >> 6) & 0x0000ff00) +
2909 pci_write_config32(dev, 0xf0, hoist);
2915 static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
2918 uint32_t hole_startk;
2921 hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
2923 #if HW_MEM_HOLE_SIZE_AUTO_INC == 1
2924 /* We need to double check if the hole_startk is valid, if it is equal
2925 to basek, we need to decrease it some */
2927 for (i=0; i<controllers; i++) {
2930 base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
2931 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
2934 base_k = (base & 0xffff0000) >> 2;
2935 if (base_k == hole_startk) {
2936 /* decrease mem hole startk to make sure it is
2937 on middle of previous node */
2938 hole_startk -= (base_k - basek_pri) >> 1;
2939 break; //only one hole
2944 /* find node index that need do set hole */
2945 for (i=0; i < controllers; i++) {
2946 uint32_t base, limit;
2947 unsigned base_k, limit_k;
2948 base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
2949 if ((base & ((1 << 1) | (1 << 0))) != ((1 << 1) | (1 << 0))) {
2952 limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
2953 base_k = (base & 0xffff0000) >> 2;
2954 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
2955 if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
2957 hoist_memory(controllers, ctrl, hole_startk, i);
2958 end_k = memory_end_k(ctrl, controllers);
2959 set_top_mem(end_k, hole_startk);
2960 break; //only one hole
2968 static void sdram_enable(int controllers, const struct mem_controller *ctrl,
2969 struct sys_info *sysinfo)
2973 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
2974 unsigned cpu_f0_f1[8];
2975 /* FIXME: How about 32 node machine later? */
2978 print_debug_addr("sdram_enable: tsc0[8]: ", &tsc0[0]);
2982 /* Error if I don't have memory */
2983 if (memory_end_k(ctrl, controllers) == 0) {
2984 die("No memory\r\n");
2987 /* Before enabling memory start the memory clocks */
2988 for (i = 0; i < controllers; i++) {
2990 if (!sysinfo->ctrl_present[ i ])
2992 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
2994 /* if no memory installed, disabled the interface */
2995 if (sysinfo->meminfo[i].dimm_mask==0x00){
2996 dch |= DCH_DisDramInterface;
2997 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
3000 dch |= DCH_MemClkFreqVal;
3001 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
3002 /* address timing and Output driver comp Control */
3003 set_misc_timing(ctrl+i, sysinfo->meminfo+i );
3007 /* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */
3008 memreset(controllers, ctrl);
3010 print_debug("prepare to InitDram:");
3011 for (i=0; i<10; i++) {
3012 print_debug_hex32(i);
3013 print_debug("\b\b\b\b\b\b\b\b");
3015 print_debug("\r\n");
3018 for (i = 0; i < controllers; i++) {
3020 if (!sysinfo->ctrl_present[ i ])
3022 /* Skip everything if I don't have any memory on this controller */
3023 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
3024 if (!(dch & DCH_MemClkFreqVal)) {
3029 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
3030 if (dcl & DCL_DimmEccEn) {
3032 print_spew("ECC enabled\r\n");
3033 mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
3035 if (dcl & DCL_Width128) {
3036 mnc |= MNC_CHIPKILL_EN;
3038 pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
3041 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3042 cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i);
3044 //Rev F0/F1 workaround
3046 /* Set the DqsRcvEnTrain bit */
3047 dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
3048 dword |= DC_DqsRcvEnTrain;
3049 pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
3056 /* Set the DqsRcvEnTrain bit */
3057 dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
3058 dword |= DC_DqsRcvEnTrain;
3059 pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
3062 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
3063 dcl |= DCL_InitDram;
3064 pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
3067 for (i = 0; i < controllers; i++) {
3068 uint32_t dcl, dch, dcm;
3069 if (!sysinfo->ctrl_present[ i ])
3071 /* Skip everything if I don't have any memory on this controller */
3072 if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
3074 print_debug("Initializing memory: ");
3077 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
3079 if ((loops & 1023) == 0) {
3082 } while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS));
3083 if (loops >= TIMEOUT_LOOPS) {
3084 print_debug(" failed\r\n");
3088 /* Wait until it is safe to touch memory */
3090 dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
3091 } while(((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ );
3093 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3097 print_debug_dqs_tsc("\r\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
3098 print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2);
3100 if (tsc.lo<tsc0[i].lo) {
3103 tsc.lo -= tsc0[i].lo;
3104 tsc.hi -= tsc0[i].hi;
3106 tsc0[i].lo = tsc.lo;
3107 tsc0[i].hi = tsc.hi;
3109 print_debug_dqs_tsc(" dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
3112 print_debug(" done\r\n");
3115 #if HW_MEM_HOLE_SIZEK != 0
3116 /* init hw mem hole here */
3117 /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
3118 set_hw_mem_hole(controllers, ctrl);
3121 /* store tom to sysinfo, and it will be used by dqs_timing */
3125 msr = rdmsr(TOP_MEM);
3126 sysinfo->tom_k = ((msr.hi<<24) | (msr.lo>>8))>>2;
3129 msr = rdmsr(TOP_MEM2);
3130 sysinfo->tom2_k = ((msr.hi<<24)| (msr.lo>>8))>>2;
3133 for (i = 0; i < controllers; i++) {
3134 sysinfo->mem_trained[i] = 0;
3136 if (!sysinfo->ctrl_present[ i ])
3139 /* Skip everything if I don't have any memory on this controller */
3140 if (sysinfo->meminfo[i].dimm_mask==0x00)
3143 sysinfo->mem_trained[i] = 0x80; // mem need to be trained
3147 #if MEM_TRAIN_SEQ == 0
3148 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
3149 dqs_timing(controllers, ctrl, tsc0, sysinfo);
3151 dqs_timing(controllers, ctrl, sysinfo);
3155 #if MEM_TRAIN_SEQ == 2
3156 /* need to enable mtrr, so dqs training could access the test address */
3157 setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
3160 for (i = 0; i < controllers; i++) {
3161 /* Skip everything if I don't have any memory on this controller */
3162 if (sysinfo->mem_trained[i]!=0x80)
3165 dqs_timing(i, &ctrl[i], sysinfo, 1);
3167 #if MEM_TRAIN_SEQ == 1
3168 break; // only train the first node with ram
3172 #if MEM_TRAIN_SEQ == 2
3173 clear_mtrr_dqs(sysinfo->tom2_k);
3178 #if MEM_TRAIN_SEQ != 1
3179 wait_all_core0_mem_trained(sysinfo);
3185 static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
3186 const uint16_t *spd_addr)
3190 struct mem_controller *ctrl;
3191 for (i=0;i<controllers; i++) {
3194 ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
3195 ctrl->f1 = PCI_DEV(0, 0x18+i, 1);
3196 ctrl->f2 = PCI_DEV(0, 0x18+i, 2);
3197 ctrl->f3 = PCI_DEV(0, 0x18+i, 3);
3199 if (spd_addr == (void *)0) continue;
3201 for (j=0;j<DIMM_SOCKETS;j++) {
3202 ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
3203 ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];