1 /* This should be done by Eric
2 2004.12 yhlu add dual core support
3 2005.01 yhlu add support move apic before pci_domain in MB devicetree.cb
4 2005.02 yhlu add e0 memory hole support
5 2005.11 yhlu add put sb ht chain on bus 0
8 #include <console/console.h>
11 #include <device/device.h>
12 #include <device/pci.h>
13 #include <device/pci_ids.h>
14 #include <device/hypertransport.h>
20 #include <cpu/x86/lapic.h>
22 #include <cpu/amd/multicore.h>
23 #if CONFIG_LOGICAL_CPUS==1
24 #include <pc80/mc146818rtc.h>
28 #include "root_complex/chip.h"
29 #include "northbridge.h"
33 #include <cpu/amd/model_fxx_rev.h>
35 #include <cpu/amd/amdk8_sysconf.h>
37 struct amdk8_sysconf_t sysconf;
40 static device_t __f0_dev[MAX_FX_DEVS];
41 static device_t __f1_dev[MAX_FX_DEVS];
42 static unsigned fx_devs=0;
44 static void get_fx_devs(void)
47 for(i = 0; i < MAX_FX_DEVS; i++) {
48 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
49 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
50 if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
53 if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
54 die("Cannot find 0:0x18.[0|1]\n");
58 static u32 f1_read_config32(unsigned reg)
62 return pci_read_config32(__f1_dev[0], reg);
65 static void f1_write_config32(unsigned reg, u32 value)
70 for(i = 0; i < fx_devs; i++) {
73 if (dev && dev->enabled) {
74 pci_write_config32(dev, reg, value);
79 static u32 amdk8_nodeid(device_t dev)
81 return (dev->path.pci.devfn >> 3) - 0x18;
84 static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink,
85 u32 max, u32 offset_unitid)
90 u32 busses, config_busses;
91 u32 free_reg, config_reg;
92 u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
97 link->cap = 0x80 + (link_num *0x20);
99 link_type = pci_read_config32(dev, link->cap + 0x18);
100 } while(link_type & ConnectionPending);
101 if (!(link_type & LinkConnected)) {
105 link_type = pci_read_config32(dev, link->cap + 0x18);
106 } while(!(link_type & InitComplete));
107 if (!(link_type & NonCoherent)) {
110 /* See if there is an available configuration space mapping
111 * register in function 1.
114 for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
116 config = f1_read_config32(config_reg);
117 if (!free_reg && ((config & 3) == 0)) {
118 free_reg = config_reg;
121 if (((config & 3) == 3) &&
122 (((config >> 4) & 7) == nodeid) &&
123 (((config >> 8) & 3) == link_num)) {
127 if (free_reg && (config_reg > 0xec)) {
128 config_reg = free_reg;
130 /* If we can't find an available configuration space mapping
131 * register skip this bus
133 if (config_reg > 0xec) {
137 /* Set up the primary, secondary and subordinate bus numbers.
138 * We have no idea how many busses are behind this bridge yet,
139 * so we set the subordinate bus number to 0xff for the moment.
141 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
142 // first chain will on bus 0
143 if((nodeid == 0) && (sblink==link_num)) { // actually max is 0 here
146 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
147 // second chain will be on 0x40, third 0x80, forth 0xc0
149 min_bus = ((max>>6) + 1) * 0x40;
163 link->secondary = min_bus;
164 link->subordinate = max_bus;
166 /* Read the existing primary/secondary/subordinate bus
167 * number configuration.
169 busses = pci_read_config32(dev, link->cap + 0x14);
170 config_busses = f1_read_config32(config_reg);
172 /* Configure the bus numbers for this bridge: the configuration
173 * transactions will not be propagates by the bridge if it is
174 * not correctly configured
176 busses &= 0xff000000;
177 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
178 ((unsigned int)(link->secondary) << 8) |
179 ((unsigned int)(link->subordinate) << 16));
180 pci_write_config32(dev, link->cap + 0x14, busses);
182 config_busses &= 0x000fc88;
184 (3 << 0) | /* rw enable, no device compare */
185 (( nodeid & 7) << 4) |
186 (( link_num & 3 ) << 8) |
187 ((link->secondary) << 16) |
188 ((link->subordinate) << 24);
189 f1_write_config32(config_reg, config_busses);
191 /* Now we can scan all of the subordinate busses i.e. the
192 * chain on the hypertranport link
195 ht_unitid_base[i] = 0x20;
199 max_devfn = (0x17<<3) | 7;
201 max_devfn = (0x1f<<3) | 7;
203 max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unitid);
205 /* We know the number of busses behind this bridge. Set the
206 * subordinate bus number to it's real value
208 link->subordinate = max;
209 busses = (busses & 0xff00ffff) |
210 ((unsigned int) (link->subordinate) << 16);
211 pci_write_config32(dev, link->cap + 0x14, busses);
213 config_busses = (config_busses & 0x00ffffff) |
214 (link->subordinate << 24);
215 f1_write_config32(config_reg, config_busses);
218 // use config_reg and ht_unitid_base to update hcdn_reg
221 index = (config_reg-0xe0) >> 2;
223 temp |= (ht_unitid_base[i] & 0xff) << (i*8);
226 sysconf.hcdn_reg[index] = temp;
232 static unsigned amdk8_scan_chains(device_t dev, unsigned max)
237 unsigned offset_unitid = 0;
239 nodeid = amdk8_nodeid(dev);
242 sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
243 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
244 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
247 for (link = dev->link_list; link; link = link->next)
248 if (link->link_num == sblink)
249 max = amdk8_scan_chain(dev, nodeid, link, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
253 for (link = dev->link_list; link; link = link->next) {
254 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
255 if( (nodeid == 0) && (sblink == link->link_num) ) continue; //already done
258 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
259 #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
260 if((nodeid == 0) && (sblink == link->link_num))
265 max = amdk8_scan_chain(dev, nodeid, link, link->link_num, sblink, max, offset_unitid);
271 static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
274 struct resource *res;
275 unsigned nodeid, link = 0;
278 for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
280 dev = __f0_dev[nodeid];
283 for(link = 0; !res && (link < 3); link++) {
284 res = probe_resource(dev, IOINDEX(0x100 + reg, link));
290 if ( (goal_link == (link - 1)) &&
291 (goal_nodeid == (nodeid - 1)) &&
299 static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link,
300 unsigned min, unsigned max)
303 unsigned free_reg, reg;
306 for(reg = min; reg <= max; reg += 0x8) {
308 result = reg_useable(reg, dev, nodeid, link);
310 /* I have been allocated this one */
313 else if (result > 1) {
314 /* I have a free register pair */
322 resource = IOINDEX(0x100 + reg, link);
327 static unsigned amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
329 return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8);
332 static unsigned amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
334 return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8);
337 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
339 struct resource *resource;
341 /* Initialize the io space constraints on the current bus */
342 resource = new_resource(dev, IOINDEX(0, link));
346 resource->align = log2(HT_IO_HOST_ALIGN);
347 resource->gran = log2(HT_IO_HOST_ALIGN);
348 resource->limit = 0xffffUL;
349 resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
352 /* Initialize the prefetchable memory constraints on the current bus */
353 resource = new_resource(dev, IOINDEX(2, link));
357 resource->align = log2(HT_MEM_HOST_ALIGN);
358 resource->gran = log2(HT_MEM_HOST_ALIGN);
359 resource->limit = 0xffffffffffULL;
360 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
361 resource->flags |= IORESOURCE_BRIDGE;
364 /* Initialize the memory constraints on the current bus */
365 resource = new_resource(dev, IOINDEX(1, link));
369 resource->align = log2(HT_MEM_HOST_ALIGN);
370 resource->gran = log2(HT_MEM_HOST_ALIGN);
371 resource->limit = 0xffffffffULL;
372 resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
376 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid);
378 static void amdk8_read_resources(device_t dev)
382 nodeid = amdk8_nodeid(dev);
383 for(link = dev->link_list; link; link = link->next) {
384 if (link->children) {
385 amdk8_link_read_bases(dev, nodeid, link->link_num);
388 amdk8_create_vga_resource(dev, nodeid);
391 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
394 resource_t rbase, rend;
395 unsigned reg, link_num;
398 /* Make certain the resource has actually been set */
399 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
400 printk(BIOS_ERR, "%s: can't set unassigned resource @%lx %lx\n",
401 __func__, resource->index, resource->flags);
405 /* If I have already stored this resource don't worry about it */
406 if (resource->flags & IORESOURCE_STORED) {
407 printk(BIOS_ERR, "%s: can't set stored resource @%lx %lx\n", __func__,
408 resource->index, resource->flags);
412 /* Only handle PCI memory and IO resources */
413 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
416 /* Ensure I am actually looking at a resource of function 1 */
417 if (resource->index < 0x100) {
421 if (resource->size == 0)
424 /* Get the base address */
425 rbase = resource->base;
427 /* Get the limit (rounded up) */
428 rend = resource_end(resource);
430 /* Get the register and link */
431 reg = resource->index & 0xfc;
432 link_num = IOINDEX_LINK(resource->index);
434 for (link = dev->link_list; link; link = link->next)
435 if (link->link_num == link_num)
439 printk(BIOS_ERR, "%s: can't find link %x for %lx\n", __func__,
440 link_num, resource->index);
444 if (resource->flags & IORESOURCE_IO) {
446 base = f1_read_config32(reg);
447 limit = f1_read_config32(reg + 0x4);
449 base |= rbase & 0x01fff000;
452 limit |= rend & 0x01fff000;
453 limit |= (link_num & 3) << 4;
454 limit |= (nodeid & 7);
456 if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
457 printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
458 __func__, dev_path(dev), link_num);
459 base |= PCI_IO_BASE_VGA_EN;
461 if (link->bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
462 base |= PCI_IO_BASE_NO_ISA;
465 f1_write_config32(reg + 0x4, limit);
466 f1_write_config32(reg, base);
468 else if (resource->flags & IORESOURCE_MEM) {
470 base = f1_read_config32(reg);
471 limit = f1_read_config32(reg + 0x4);
473 base |= (rbase >> 8) & 0xffffff00;
476 limit |= (rend >> 8) & 0xffffff00;
477 limit |= (link_num & 3) << 4;
478 limit |= (nodeid & 7);
479 f1_write_config32(reg + 0x4, limit);
480 f1_write_config32(reg, base);
482 resource->flags |= IORESOURCE_STORED;
483 sprintf(buf, " <node %x link %x>",
485 report_resource_stored(dev, resource, buf);
488 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
490 struct resource *resource;
493 /* find out which link the VGA card is connected,
494 * we only deal with the 'first' vga card */
495 for (link = dev->link_list; link; link = link->next) {
496 if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
497 #if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
498 extern device_t vga_pri; // the primary vga device, defined in device.c
499 printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary,
500 link->secondary,link->subordinate);
501 /* We need to make sure the vga_pri is under the link */
502 if((vga_pri->bus->secondary >= link->secondary ) &&
503 (vga_pri->bus->secondary <= link->subordinate )
510 /* no VGA card installed */
514 printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num);
516 /* allocate a temp resource for the legacy VGA buffer */
517 resource = new_resource(dev, IOINDEX(4, link->link_num));
519 printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev));
522 resource->base = 0xa0000;
523 resource->size = 0x20000;
524 resource->limit = 0xffffffff;
525 resource->flags = IORESOURCE_FIXED | IORESOURCE_MEM |
529 static void amdk8_set_resources(device_t dev)
533 struct resource *res;
535 /* Find the nodeid */
536 nodeid = amdk8_nodeid(dev);
538 /* Set each resource we have found */
539 for(res = dev->resource_list; res; res = res->next) {
540 struct resource *old = NULL;
543 if (res->size == 0) /* No need to allocate registers. */
546 if (res->flags & IORESOURCE_IO)
547 index = amdk8_find_iopair(dev, nodeid,
548 IOINDEX_LINK(res->index));
550 index = amdk8_find_mempair(dev, nodeid,
551 IOINDEX_LINK(res->index));
553 old = probe_resource(dev, index);
555 res->index = old->index;
562 amdk8_set_resource(dev, res, nodeid);
565 compact_resources(dev);
567 for(bus = dev->link_list; bus; bus = bus->next) {
569 assign_resources(bus);
574 static void mcf0_control_init(struct device *dev)
577 printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. ");
580 printk(BIOS_DEBUG, "done.\n");
584 static struct device_operations northbridge_operations = {
585 .read_resources = amdk8_read_resources,
586 .set_resources = amdk8_set_resources,
587 .enable_resources = pci_dev_enable_resources,
588 .init = mcf0_control_init,
589 .scan_bus = amdk8_scan_chains,
595 static const struct pci_driver mcf0_driver __pci_driver = {
596 .ops = &northbridge_operations,
597 .vendor = PCI_VENDOR_ID_AMD,
601 struct chip_operations northbridge_amd_amdk8_ops = {
602 CHIP_NAME("AMD K8 Northbridge")
606 static void amdk8_domain_read_resources(device_t dev)
610 /* Find the already assigned resource pairs */
612 for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
614 base = f1_read_config32(reg);
615 limit = f1_read_config32(reg + 0x04);
616 /* Is this register allocated? */
617 if ((base & 3) != 0) {
618 unsigned nodeid, reg_link;
621 reg_link = (limit >> 4) & 3;
622 reg_dev = __f0_dev[nodeid];
624 /* Reserve the resource */
625 struct resource *res;
626 res = new_resource(reg_dev, IOINDEX(0x100 + reg, reg_link));
636 pci_domain_read_resources(dev);
638 #if CONFIG_PCI_64BIT_PREF_MEM == 1
639 /* Initialize the system wide prefetchable memory resources constraints */
640 resource = new_resource(dev, 2);
641 resource->limit = 0xfcffffffffULL;
642 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
646 static void my_tolm_test(void *gp, struct device *dev, struct resource *new)
648 struct resource **best_p = gp;
649 struct resource *best;
652 if (!best || (best->base > new->base && new->base > 0xa0000)) {
658 static u32 my_find_pci_tolm(struct bus *bus)
660 struct resource *min;
663 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, my_tolm_test, &min);
665 if (min && tolm > min->base) {
671 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
673 struct hw_mem_hole_info {
674 unsigned hole_startk;
678 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
680 struct hw_mem_hole_info mem_hole;
683 mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
684 mem_hole.node_id = -1;
686 for (i = 0; i < fx_devs; i++) {
689 base = f1_read_config32(0x40 + (i << 3));
690 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
694 hole = pci_read_config32(__f1_dev[i], 0xf0);
695 if(hole & 1) { // we find the hole
696 mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
697 mem_hole.node_id = i; // record the node No with hole
698 break; // only one hole
702 //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
703 if(mem_hole.node_id==-1) {
707 unsigned base_k, limit_k;
708 base = f1_read_config32(0x40 + (i << 3));
709 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
713 base_k = (base & 0xffff0000) >> 2;
714 if(limitk_pri != base_k) { // we find the hole
715 mem_hole.hole_startk = limitk_pri;
716 mem_hole.node_id = i;
717 break; //only one hole
720 limit = f1_read_config32(0x44 + (i << 3));
721 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
722 limitk_pri = limit_k;
728 static void disable_hoist_memory(unsigned long hole_startk, int node_id)
737 //1. find which node has hole
738 //2. change limit in that node.
739 //3. change base and limit in later node
740 //4. clear that node f0
742 //if there is not mem hole enabled, we need to change it's base instead
744 hole_sizek = (4*1024*1024) - hole_startk;
746 for(i=7;i>node_id;i--) {
748 base = f1_read_config32(0x40 + (i << 3));
749 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
752 limit = f1_read_config32(0x44 + (i << 3));
753 f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
754 f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
756 limit = f1_read_config32(0x44 + (node_id << 3));
757 f1_write_config32(0x44 + (node_id << 3),limit - (hole_sizek << 2));
758 dev = __f1_dev[node_id];
760 printk(BIOS_ERR, "%s: node %x is NULL!\n", __func__, node_id);
763 hoist = pci_read_config32(dev, 0xf0);
765 pci_write_config32(dev, 0xf0, 0);
767 base = pci_read_config32(dev, 0x40 + (node_id << 3));
768 f1_write_config32(0x40 + (node_id << 3),base - (hole_sizek << 2));
772 static u32 hoist_memory(unsigned long hole_startk, int node_id)
781 carry_over = (4*1024*1024) - hole_startk;
783 for(i=7;i>node_id;i--) {
785 base = f1_read_config32(0x40 + (i << 3));
786 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
789 limit = f1_read_config32(0x44 + (i << 3));
790 f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
791 f1_write_config32(0x40 + (i << 3),base + (carry_over << 2));
793 limit = f1_read_config32(0x44 + (node_id << 3));
794 f1_write_config32(0x44 + (node_id << 3),limit + (carry_over << 2));
795 dev = __f1_dev[node_id];
796 base = pci_read_config32(dev, 0x40 + (node_id << 3));
797 basek = (base & 0xffff0000) >> 2;
798 if(basek == hole_startk) {
799 //don't need set memhole here, because hole off set will be 0, overflow
800 //so need to change base reg instead, new basek will be 4*1024*1024
802 base |= (4*1024*1024)<<2;
803 f1_write_config32(0x40 + (node_id<<3), base);
807 hoist = /* hole start address */
808 ((hole_startk << 10) & 0xff000000) +
809 /* hole address to memory controller address */
810 (((basek + carry_over) >> 6) & 0x0000ff00) +
814 pci_write_config32(dev, 0xf0, hoist);
821 #if CONFIG_WRITE_HIGH_TABLES==1
823 #define HIGH_TABLES_SIZE ((HIGH_MEMORY_SIZE + 1024) / 1024)
824 extern uint64_t high_tables_base, high_tables_size;
827 #if CONFIG_GFXUMA == 1
828 extern uint64_t uma_memory_base, uma_memory_size;
830 static void add_uma_resource(struct device *dev, int index)
832 struct resource *resource;
834 printk(BIOS_DEBUG, "Adding UMA memory area\n");
835 resource = new_resource(dev, index);
836 resource->base = (resource_t) uma_memory_base;
837 resource->size = (resource_t) uma_memory_size;
838 resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
839 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
843 static void amdk8_domain_set_resources(device_t dev)
845 #if CONFIG_PCI_64BIT_PREF_MEM == 1
846 struct resource *io, *mem1, *mem2;
847 struct resource *res;
849 unsigned long mmio_basek;
852 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
853 struct hw_mem_hole_info mem_hole;
854 u32 reset_memhole = 1;
858 /* Place the IO devices somewhere safe */
859 io = find_resource(dev, 0);
860 io->base = DEVICE_IO_START;
862 #if CONFIG_PCI_64BIT_PREF_MEM == 1
863 /* Now reallocate the pci resources memory with the
864 * highest addresses I can manage.
866 mem1 = find_resource(dev, 1);
867 mem2 = find_resource(dev, 2);
870 printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
871 mem1->base, mem1->limit, mem1->size, mem1->align);
872 printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
873 mem2->base, mem2->limit, mem2->size, mem2->align);
876 /* See if both resources have roughly the same limits */
877 if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
878 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
880 /* If so place the one with the most stringent alignment first
882 if (mem2->align > mem1->align) {
883 struct resource *tmp;
888 /* Now place the memory as high up as it will go */
889 mem2->base = resource_max(mem2);
890 mem1->limit = mem2->base - 1;
891 mem1->base = resource_max(mem1);
894 /* Place the resources as high up as they will go */
895 mem2->base = resource_max(mem2);
896 mem1->base = resource_max(mem1);
900 printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
901 mem1->base, mem1->limit, mem1->size, mem1->align);
902 printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
903 mem2->base, mem2->limit, mem2->size, mem2->align);
906 for(res = dev->resource_list; res; res = res->next)
908 res->flags |= IORESOURCE_ASSIGNED;
909 res->flags |= IORESOURCE_STORED;
910 report_resource_stored(dev, res, "");
914 pci_tolm = my_find_pci_tolm(dev->link_list);
916 // FIXME handle interleaved nodes. If you fix this here, please fix
918 mmio_basek = pci_tolm >> 10;
919 /* Round mmio_basek to something the processor can support */
920 mmio_basek &= ~((1 << 6) -1);
922 // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
923 // MMIO hole. If you fix this here, please fix amdfam10, too.
924 /* Round the mmio hole to 64M */
925 mmio_basek &= ~((64*1024) - 1);
927 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
928 /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
929 * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
930 * otherwise We reset the hole to the mmio_basek
932 #if CONFIG_K8_REV_F_SUPPORT == 0
933 if (!is_cpu_pre_e0()) {
936 mem_hole = get_hw_mem_hole_info();
938 if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
939 mmio_basek = mem_hole.hole_startk;
943 //mmio_basek = 3*1024*1024; // for debug to meet boundary
946 if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
947 // We need to reset our Mem Hole, because We want more big HOLE than we already set
948 //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
949 disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
952 #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
953 //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
955 for (i = 0; i < fx_devs; i++) {
958 base = f1_read_config32(0x40 + (i << 3));
959 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
963 basek = (base & 0xffff0000) >> 2;
964 if(mmio_basek == basek) {
965 mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node
973 #if CONFIG_K8_REV_F_SUPPORT == 0
980 for(i = 0; i < fx_devs; i++) {
982 u32 basek, limitk, sizek;
983 base = f1_read_config32(0x40 + (i << 3));
984 limit = f1_read_config32(0x44 + (i << 3));
985 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
988 basek = (base & 0xffff0000) >> 2;
989 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
990 sizek = limitk - basek;
992 /* see if we need a hole from 0xa0000 to 0xbffff */
993 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
994 ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
996 basek = (8*64)+(16*16);
997 sizek = limitk - ((8*64)+(16*16));
1002 #if CONFIG_GFXUMA == 1
1003 printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
1004 if ((uma_memory_base >> 10) < mmio_basek)
1005 printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i);
1007 // printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
1010 /* See if I need to split the region to accomodate pci memory space */
1011 if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
1012 if (basek <= mmio_basek) {
1014 pre_sizek = mmio_basek - basek;
1016 ram_resource(dev, (idx | i), basek, pre_sizek);
1019 #if CONFIG_WRITE_HIGH_TABLES==1
1020 if (high_tables_base==0) {
1021 /* Leave some space for ACPI, PIRQ and MP tables */
1022 #if CONFIG_GFXUMA == 1
1023 high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
1025 high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
1027 high_tables_size = HIGH_TABLES_SIZE * 1024;
1028 printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
1033 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
1035 #if CONFIG_K8_REV_F_SUPPORT == 0
1036 if(!is_cpu_pre_e0() )
1038 sizek += hoist_memory(mmio_basek,i);
1043 if ((basek + sizek) <= 4*1024*1024) {
1047 basek = 4*1024*1024;
1048 sizek -= (4*1024*1024 - mmio_basek);
1051 /* If sizek == 0, it was split at mmio_basek without a hole.
1052 * Don't create an empty ram_resource.
1054 #if CONFIG_GFXUMA == 1
1055 /* Deduct uma memory before reporting because
1056 * this is what the mtrr code expects */
1057 sizek -= uma_memory_size / 1024;
1060 ram_resource(dev, (idx | i), basek, sizek);
1062 #if CONFIG_WRITE_HIGH_TABLES==1
1063 printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
1064 i, mmio_basek, basek, limitk);
1065 if (high_tables_base==0) {
1066 /* Leave some space for ACPI, PIRQ and MP tables */
1067 #if CONFIG_GFXUMA == 1
1068 high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
1070 high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
1072 high_tables_size = HIGH_TABLES_SIZE * 1024;
1077 #if CONFIG_GFXUMA == 1
1078 add_uma_resource(dev, 7);
1080 assign_resources(dev->link_list);
1084 static u32 amdk8_domain_scan_bus(device_t dev, u32 max)
1088 /* Unmap all of the HT chains */
1089 for(reg = 0xe0; reg <= 0xec; reg += 4) {
1090 f1_write_config32(reg, 0);
1092 max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max);
1094 /* Tune the hypertransport transaction for best performance.
1095 * Including enabling relaxed ordering if it is safe.
1098 for(i = 0; i < fx_devs; i++) {
1100 f0_dev = __f0_dev[i];
1101 if (f0_dev && f0_dev->enabled) {
1103 httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
1104 httc &= ~HTTC_RSP_PASS_PW;
1105 if (!dev->link_list->disable_relaxed_ordering) {
1106 httc |= HTTC_RSP_PASS_PW;
1108 printk(BIOS_SPEW, "%s passpw: %s\n",
1110 (!dev->link_list->disable_relaxed_ordering)?
1111 "enabled":"disabled");
1112 pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
1118 static struct device_operations pci_domain_ops = {
1119 .read_resources = amdk8_domain_read_resources,
1120 .set_resources = amdk8_domain_set_resources,
1121 .enable_resources = NULL,
1123 .scan_bus = amdk8_domain_scan_bus,
1124 .ops_pci_bus = &pci_cf8_conf1,
1127 static void add_more_links(device_t dev, unsigned total_links)
1129 struct bus *link, *last = NULL;
1132 for (link = dev->link_list; link; link = link->next)
1136 int links = total_links - last->link_num;
1137 link_num = last->link_num;
1139 link = malloc(links*sizeof(*link));
1141 die("Couldn't allocate more links!\n");
1142 memset(link, 0, links*sizeof(*link));
1148 link = malloc(total_links*sizeof(*link));
1149 memset(link, 0, total_links*sizeof(*link));
1150 dev->link_list = link;
1153 for (link_num = link_num + 1; link_num < total_links; link_num++) {
1154 link->link_num = link_num;
1156 link->next = link + 1;
1163 static u32 cpu_bus_scan(device_t dev, u32 max)
1165 struct bus *cpu_bus;
1171 int e0_later_single_core;
1172 int disable_siblings;
1175 sysconf.enabled_apic_ext_id = 0;
1176 sysconf.lift_bsp_apicid = 0;
1179 /* Find the bootstrap processors apicid */
1180 bsp_apicid = lapicid();
1181 sysconf.apicid_offset = bsp_apicid;
1183 disable_siblings = !CONFIG_LOGICAL_CPUS;
1184 #if CONFIG_LOGICAL_CPUS == 1
1185 get_option(&disable_siblings, "multi_core");
1188 // for pre_e0, nb_cfg_54 can not be set, (when you read it still is 0)
1189 // How can I get the nb_cfg_54 of every node's nb_cfg_54 in bsp???
1190 // and differ d0 and e0 single core
1191 nb_cfg_54 = read_nb_cfg_54();
1193 dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
1195 die("0:18.0 not found?");
1198 sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
1201 if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
1203 sysconf.enabled_apic_ext_id = 1;
1204 if(bsp_apicid == 0) {
1205 /* bsp apic id is not changed */
1206 sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET;
1209 sysconf.lift_bsp_apicid = 1;
1214 /* Find which cpus are present */
1215 cpu_bus = dev->link_list;
1216 for(i = 0; i < sysconf.nodes; i++) {
1217 device_t cpu_dev, cpu;
1218 struct device_path cpu_path;
1220 /* Find the cpu's pci device */
1221 cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
1223 /* If I am probing things in a weird order
1224 * ensure all of the cpu's pci devices are found.
1228 for(local_j = 0; local_j <= 3; local_j++) {
1229 cpu_dev = pci_probe_dev(NULL, dev_mc->bus,
1230 PCI_DEVFN(0x18 + i, local_j));
1232 /* Ok, We need to set the links for that device.
1233 * otherwise the device under it will not be scanned
1235 dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0));
1237 add_more_links(dev_f0, 3);
1241 e0_later_single_core = 0;
1242 if (cpu_dev && cpu_dev->enabled) {
1243 j = pci_read_config32(cpu_dev, 0xe8);
1244 j = (j >> 12) & 3; // dev is func 3
1245 printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(cpu_dev), j);
1248 // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
1249 // ----> you can mixed single core e0 and dual core e0 at any sequence
1250 // That is the typical case
1253 #if CONFIG_K8_REV_F_SUPPORT == 0
1254 e0_later_single_core = is_e0_later_in_bsp(i); // single core
1256 e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
1259 e0_later_single_core = 0;
1261 if(e0_later_single_core) {
1262 printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");
1278 if(e0_later_single_core || disable_siblings) {
1285 jj = 0; // if create cpu core1 path in amd_siblings by core0
1288 for (j = 0; j <=jj; j++ ) {
1290 /* Build the cpu device path */
1291 cpu_path.type = DEVICE_PATH_APIC;
1292 cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
1294 /* See if I can find the cpu */
1295 cpu = find_dev_path(cpu_bus, &cpu_path);
1297 /* Enable the cpu if I have the processor */
1298 if (cpu_dev && cpu_dev->enabled) {
1300 cpu = alloc_dev(cpu_bus, &cpu_path);
1307 /* Disable the cpu if I don't have the processor */
1308 if (cpu && (!cpu_dev || !cpu_dev->enabled)) {
1312 /* Report what I have done */
1314 cpu->path.apic.node_id = i;
1315 cpu->path.apic.core_id = j;
1316 if(sysconf.enabled_apic_ext_id) {
1317 if(sysconf.lift_bsp_apicid) {
1318 cpu->path.apic.apic_id += sysconf.apicid_offset;
1321 if (cpu->path.apic.apic_id != 0)
1322 cpu->path.apic.apic_id += sysconf.apicid_offset;
1325 printk(BIOS_DEBUG, "CPU: %s %s\n",
1326 dev_path(cpu), cpu->enabled?"enabled":"disabled");
1334 static void cpu_bus_init(device_t dev)
1336 initialize_cpus(dev->link_list);
1339 static void cpu_bus_noop(device_t dev)
1343 static struct device_operations cpu_bus_ops = {
1344 .read_resources = cpu_bus_noop,
1345 .set_resources = cpu_bus_noop,
1346 .enable_resources = cpu_bus_noop,
1347 .init = cpu_bus_init,
1348 .scan_bus = cpu_bus_scan,
1351 static void root_complex_enable_dev(struct device *dev)
1353 /* Set the operations if it is a special bus type */
1354 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
1355 dev->ops = &pci_domain_ops;
1357 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
1358 dev->ops = &cpu_bus_ops;
1362 struct chip_operations northbridge_amd_amdk8_root_complex_ops = {
1363 CHIP_NAME("AMD K8 Root Complex")
1364 .enable_dev = root_complex_enable_dev,