1 /* This should be done by Eric
2 2004.12 yhlu add dual core support
3 2005.01 yhlu add support move apic before pci_domain in MB Config.lb
4 2005.02 yhlu add e0 memory hole support
5 2005.11 yhlu add put sb ht chain on bus 0
8 #include <console/console.h>
11 #include <device/device.h>
12 #include <device/pci.h>
13 #include <device/pci_ids.h>
14 #include <device/hypertransport.h>
20 #include <cpu/x86/lapic.h>
22 #if CONFIG_LOGICAL_CPUS==1
23 #include <cpu/amd/dualcore.h>
24 #include <pc80/mc146818rtc.h>
28 #include "root_complex/chip.h"
29 #include "northbridge.h"
33 #if HW_MEM_HOLE_SIZEK != 0
34 #include <cpu/amd/model_fxx_rev.h>
37 #include <cpu/amd/amdk8_sysconf.h>
39 struct amdk8_sysconf_t sysconf;
42 static device_t __f0_dev[FX_DEVS];
43 static device_t __f1_dev[FX_DEVS];
46 static void debug_fx_devs(void)
49 for(i = 0; i < FX_DEVS; i++) {
53 printk_debug("__f0_dev[%d]: %s bus: %p\n",
54 i, dev_path(dev), dev->bus);
58 printk_debug("__f1_dev[%d]: %s bus: %p\n",
59 i, dev_path(dev), dev->bus);
65 static void get_fx_devs(void)
71 for(i = 0; i < FX_DEVS; i++) {
72 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
73 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
76 die("Cannot find 0:0x18.1\n");
80 static uint32_t f1_read_config32(unsigned reg)
83 return pci_read_config32(__f1_dev[0], reg);
86 static void f1_write_config32(unsigned reg, uint32_t value)
90 for(i = 0; i < FX_DEVS; i++) {
93 if (dev && dev->enabled) {
94 pci_write_config32(dev, reg, value);
99 static unsigned int amdk8_nodeid(device_t dev)
101 return (dev->path.pci.devfn >> 3) - 0x18;
104 static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
109 uint32_t busses, config_busses;
110 unsigned free_reg, config_reg;
111 unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
116 dev->link[link].cap = 0x80 + (link *0x20);
118 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
119 } while(link_type & ConnectionPending);
120 if (!(link_type & LinkConnected)) {
124 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
125 } while(!(link_type & InitComplete));
126 if (!(link_type & NonCoherent)) {
129 /* See if there is an available configuration space mapping
130 * register in function 1.
133 for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
135 config = f1_read_config32(config_reg);
136 if (!free_reg && ((config & 3) == 0)) {
137 free_reg = config_reg;
140 if (((config & 3) == 3) &&
141 (((config >> 4) & 7) == nodeid) &&
142 (((config >> 8) & 3) == link)) {
146 if (free_reg && (config_reg > 0xec)) {
147 config_reg = free_reg;
149 /* If we can't find an available configuration space mapping
150 * register skip this bus
152 if (config_reg > 0xec) {
156 /* Set up the primary, secondary and subordinate bus numbers.
157 * We have no idea how many busses are behind this bridge yet,
158 * so we set the subordinate bus number to 0xff for the moment.
160 #if SB_HT_CHAIN_ON_BUS0 > 0
161 // first chain will on bus 0
162 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
165 #if SB_HT_CHAIN_ON_BUS0 > 1
166 // second chain will be on 0x40, third 0x80, forth 0xc0
168 min_bus = ((max>>6) + 1) * 0x40;
182 dev->link[link].secondary = min_bus;
183 dev->link[link].subordinate = max_bus;
185 /* Read the existing primary/secondary/subordinate bus
186 * number configuration.
188 busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
189 config_busses = f1_read_config32(config_reg);
191 /* Configure the bus numbers for this bridge: the configuration
192 * transactions will not be propagates by the bridge if it is
193 * not correctly configured
195 busses &= 0xff000000;
196 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
197 ((unsigned int)(dev->link[link].secondary) << 8) |
198 ((unsigned int)(dev->link[link].subordinate) << 16));
199 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
201 config_busses &= 0x000fc88;
203 (3 << 0) | /* rw enable, no device compare */
204 (( nodeid & 7) << 4) |
205 (( link & 3 ) << 8) |
206 ((dev->link[link].secondary) << 16) |
207 ((dev->link[link].subordinate) << 24);
208 f1_write_config32(config_reg, config_busses);
210 /* Now we can scan all of the subordinate busses i.e. the
211 * chain on the hypertranport link
214 ht_unitid_base[i] = 0x20;
218 max_devfn = (0x17<<3) | 7;
220 max_devfn = (0x1f<<3) | 7;
222 max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid);
224 /* We know the number of busses behind this bridge. Set the
225 * subordinate bus number to it's real value
227 dev->link[link].subordinate = max;
228 busses = (busses & 0xff00ffff) |
229 ((unsigned int) (dev->link[link].subordinate) << 16);
230 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
232 config_busses = (config_busses & 0x00ffffff) |
233 (dev->link[link].subordinate << 24);
234 f1_write_config32(config_reg, config_busses);
237 // config config_reg, and ht_unitid_base to update hcdn_reg;
240 index = (config_reg-0xe0) >> 2;
242 temp |= (ht_unitid_base[i] & 0xff) << (i*8);
245 sysconf.hcdn_reg[index] = temp;
252 static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
257 unsigned offset_unitid = 0;
258 nodeid = amdk8_nodeid(dev);
261 sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
262 #if SB_HT_CHAIN_ON_BUS0 > 0
263 #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
266 max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
270 for(link = 0; link < dev->links; link++) {
271 #if SB_HT_CHAIN_ON_BUS0 > 0
272 if( (nodeid == 0) && (sblink == link) ) continue; //already done
275 #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
276 #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
277 if((nodeid == 0) && (sblink == link))
282 max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
289 static int reg_useable(unsigned reg,
290 device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
292 struct resource *res;
293 unsigned nodeid, link;
296 for(nodeid = 0; !res && (nodeid < 8); nodeid++) {
298 dev = __f0_dev[nodeid];
299 for(link = 0; !res && (link < 3); link++) {
300 res = probe_resource(dev, 0x100 + (reg | link));
306 if ( (goal_link == (link - 1)) &&
307 (goal_nodeid == (nodeid - 1)) &&
316 static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
318 struct resource *resource;
319 unsigned free_reg, reg;
322 for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
324 result = reg_useable(reg, dev, nodeid, link);
326 /* I have been allocated this one */
329 else if (result > 1) {
330 /* I have a free register pair */
338 resource = new_resource(dev, 0x100 + (reg | link));
343 static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
345 struct resource *resource;
346 unsigned free_reg, reg;
349 for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
351 result = reg_useable(reg, dev, nodeid, link);
353 /* I have been allocated this one */
356 else if (result > 1) {
357 /* I have a free register pair */
365 resource = new_resource(dev, 0x100 + (reg | link));
370 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
372 struct resource *resource;
374 /* Initialize the io space constraints on the current bus */
375 resource = amdk8_find_iopair(dev, nodeid, link);
379 resource->align = log2(HT_IO_HOST_ALIGN);
380 resource->gran = log2(HT_IO_HOST_ALIGN);
381 resource->limit = 0xffffUL;
382 resource->flags = IORESOURCE_IO;
383 compute_allocate_resource(&dev->link[link], resource,
384 IORESOURCE_IO, IORESOURCE_IO);
387 /* Initialize the prefetchable memory constraints on the current bus */
388 resource = amdk8_find_mempair(dev, nodeid, link);
392 resource->align = log2(HT_MEM_HOST_ALIGN);
393 resource->gran = log2(HT_MEM_HOST_ALIGN);
394 resource->limit = 0xffffffffffULL;
395 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
396 compute_allocate_resource(&dev->link[link], resource,
397 IORESOURCE_MEM | IORESOURCE_PREFETCH,
398 IORESOURCE_MEM | IORESOURCE_PREFETCH);
401 /* Initialize the memory constraints on the current bus */
402 resource = amdk8_find_mempair(dev, nodeid, link);
406 resource->align = log2(HT_MEM_HOST_ALIGN);
407 resource->gran = log2(HT_MEM_HOST_ALIGN);
408 resource->limit = 0xffffffffffULL;
409 resource->flags = IORESOURCE_MEM;
410 compute_allocate_resource(&dev->link[link], resource,
411 IORESOURCE_MEM | IORESOURCE_PREFETCH,
416 static void amdk8_read_resources(device_t dev)
418 unsigned nodeid, link;
419 nodeid = amdk8_nodeid(dev);
420 for(link = 0; link < dev->links; link++) {
421 if (dev->link[link].children) {
422 amdk8_link_read_bases(dev, nodeid, link);
427 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
429 resource_t rbase, rend;
433 /* Make certain the resource has actually been set */
434 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
438 /* If I have already stored this resource don't worry about it */
439 if (resource->flags & IORESOURCE_STORED) {
443 /* Only handle PCI memory and IO resources */
444 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
447 /* Ensure I am actually looking at a resource of function 1 */
448 if (resource->index < 0x100) {
451 /* Get the base address */
452 rbase = resource->base;
454 /* Get the limit (rounded up) */
455 rend = resource_end(resource);
457 /* Get the register and link */
458 reg = resource->index & 0xfc;
459 link = resource->index & 3;
461 if (resource->flags & IORESOURCE_IO) {
462 uint32_t base, limit;
463 compute_allocate_resource(&dev->link[link], resource,
464 IORESOURCE_IO, IORESOURCE_IO);
465 base = f1_read_config32(reg);
466 limit = f1_read_config32(reg + 0x4);
468 base |= rbase & 0x01fff000;
471 limit |= rend & 0x01fff000;
472 limit |= (link & 3) << 4;
473 limit |= (nodeid & 7);
475 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
476 printk_spew("%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
477 __func__, dev_path(dev), link);
478 base |= PCI_IO_BASE_VGA_EN;
480 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
481 base |= PCI_IO_BASE_NO_ISA;
484 f1_write_config32(reg + 0x4, limit);
485 f1_write_config32(reg, base);
487 else if (resource->flags & IORESOURCE_MEM) {
488 uint32_t base, limit;
489 compute_allocate_resource(&dev->link[link], resource,
490 IORESOURCE_MEM | IORESOURCE_PREFETCH,
491 resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
492 base = f1_read_config32(reg);
493 limit = f1_read_config32(reg + 0x4);
495 base |= (rbase >> 8) & 0xffffff00;
498 limit |= (rend >> 8) & 0xffffff00;
499 limit |= (link & 3) << 4;
500 limit |= (nodeid & 7);
501 f1_write_config32(reg + 0x4, limit);
502 f1_write_config32(reg, base);
504 resource->flags |= IORESOURCE_STORED;
505 sprintf(buf, " <node %d link %d>",
507 report_resource_stored(dev, resource, buf);
512 * I tried to reuse the resource allocation code in amdk8_set_resource()
513 * but it is too diffcult to deal with the resource allocation magic.
515 #if CONFIG_CONSOLE_VGA_MULTI == 1
516 extern device_t vga_pri; // the primary vga device, defined in device.c
519 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
521 struct resource *resource;
523 uint32_t base, limit;
526 /* find out which link the VGA card is connected,
527 * we only deal with the 'first' vga card */
528 for (link = 0; link < dev->links; link++) {
529 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
530 #if CONFIG_CONSOLE_VGA_MULTI == 1
531 printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
532 dev->link[link].secondary,dev->link[link].subordinate);
533 /* We need to make sure the vga_pri is under the link */
534 if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
535 (vga_pri->bus->secondary <= dev->link[link].subordinate )
542 /* no VGA card installed */
543 if (link == dev->links)
546 printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
548 /* allocate a temp resrouce for legacy VGA buffer */
549 resource = amdk8_find_mempair(dev, nodeid, link);
551 printk_debug("VGA: Can not find free mmio reg for legacy VGA buffer\n");
554 resource->base = 0xa0000;
555 resource->size = 0x20000;
557 /* write the resource to the hardware */
558 reg = resource->index & 0xfc;
559 base = f1_read_config32(reg);
560 limit = f1_read_config32(reg + 0x4);
562 base |= (resource->base >> 8) & 0xffffff00;
565 limit |= (resource_end(resource) >> 8) & 0xffffff00;
566 limit |= (resource->index & 3) << 4;
567 limit |= (nodeid & 7);
568 f1_write_config32(reg + 0x4, limit);
569 f1_write_config32(reg, base);
571 /* release the temp resource */
575 static void amdk8_set_resources(device_t dev)
577 unsigned nodeid, link;
580 /* Find the nodeid */
581 nodeid = amdk8_nodeid(dev);
583 amdk8_create_vga_resource(dev, nodeid);
585 /* Set each resource we have found */
586 for(i = 0; i < dev->resources; i++) {
587 amdk8_set_resource(dev, &dev->resource[i], nodeid);
590 for(link = 0; link < dev->links; link++) {
592 bus = &dev->link[link];
594 assign_resources(bus);
599 static void amdk8_enable_resources(device_t dev)
601 pci_dev_enable_resources(dev);
602 enable_childrens_resources(dev);
605 static void mcf0_control_init(struct device *dev)
608 printk_debug("NB: Function 0 Misc Control.. ");
611 printk_debug("done.\n");
615 static struct device_operations northbridge_operations = {
616 .read_resources = amdk8_read_resources,
617 .set_resources = amdk8_set_resources,
618 .enable_resources = amdk8_enable_resources,
619 .init = mcf0_control_init,
620 .scan_bus = amdk8_scan_chains,
626 static const struct pci_driver mcf0_driver __pci_driver = {
627 .ops = &northbridge_operations,
628 .vendor = PCI_VENDOR_ID_AMD,
632 #if CONFIG_CHIP_NAME == 1
634 struct chip_operations northbridge_amd_amdk8_ops = {
635 CHIP_NAME("AMD K8 Northbridge")
641 static void pci_domain_read_resources(device_t dev)
643 struct resource *resource;
646 /* Find the already assigned resource pairs */
648 for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
649 uint32_t base, limit;
650 base = f1_read_config32(reg);
651 limit = f1_read_config32(reg + 0x04);
652 /* Is this register allocated? */
653 if ((base & 3) != 0) {
654 unsigned nodeid, link;
657 link = (limit >> 4) & 3;
658 dev = __f0_dev[nodeid];
660 /* Reserve the resource */
661 struct resource *resource;
662 resource = new_resource(dev, 0x100 + (reg | link));
669 #if CONFIG_PCI_64BIT_PREF_MEM == 0
670 /* Initialize the system wide io space constraints */
671 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
672 resource->base = 0x400;
673 resource->limit = 0xffffUL;
674 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
676 /* Initialize the system wide memory resources constraints */
677 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
678 resource->limit = 0xfcffffffffULL;
679 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
681 /* Initialize the system wide io space constraints */
682 resource = new_resource(dev, 0);
683 resource->base = 0x400;
684 resource->limit = 0xffffUL;
685 resource->flags = IORESOURCE_IO;
686 compute_allocate_resource(&dev->link[0], resource,
687 IORESOURCE_IO, IORESOURCE_IO);
689 /* Initialize the system wide prefetchable memory resources constraints */
690 resource = new_resource(dev, 1);
691 resource->limit = 0xfcffffffffULL;
692 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
693 compute_allocate_resource(&dev->link[0], resource,
694 IORESOURCE_MEM | IORESOURCE_PREFETCH,
695 IORESOURCE_MEM | IORESOURCE_PREFETCH);
697 /* Initialize the system wide memory resources constraints */
698 resource = new_resource(dev, 2);
699 resource->limit = 0xfcffffffffULL;
700 resource->flags = IORESOURCE_MEM;
701 compute_allocate_resource(&dev->link[0], resource,
702 IORESOURCE_MEM | IORESOURCE_PREFETCH,
707 static void ram_resource(device_t dev, unsigned long index,
708 unsigned long basek, unsigned long sizek)
710 struct resource *resource;
715 resource = new_resource(dev, index);
716 resource->base = ((resource_t)basek) << 10;
717 resource->size = ((resource_t)sizek) << 10;
718 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
719 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
722 static void tolm_test(void *gp, struct device *dev, struct resource *new)
724 struct resource **best_p = gp;
725 struct resource *best;
727 if (!best || (best->base > new->base)) {
733 static uint32_t find_pci_tolm(struct bus *bus)
735 struct resource *min;
738 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
740 if (min && tolm > min->base) {
746 #if CONFIG_PCI_64BIT_PREF_MEM == 1
747 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
750 #if HW_MEM_HOLE_SIZEK != 0
752 struct hw_mem_hole_info {
753 unsigned hole_startk;
757 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
759 struct hw_mem_hole_info mem_hole;
762 mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
763 mem_hole.node_id = -1;
765 for (i = 0; i < 8; i++) {
768 base = f1_read_config32(0x40 + (i << 3));
769 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
773 hole = pci_read_config32(__f1_dev[i], 0xf0);
774 if(hole & 1) { // we find the hole
775 mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
776 mem_hole.node_id = i; // record the node No with hole
777 break; // only one hole
781 //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
782 if(mem_hole.node_id==-1) {
783 uint32_t limitk_pri = 0;
785 uint32_t base, limit;
786 unsigned base_k, limit_k;
787 base = f1_read_config32(0x40 + (i << 3));
788 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
792 base_k = (base & 0xffff0000) >> 2;
793 if(limitk_pri != base_k) { // we find the hole
794 mem_hole.hole_startk = limitk_pri;
795 mem_hole.node_id = i;
796 break; //only one hole
799 limit = f1_read_config32(0x44 + (i << 3));
800 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
801 limitk_pri = limit_k;
808 static void disable_hoist_memory(unsigned long hole_startk, int i)
812 uint32_t base, limit;
817 //1. find which node has hole
818 //2. change limit in that node.
819 //3. change base and limit in later node
820 //4. clear that node f0
822 //if there is not mem hole enabled, we need to change it's base instead
824 hole_sizek = (4*1024*1024) - hole_startk;
826 for(ii=7;ii>i;ii--) {
828 base = f1_read_config32(0x40 + (ii << 3));
829 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
832 limit = f1_read_config32(0x44 + (ii << 3));
833 f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
834 f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
836 limit = f1_read_config32(0x44 + (i << 3));
837 f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
839 hoist = pci_read_config32(dev, 0xf0);
841 pci_write_config32(dev, 0xf0, 0);
844 base = pci_read_config32(dev, 0x40 + (i << 3));
845 f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
850 static uint32_t hoist_memory(unsigned long hole_startk, int i)
855 uint32_t base, limit;
859 carry_over = (4*1024*1024) - hole_startk;
861 for(ii=7;ii>i;ii--) {
863 base = f1_read_config32(0x40 + (ii << 3));
864 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
867 limit = f1_read_config32(0x44 + (ii << 3));
868 f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
869 f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
871 limit = f1_read_config32(0x44 + (i << 3));
872 f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
874 base = pci_read_config32(dev, 0x40 + (i << 3));
875 basek = (base & 0xffff0000) >> 2;
876 if(basek == hole_startk) {
877 //don't need set memhole here, because hole off set will be 0, overflow
878 //so need to change base reg instead, new basek will be 4*1024*1024
880 base |= (4*1024*1024)<<2;
881 f1_write_config32(0x40 + (i<<3), base);
885 hoist = /* hole start address */
886 ((hole_startk << 10) & 0xff000000) +
887 /* hole address to memory controller address */
888 (((basek + carry_over) >> 6) & 0x0000ff00) +
892 pci_write_config32(dev, 0xf0, hoist);
899 #if HAVE_HIGH_TABLES==1
900 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
901 extern uint64_t high_tables_base, high_tables_size;
904 static void pci_domain_set_resources(device_t dev)
906 #if CONFIG_PCI_64BIT_PREF_MEM == 1
907 struct resource *io, *mem1, *mem2;
908 struct resource *resource, *last;
910 unsigned long mmio_basek;
913 #if HW_MEM_HOLE_SIZEK != 0
914 struct hw_mem_hole_info mem_hole;
915 unsigned reset_memhole = 1;
919 /* Place the IO devices somewhere safe */
920 io = find_resource(dev, 0);
921 io->base = DEVICE_IO_START;
923 #if CONFIG_PCI_64BIT_PREF_MEM == 1
924 /* Now reallocate the pci resources memory with the
925 * highest addresses I can manage.
927 mem1 = find_resource(dev, 1);
928 mem2 = find_resource(dev, 2);
931 printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
932 mem1->base, mem1->limit, mem1->size, mem1->align);
933 printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
934 mem2->base, mem2->limit, mem2->size, mem2->align);
937 /* See if both resources have roughly the same limits */
938 if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
939 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
941 /* If so place the one with the most stringent alignment first
943 if (mem2->align > mem1->align) {
944 struct resource *tmp;
949 /* Now place the memory as high up as it will go */
950 mem2->base = resource_max(mem2);
951 mem1->limit = mem2->base - 1;
952 mem1->base = resource_max(mem1);
955 /* Place the resources as high up as they will go */
956 mem2->base = resource_max(mem2);
957 mem1->base = resource_max(mem1);
961 printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
962 mem1->base, mem1->limit, mem1->size, mem1->align);
963 printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
964 mem2->base, mem2->limit, mem2->size, mem2->align);
967 last = &dev->resource[dev->resources];
968 for(resource = &dev->resource[0]; resource < last; resource++)
971 resource->flags |= IORESOURCE_ASSIGNED;
972 resource->flags &= ~IORESOURCE_STORED;
974 compute_allocate_resource(&dev->link[0], resource,
975 BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
977 resource->flags |= IORESOURCE_STORED;
978 report_resource_stored(dev, resource, "");
984 pci_tolm = find_pci_tolm(&dev->link[0]);
986 #warning "FIXME handle interleaved nodes"
987 mmio_basek = pci_tolm >> 10;
988 /* Round mmio_basek to something the processor can support */
989 mmio_basek &= ~((1 << 6) -1);
992 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
993 /* Round the mmio hold to 64M */
994 mmio_basek &= ~((64*1024) - 1);
997 #if HW_MEM_HOLE_SIZEK != 0
998 /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
999 * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
1000 * otherwise We reset the hole to the mmio_basek
1002 #if K8_REV_F_SUPPORT == 0
1003 if (!is_cpu_pre_e0()) {
1006 mem_hole = get_hw_mem_hole_info();
1008 if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
1009 mmio_basek = mem_hole.hole_startk;
1013 //mmio_basek = 3*1024*1024; // for debug to meet boundary
1016 if(mem_hole.node_id!=-1) { // We need to select HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
1017 // We need to reset our Mem Hole, because We want more big HOLE than we already set
1018 //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
1019 disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
1022 #if HW_MEM_HOLE_SIZE_AUTO_INC == 1
1023 //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
1025 for (i = 0; i < 8; i++) {
1028 base = f1_read_config32(0x40 + (i << 3));
1029 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
1033 basek = (base & 0xffff0000) >> 2;
1034 if(mmio_basek == basek) {
1035 mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node
1043 #if K8_REV_F_SUPPORT == 0
1050 for(i = 0; i < 8; i++) {
1051 uint32_t base, limit;
1052 unsigned basek, limitk, sizek;
1053 base = f1_read_config32(0x40 + (i << 3));
1054 limit = f1_read_config32(0x44 + (i << 3));
1055 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
1058 basek = (base & 0xffff0000) >> 2;
1059 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
1060 sizek = limitk - basek;
1062 /* see if we need a hole from 0xa0000 to 0xbffff */
1063 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
1064 ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
1066 basek = (8*64)+(16*16);
1067 sizek = limitk - ((8*64)+(16*16));
1072 // printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
1074 /* See if I need to split the region to accomodate pci memory space */
1075 if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
1076 if (basek <= mmio_basek) {
1078 pre_sizek = mmio_basek - basek;
1080 ram_resource(dev, (idx | i), basek, pre_sizek);
1083 #if HAVE_HIGH_TABLES==1
1084 if (i==0 && high_tables_base==0) {
1085 /* Leave some space for ACPI, PIRQ and MP tables */
1086 high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
1087 high_tables_size = HIGH_TABLES_SIZE * 1024;
1088 printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE,
1093 #if HW_MEM_HOLE_SIZEK != 0
1095 #if K8_REV_F_SUPPORT == 0
1096 if(!is_cpu_pre_e0() )
1098 sizek += hoist_memory(mmio_basek,i);
1103 if ((basek + sizek) <= 4*1024*1024) {
1107 basek = 4*1024*1024;
1108 sizek -= (4*1024*1024 - mmio_basek);
1111 /* If sizek == 0, it was split at mmio_basek without a hole.
1112 * Don't create an empty ram_resource.
1115 ram_resource(dev, (idx | i), basek, sizek);
1117 #if HAVE_HIGH_TABLES==1
1118 printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
1119 i, mmio_basek, basek, limitk);
1120 if (i==0 && high_tables_base==0) {
1121 /* Leave some space for ACPI, PIRQ and MP tables */
1122 high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
1123 high_tables_size = HIGH_TABLES_SIZE * 1024;
1127 assign_resources(&dev->link[0]);
1131 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
1135 /* Unmap all of the HT chains */
1136 for(reg = 0xe0; reg <= 0xec; reg += 4) {
1137 f1_write_config32(reg, 0);
1139 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
1141 /* Tune the hypertransport transaction for best performance.
1142 * Including enabling relaxed ordering if it is safe.
1145 for(i = 0; i < FX_DEVS; i++) {
1147 f0_dev = __f0_dev[i];
1148 if (f0_dev && f0_dev->enabled) {
1150 httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
1151 httc &= ~HTTC_RSP_PASS_PW;
1152 if (!dev->link[0].disable_relaxed_ordering) {
1153 httc |= HTTC_RSP_PASS_PW;
1155 printk_spew("%s passpw: %s\n",
1157 (!dev->link[0].disable_relaxed_ordering)?
1158 "enabled":"disabled");
1159 pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
1165 static struct device_operations pci_domain_ops = {
1166 .read_resources = pci_domain_read_resources,
1167 .set_resources = pci_domain_set_resources,
1168 .enable_resources = enable_childrens_resources,
1170 .scan_bus = pci_domain_scan_bus,
1171 .ops_pci_bus = &pci_cf8_conf1,
1174 static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
1176 struct bus *cpu_bus;
1182 int e0_later_single_core;
1183 int disable_siblings;
1186 sysconf.enabled_apic_ext_id = 0;
1187 sysconf.lift_bsp_apicid = 0;
1190 /* Find the bootstrap processors apicid */
1191 bsp_apicid = lapicid();
1192 sysconf.apicid_offset = bsp_apicid;
1194 disable_siblings = !CONFIG_LOGICAL_CPUS;
1195 #if CONFIG_LOGICAL_CPUS == 1
1196 get_option(&disable_siblings, "dual_core");
1199 // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)
1200 // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core
1202 nb_cfg_54 = read_nb_cfg_54();
1204 dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
1206 die("0:18.0 not found?");
1209 sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
1212 if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
1214 sysconf.enabled_apic_ext_id = 1;
1215 if(bsp_apicid == 0) {
1216 /* bsp apic id is not changed */
1217 sysconf.apicid_offset = APIC_ID_OFFSET;
1220 sysconf.lift_bsp_apicid = 1;
1225 /* Find which cpus are present */
1226 cpu_bus = &dev->link[0];
1227 for(i = 0; i < sysconf.nodes; i++) {
1229 struct device_path cpu_path;
1231 /* Find the cpu's pci device */
1232 dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
1234 /* If I am probing things in a weird order
1235 * ensure all of the cpu's pci devices are found.
1239 for(j = 0; j <= 3; j++) {
1240 dev = pci_probe_dev(NULL, dev_mc->bus,
1241 PCI_DEVFN(0x18 + i, j));
1243 /* Ok, We need to set the links for that device.
1244 * otherwise the device under it will not be scanned
1246 dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0));
1250 dev_f0->link[j].link = j;
1251 dev_f0->link[j].dev = dev_f0;
1257 e0_later_single_core = 0;
1258 if (dev && dev->enabled) {
1259 j = pci_read_config32(dev, 0xe8);
1260 j = (j >> 12) & 3; // dev is func 3
1261 printk_debug(" %s siblings=%d\n", dev_path(dev), j);
1264 // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
1265 // ----> you can mixed single core e0 and dual core e0 at any sequence
1266 // That is the typical case
1269 #if K8_REV_F_SUPPORT == 0
1270 e0_later_single_core = is_e0_later_in_bsp(i); // single core
1272 e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
1275 e0_later_single_core = 0;
1277 if(e0_later_single_core) {
1278 printk_debug("\tFound Rev E or Rev F later single core\r\n");
1294 if(e0_later_single_core || disable_siblings) {
1301 jj = 0; // if create cpu core1 path in amd_siblings by core0
1304 for (j = 0; j <=jj; j++ ) {
1306 /* Build the cpu device path */
1307 cpu_path.type = DEVICE_PATH_APIC;
1308 cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
1310 /* See if I can find the cpu */
1311 cpu = find_dev_path(cpu_bus, &cpu_path);
1313 /* Enable the cpu if I have the processor */
1314 if (dev && dev->enabled) {
1316 cpu = alloc_dev(cpu_bus, &cpu_path);
1323 /* Disable the cpu if I don't have the processor */
1324 if (cpu && (!dev || !dev->enabled)) {
1328 /* Report what I have done */
1330 cpu->path.apic.node_id = i;
1331 cpu->path.apic.core_id = j;
1332 if(sysconf.enabled_apic_ext_id) {
1333 if(sysconf.lift_bsp_apicid) {
1334 cpu->path.apic.apic_id += sysconf.apicid_offset;
1337 if (cpu->path.apic.apic_id != 0)
1338 cpu->path.apic.apic_id += sysconf.apicid_offset;
1341 printk_debug("CPU: %s %s\n",
1342 dev_path(cpu), cpu->enabled?"enabled":"disabled");
1350 static void cpu_bus_init(device_t dev)
1352 initialize_cpus(&dev->link[0]);
1355 static void cpu_bus_noop(device_t dev)
1359 static struct device_operations cpu_bus_ops = {
1360 .read_resources = cpu_bus_noop,
1361 .set_resources = cpu_bus_noop,
1362 .enable_resources = cpu_bus_noop,
1363 .init = cpu_bus_init,
1364 .scan_bus = cpu_bus_scan,
1367 static void root_complex_enable_dev(struct device *dev)
1369 /* Set the operations if it is a special bus type */
1370 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
1371 dev->ops = &pci_domain_ops;
1373 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
1374 dev->ops = &cpu_bus_ops;
1378 struct chip_operations northbridge_amd_amdk8_root_complex_ops = {
1379 CHIP_NAME("AMD K8 Root Complex")
1380 .enable_dev = root_complex_enable_dev,