src/northbridge/amd/amdk8/northbridge.c

   1 /* This should be done by Eric
   2         2004.12 yhlu add dual core support
   3         2005.01 yhlu add support move apic before pci_domain in MB Config.lb
   4         2005.02 yhlu add e0 memory hole support
   5         2005.11 yhlu add put sb ht chain on bus 0
   6 */
   7
   8 #include <console/console.h>
   9 #include <arch/io.h>
  10 #include <stdint.h>
  11 #include <device/device.h>
  12 #include <device/pci.h>
  13 #include <device/pci_ids.h>
  14 #include <device/hypertransport.h>
  15 #include <stdlib.h>
  16 #include <string.h>
  17 #include <bitops.h>
  18 #include <cpu/cpu.h>
  19
  20 #include <cpu/x86/lapic.h>
  21
  22 #include <cpu/amd/multicore.h>
  23 #if CONFIG_LOGICAL_CPUS==1
  24 #include <pc80/mc146818rtc.h>
  25 #endif
  26
  27 #include "chip.h"
  28 #include "root_complex/chip.h"
  29 #include "northbridge.h"
  30
  31 #include "amdk8.h"
  32
  33 #include <cpu/amd/model_fxx_rev.h>
  34
  35 #include <cpu/amd/amdk8_sysconf.h>
  36
  37 struct amdk8_sysconf_t sysconf;
  38
  39 #define MAX_FX_DEVS 8
  40 static device_t __f0_dev[MAX_FX_DEVS];
  41 static device_t __f1_dev[MAX_FX_DEVS];
  42 static unsigned fx_devs=0;
  43
  44 static void get_fx_devs(void)
  45 {
  46         int i;
  47         for(i = 0; i < MAX_FX_DEVS; i++) {
  48                 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
  49                 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
  50                 if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
  51                         fx_devs = i+1;
  52         }
  53         if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
  54                 die("Cannot find 0:0x18.[0|1]\n");
  55         }
  56 }
  57
  58 static u32 f1_read_config32(unsigned reg)
  59 {
  60         if (fx_devs == 0)
  61                 get_fx_devs();
  62         return pci_read_config32(__f1_dev[0], reg);
  63 }
  64
  65 static void f1_write_config32(unsigned reg, u32 value)
  66 {
  67         int i;
  68         if (fx_devs == 0)
  69                 get_fx_devs();
  70         for(i = 0; i < fx_devs; i++) {
  71                 device_t dev;
  72                 dev = __f1_dev[i];
  73                 if (dev && dev->enabled) {
  74                         pci_write_config32(dev, reg, value);
  75                 }
  76         }
  77 }
  78
  79 static u32 amdk8_nodeid(device_t dev)
  80 {
  81         return (dev->path.pci.devfn >> 3) - 0x18;
  82 }
  83
  84 static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink,
  85                                 u32 max, u32 offset_unitid)
  86 {
  87
  88                 u32 link_type;
  89                 int i;
  90                 u32 busses, config_busses;
  91                 u32 free_reg, config_reg;
  92                 u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
  93                 u32 max_bus;
  94                 u32 min_bus;
  95                 u32 max_devfn;
  96
  97                 link->cap = 0x80 + (link_num *0x20);
  98                 do {
  99                         link_type = pci_read_config32(dev, link->cap + 0x18);
 100                 } while(link_type & ConnectionPending);
 101                 if (!(link_type & LinkConnected)) {
 102                         return max;
 103                 }
 104                 do {
 105                         link_type = pci_read_config32(dev, link->cap + 0x18);
 106                 } while(!(link_type & InitComplete));
 107                 if (!(link_type & NonCoherent)) {
 108                         return max;
 109                 }
 110                 /* See if there is an available configuration space mapping
 111                  * register in function 1.
 112                  */
 113                 free_reg = 0;
 114                 for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
 115                         u32 config;
 116                         config = f1_read_config32(config_reg);
 117                         if (!free_reg && ((config & 3) == 0)) {
 118                                 free_reg = config_reg;
 119                                 continue;
 120                         }
 121                         if (((config & 3) == 3) &&
 122                                 (((config >> 4) & 7) == nodeid) &&
 123                                 (((config >> 8) & 3) == link_num)) {
 124                                 break;
 125                         }
 126                 }
 127                 if (free_reg && (config_reg > 0xec)) {
 128                         config_reg = free_reg;
 129                 }
 130                 /* If we can't find an available configuration space mapping
 131                  * register skip this bus
 132                  */
 133                 if (config_reg > 0xec) {
 134                         return max;
 135                 }
 136
 137                 /* Set up the primary, secondary and subordinate bus numbers.
 138                  * We have no idea how many busses are behind this bridge yet,
 139                  * so we set the subordinate bus number to 0xff for the moment.
 140                  */
 141 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
 142                 // first chain will on bus 0
 143                 if((nodeid == 0) && (sblink==link_num)) { // actually max is 0 here
 144                         min_bus = max;
 145                 }
 146         #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
 147                 // second chain will be on 0x40, third 0x80, forth 0xc0
 148                 else {
 149                         min_bus = ((max>>6) + 1) * 0x40;
 150                 }
 151                 max = min_bus;
 152         #else
 153                 //other ...
 154                 else {
 155                         min_bus = ++max;
 156                 }
 157         #endif
 158 #else
 159                 min_bus = ++max;
 160 #endif
 161                 max_bus = 0xff;
 162
 163                 link->secondary = min_bus;
 164                 link->subordinate = max_bus;
 165
 166                 /* Read the existing primary/secondary/subordinate bus
 167                  * number configuration.
 168                  */
 169                 busses = pci_read_config32(dev, link->cap + 0x14);
 170                 config_busses = f1_read_config32(config_reg);
 171
 172                 /* Configure the bus numbers for this bridge: the configuration
 173                  * transactions will not be propagates by the bridge if it is
 174                  * not correctly configured
 175                  */
 176                 busses &= 0xff000000;
 177                 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
 178                         ((unsigned int)(link->secondary) << 8) |
 179                         ((unsigned int)(link->subordinate) << 16));
 180                 pci_write_config32(dev, link->cap + 0x14, busses);
 181
 182                 config_busses &= 0x000fc88;
 183                 config_busses |=
 184                         (3 << 0) |  /* rw enable, no device compare */
 185                         (( nodeid & 7) << 4) |
 186                         (( link_num & 3 ) << 8) |
 187                         ((link->secondary) << 16) |
 188                         ((link->subordinate) << 24);
 189                 f1_write_config32(config_reg, config_busses);
 190
 191                 /* Now we can scan all of the subordinate busses i.e. the
 192                  * chain on the hypertranport link
 193                  */
 194                 for(i=0;i<4;i++) {
 195                         ht_unitid_base[i] = 0x20;
 196                 }
 197
 198                 if (min_bus == 0)
 199                         max_devfn = (0x17<<3) | 7;
 200                 else
 201                         max_devfn = (0x1f<<3) | 7;
 202
 203                 max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unitid);
 204
 205                 /* We know the number of busses behind this bridge.  Set the
 206                  * subordinate bus number to it's real value
 207                  */
 208                 link->subordinate = max;
 209                 busses = (busses & 0xff00ffff) |
 210                         ((unsigned int) (link->subordinate) << 16);
 211                 pci_write_config32(dev, link->cap + 0x14, busses);
 212
 213                 config_busses = (config_busses & 0x00ffffff) |
 214                         (link->subordinate << 24);
 215                 f1_write_config32(config_reg, config_busses);
 216
 217                 {
 218                         // use config_reg and ht_unitid_base to update hcdn_reg
 219                         int index;
 220                         u32 temp = 0;
 221                         index = (config_reg-0xe0) >> 2;
 222                         for(i=0;i<4;i++) {
 223                                 temp |= (ht_unitid_base[i] & 0xff) << (i*8);
 224                         }
 225
 226                         sysconf.hcdn_reg[index] = temp;
 227
 228                 }
 229         return max;
 230 }
 231
 232 static unsigned amdk8_scan_chains(device_t dev, unsigned max)
 233 {
 234         unsigned nodeid;
 235         struct bus *link;
 236         unsigned sblink = 0;
 237         unsigned offset_unitid = 0;
 238
 239         nodeid = amdk8_nodeid(dev);
 240
 241         if(nodeid==0) {
 242                 sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
 243 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
 244         #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
 245                 offset_unitid = 1;
 246         #endif
 247                 for (link = dev->link_list; link; link = link->next)
 248                         if (link->link_num == sblink)
 249                                 max = amdk8_scan_chain(dev, nodeid, link, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
 250 #endif
 251         }
 252
 253         for (link = dev->link_list; link; link = link->next) {
 254 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
 255                 if( (nodeid == 0) && (sblink == link->link_num) ) continue; //already done
 256 #endif
 257                 offset_unitid = 0;
 258                 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
 259                         #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
 260                         if((nodeid == 0) && (sblink == link->link_num))
 261                         #endif
 262                                 offset_unitid = 1;
 263                 #endif
 264
 265                 max = amdk8_scan_chain(dev, nodeid, link, link->link_num, sblink, max, offset_unitid);
 266         }
 267         return max;
 268 }
 269
 270
 271 static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
 272                         unsigned goal_link)
 273 {
 274         struct resource *res;
 275         unsigned nodeid, link = 0;
 276         int result;
 277         res = 0;
 278         for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
 279                 device_t dev;
 280                 dev = __f0_dev[nodeid];
 281                 if (!dev)
 282                         continue;
 283                 for(link = 0; !res && (link < 3); link++) {
 284                         res = probe_resource(dev, IOINDEX(0x100 + reg, link));
 285                 }
 286         }
 287         result = 2;
 288         if (res) {
 289                 result = 0;
 290                 if (    (goal_link == (link - 1)) &&
 291                         (goal_nodeid == (nodeid - 1)) &&
 292                         (res->flags <= 1)) {
 293                         result = 1;
 294                 }
 295         }
 296         return result;
 297 }
 298
 299 static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link,
 300                                unsigned min, unsigned max)
 301 {
 302         unsigned resource;
 303         unsigned free_reg, reg;
 304         resource = 0;
 305         free_reg = 0;
 306         for(reg = min; reg <= max; reg += 0x8) {
 307                 int result;
 308                 result = reg_useable(reg, dev, nodeid, link);
 309                 if (result == 1) {
 310                         /* I have been allocated this one */
 311                         break;
 312                 }
 313                 else if (result > 1) {
 314                         /* I have a free register pair */
 315                         free_reg = reg;
 316                 }
 317         }
 318         if (reg > max) {
 319                 reg = free_reg;
 320         }
 321         if (reg > 0) {
 322                 resource = IOINDEX(0x100 + reg, link);
 323         }
 324         return resource;
 325 }
 326
 327 static unsigned amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
 328 {
 329         return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8);
 330 }
 331
 332 static unsigned amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
 333 {
 334         return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8);
 335 }
 336
 337 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
 338 {
 339         struct resource *resource;
 340
 341         /* Initialize the io space constraints on the current bus */
 342         resource = new_resource(dev, IOINDEX(0, link));
 343         if (resource) {
 344                 resource->base  = 0;
 345                 resource->size  = 0;
 346                 resource->align = log2(HT_IO_HOST_ALIGN);
 347                 resource->gran  = log2(HT_IO_HOST_ALIGN);
 348                 resource->limit = 0xffffUL;
 349                 resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
 350         }
 351
 352         /* Initialize the prefetchable memory constraints on the current bus */
 353         resource = new_resource(dev, IOINDEX(2, link));
 354         if (resource) {
 355                 resource->base = 0;
 356                 resource->size = 0;
 357                 resource->align = log2(HT_MEM_HOST_ALIGN);
 358                 resource->gran = log2(HT_MEM_HOST_ALIGN);
 359                 resource->limit = 0xffffffffffULL;
 360                 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 361                 resource->flags |= IORESOURCE_BRIDGE;
 362         }
 363
 364         /* Initialize the memory constraints on the current bus */
 365         resource = new_resource(dev, IOINDEX(1, link));
 366         if (resource) {
 367                 resource->base = 0;
 368                 resource->size = 0;
 369                 resource->align = log2(HT_MEM_HOST_ALIGN);
 370                 resource->gran = log2(HT_MEM_HOST_ALIGN);
 371                 resource->limit = 0xffffffffULL;
 372                 resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
 373         }
 374 }
 375
 376 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid);
 377
 378 static void amdk8_read_resources(device_t dev)
 379 {
 380         unsigned nodeid;
 381         struct bus *link;
 382         nodeid = amdk8_nodeid(dev);
 383         for(link = dev->link_list; link; link = link->next) {
 384                 if (link->children) {
 385                         amdk8_link_read_bases(dev, nodeid, link->link_num);
 386                 }
 387         }
 388         amdk8_create_vga_resource(dev, nodeid);
 389 }
 390
 391 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
 392 {
 393         struct bus *link;
 394         resource_t rbase, rend;
 395         unsigned reg, link_num;
 396         char buf[50];
 397
 398         /* Make certain the resource has actually been set */
 399         if (!(resource->flags & IORESOURCE_ASSIGNED)) {
 400                 printk(BIOS_ERR, "%s: can't set unassigned resource @%lx %lx\n",
 401                            __func__, resource->index, resource->flags);
 402                 return;
 403         }
 404
 405         /* If I have already stored this resource don't worry about it */
 406         if (resource->flags & IORESOURCE_STORED) {
 407                 printk(BIOS_ERR, "%s: can't set stored resource @%lx %lx\n", __func__,
 408                            resource->index, resource->flags);
 409                 return;
 410         }
 411
 412         /* Only handle PCI memory and IO resources */
 413         if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
 414                 return;
 415
 416         /* Ensure I am actually looking at a resource of function 1 */
 417         if (resource->index < 0x100) {
 418                 return;
 419         }
 420
 421         if (resource->size == 0)
 422                 return;
 423
 424         /* Get the base address */
 425         rbase = resource->base;
 426
 427         /* Get the limit (rounded up) */
 428         rend  = resource_end(resource);
 429
 430         /* Get the register and link */
 431         reg  = resource->index & 0xfc;
 432         link_num = IOINDEX_LINK(resource->index);
 433
 434         for (link = dev->link_list; link; link = link->next)
 435                 if (link->link_num == link_num)
 436                         break;
 437
 438         if (link == NULL) {
 439                 printk(BIOS_ERR, "%s: can't find link %x for %lx\n", __func__,
 440                            link_num, resource->index);
 441                 return;
 442         }
 443
 444         if (resource->flags & IORESOURCE_IO) {
 445                 u32 base, limit;
 446                 base  = f1_read_config32(reg);
 447                 limit = f1_read_config32(reg + 0x4);
 448                 base  &= 0xfe000fcc;
 449                 base  |= rbase  & 0x01fff000;
 450                 base  |= 3;
 451                 limit &= 0xfe000fc8;
 452                 limit |= rend & 0x01fff000;
 453                 limit |= (link_num & 3) << 4;
 454                 limit |= (nodeid & 7);
 455
 456                 if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 457                         printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
 458                                     __func__, dev_path(dev), link_num);
 459                         base |= PCI_IO_BASE_VGA_EN;
 460                 }
 461                 if (link->bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
 462                         base |= PCI_IO_BASE_NO_ISA;
 463                 }
 464
 465                 f1_write_config32(reg + 0x4, limit);
 466                 f1_write_config32(reg, base);
 467         }
 468         else if (resource->flags & IORESOURCE_MEM) {
 469                 u32 base, limit;
 470                 base  = f1_read_config32(reg);
 471                 limit = f1_read_config32(reg + 0x4);
 472                 base  &= 0x000000f0;
 473                 base  |= (rbase >> 8) & 0xffffff00;
 474                 base  |= 3;
 475                 limit &= 0x00000048;
 476                 limit |= (rend >> 8) & 0xffffff00;
 477                 limit |= (link_num & 3) << 4;
 478                 limit |= (nodeid & 7);
 479                 f1_write_config32(reg + 0x4, limit);
 480                 f1_write_config32(reg, base);
 481         }
 482         resource->flags |= IORESOURCE_STORED;
 483         sprintf(buf, " <node %x link %x>",
 484                 nodeid, link_num);
 485         report_resource_stored(dev, resource, buf);
 486 }
 487
 488 #if CONFIG_CONSOLE_VGA_MULTI == 1
 489 extern device_t vga_pri;        // the primary vga device, defined in device.c
 490 #endif
 491
 492 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
 493 {
 494         struct resource *resource;
 495         struct bus *link;
 496
 497         /* find out which link the VGA card is connected,
 498          * we only deal with the 'first' vga card */
 499         for (link = dev->link_list; link; link = link->next) {
 500                 if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 501 #if CONFIG_CONSOLE_VGA_MULTI == 1
 502                         printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary,
 503                                 link->secondary,link->subordinate);
 504                         /* We need to make sure the vga_pri is under the link */
 505                         if((vga_pri->bus->secondary >= link->secondary ) &&
 506                                 (vga_pri->bus->secondary <= link->subordinate )
 507                         )
 508 #endif
 509                         break;
 510                 }
 511         }
 512
 513         /* no VGA card installed */
 514         if (link == NULL)
 515                 return;
 516
 517         printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num);
 518
 519         /* allocate a temp resource for the legacy VGA buffer */
 520         resource = new_resource(dev, IOINDEX(4, link->link_num));
 521         if(!resource){
 522                 printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev));
 523                 return;
 524         }
 525         resource->base = 0xa0000;
 526         resource->size = 0x20000;
 527         resource->limit = 0xffffffff;
 528         resource->flags = IORESOURCE_FIXED | IORESOURCE_MEM |
 529                           IORESOURCE_ASSIGNED;
 530 }
 531
 532 static void amdk8_set_resources(device_t dev)
 533 {
 534         unsigned nodeid;
 535         struct bus *bus;
 536         struct resource *res;
 537
 538         /* Find the nodeid */
 539         nodeid = amdk8_nodeid(dev);
 540
 541         /* Set each resource we have found */
 542         for(res = dev->resource_list; res; res = res->next) {
 543                 struct resource *old = NULL;
 544                 unsigned index;
 545
 546                 if (res->size == 0) /* No need to allocate registers. */
 547                         continue;
 548
 549                 if (res->flags & IORESOURCE_IO)
 550                         index = amdk8_find_iopair(dev, nodeid,
 551                                                   IOINDEX_LINK(res->index));
 552                 else
 553                         index = amdk8_find_mempair(dev, nodeid,
 554                                                    IOINDEX_LINK(res->index));
 555
 556                 old = probe_resource(dev, index);
 557                 if (old) {
 558                         res->index = old->index;
 559                         old->index = 0;
 560                         old->flags = 0;
 561                 }
 562                 else
 563                         res->index = index;
 564
 565                 amdk8_set_resource(dev, res, nodeid);
 566         }
 567
 568         compact_resources(dev);
 569
 570         for(bus = dev->link_list; bus; bus = bus->next) {
 571                 if (bus->children) {
 572                         assign_resources(bus);
 573                 }
 574         }
 575 }
 576
 577 static void mcf0_control_init(struct device *dev)
 578 {
 579 #if 0
 580         printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. ");
 581 #endif
 582 #if 0
 583         printk(BIOS_DEBUG, "done.\n");
 584 #endif
 585 }
 586
 587 static struct device_operations northbridge_operations = {
 588         .read_resources   = amdk8_read_resources,
 589         .set_resources    = amdk8_set_resources,
 590         .enable_resources = pci_dev_enable_resources,
 591         .init             = mcf0_control_init,
 592         .scan_bus         = amdk8_scan_chains,
 593         .enable           = 0,
 594         .ops_pci          = 0,
 595 };
 596
 597
 598 static const struct pci_driver mcf0_driver __pci_driver = {
 599         .ops    = &northbridge_operations,
 600         .vendor = PCI_VENDOR_ID_AMD,
 601         .device = 0x1100,
 602 };
 603
 604 struct chip_operations northbridge_amd_amdk8_ops = {
 605         CHIP_NAME("AMD K8 Northbridge")
 606         .enable_dev = 0,
 607 };
 608
 609 static void amdk8_domain_read_resources(device_t dev)
 610 {
 611         unsigned reg;
 612
 613         /* Find the already assigned resource pairs */
 614         get_fx_devs();
 615         for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
 616                 u32 base, limit;
 617                 base  = f1_read_config32(reg);
 618                 limit = f1_read_config32(reg + 0x04);
 619                 /* Is this register allocated? */
 620                 if ((base & 3) != 0) {
 621                         unsigned nodeid, reg_link;
 622                         device_t reg_dev;
 623                         nodeid = limit & 7;
 624                         reg_link = (limit >> 4) & 3;
 625                         reg_dev = __f0_dev[nodeid];
 626                         if (reg_dev) {
 627                                 /* Reserve the resource  */
 628                                 struct resource *res;
 629                                 res = new_resource(reg_dev, IOINDEX(0x100 + reg, reg_link));
 630                                 if (res) {
 631                                         res->base = base;
 632                                         res->limit = limit;
 633                                         res->flags = 1;
 634                                 }
 635                         }
 636                 }
 637         }
 638
 639         pci_domain_read_resources(dev);
 640
 641 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 642         /* Initialize the system wide prefetchable memory resources constraints */
 643         resource = new_resource(dev, 2);
 644         resource->limit = 0xfcffffffffULL;
 645         resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 646 #endif
 647 }
 648
 649 static void my_tolm_test(void *gp, struct device *dev, struct resource *new)
 650 {
 651         struct resource **best_p = gp;
 652         struct resource *best;
 653         best = *best_p;
 654         /* Skip VGA. */
 655         if (!best || (best->base > new->base && new->base > 0xa0000)) {
 656                 best = new;
 657         }
 658         *best_p = best;
 659 }
 660
 661 static u32 my_find_pci_tolm(struct bus *bus)
 662 {
 663         struct resource *min;
 664         u32 tolm;
 665         min = 0;
 666         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, my_tolm_test, &min);
 667         tolm = 0xffffffffUL;
 668         if (min && tolm > min->base) {
 669                 tolm = min->base;
 670         }
 671         return tolm;
 672 }
 673
 674 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 675
 676 struct hw_mem_hole_info {
 677         unsigned hole_startk;
 678         int node_id;
 679 };
 680
 681 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 682 {
 683                 struct hw_mem_hole_info mem_hole;
 684                 int i;
 685
 686                 mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
 687                 mem_hole.node_id = -1;
 688
 689                 for (i = 0; i < fx_devs; i++) {
 690                         u32 base;
 691                         u32 hole;
 692                         base  = f1_read_config32(0x40 + (i << 3));
 693                         if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 694                                 continue;
 695                         }
 696
 697                         hole = pci_read_config32(__f1_dev[i], 0xf0);
 698                         if(hole & 1) { // we find the hole
 699                                 mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
 700                                 mem_hole.node_id = i; // record the node No with hole
 701                                 break; // only one hole
 702                         }
 703                 }
 704
 705                 //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
 706                 if(mem_hole.node_id==-1) {
 707                         u32 limitk_pri = 0;
 708                         for(i=0; i<8; i++) {
 709                                 u32 base, limit;
 710                                 unsigned base_k, limit_k;
 711                                 base  = f1_read_config32(0x40 + (i << 3));
 712                                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 713                                         continue;
 714                                 }
 715
 716                                 base_k = (base & 0xffff0000) >> 2;
 717                                 if(limitk_pri != base_k) { // we find the hole
 718                                         mem_hole.hole_startk = limitk_pri;
 719                                         mem_hole.node_id = i;
 720                                         break; //only one hole
 721                                 }
 722
 723                                 limit = f1_read_config32(0x44 + (i << 3));
 724                                 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
 725                                 limitk_pri = limit_k;
 726                         }
 727                 }
 728                 return mem_hole;
 729 }
 730
 731 static void disable_hoist_memory(unsigned long hole_startk, int node_id)
 732 {
 733         int i;
 734         device_t dev;
 735         u32 base, limit;
 736         u32 hoist;
 737         u32 hole_sizek;
 738
 739
 740         //1. find which node has hole
 741         //2. change limit in that node.
 742         //3. change base and limit in later node
 743         //4. clear that node f0
 744
 745         //if there is not mem hole enabled, we need to change it's base instead
 746
 747         hole_sizek = (4*1024*1024) - hole_startk;
 748
 749         for(i=7;i>node_id;i--) {
 750
 751                 base  = f1_read_config32(0x40 + (i << 3));
 752                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 753                         continue;
 754                 }
 755                 limit = f1_read_config32(0x44 + (i << 3));
 756                 f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
 757                 f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
 758         }
 759         limit = f1_read_config32(0x44 + (node_id << 3));
 760         f1_write_config32(0x44 + (node_id << 3),limit - (hole_sizek << 2));
 761         dev = __f1_dev[node_id];
 762         if (dev == NULL) {
 763                 printk(BIOS_ERR, "%s: node %x is NULL!\n", __func__, node_id);
 764                 return;
 765         }
 766         hoist = pci_read_config32(dev, 0xf0);
 767         if(hoist & 1) {
 768                 pci_write_config32(dev, 0xf0, 0);
 769         } else {
 770                 base = pci_read_config32(dev, 0x40 + (node_id << 3));
 771                 f1_write_config32(0x40 + (node_id << 3),base - (hole_sizek << 2));
 772         }
 773 }
 774
 775 static u32 hoist_memory(unsigned long hole_startk, int node_id)
 776 {
 777         int i;
 778         u32 carry_over;
 779         device_t dev;
 780         u32 base, limit;
 781         u32 basek;
 782         u32 hoist;
 783
 784         carry_over = (4*1024*1024) - hole_startk;
 785
 786         for(i=7;i>node_id;i--) {
 787
 788                 base  = f1_read_config32(0x40 + (i << 3));
 789                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 790                         continue;
 791                 }
 792                 limit = f1_read_config32(0x44 + (i << 3));
 793                 f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
 794                 f1_write_config32(0x40 + (i << 3),base + (carry_over << 2));
 795         }
 796         limit = f1_read_config32(0x44 + (node_id << 3));
 797         f1_write_config32(0x44 + (node_id << 3),limit + (carry_over << 2));
 798         dev = __f1_dev[node_id];
 799         base  = pci_read_config32(dev, 0x40 + (node_id << 3));
 800         basek  = (base & 0xffff0000) >> 2;
 801         if(basek == hole_startk) {
 802                 //don't need set memhole here, because hole off set will be 0, overflow
 803                 //so need to change base reg instead, new basek will be 4*1024*1024
 804                 base &= 0x0000ffff;
 805                 base |= (4*1024*1024)<<2;
 806                 f1_write_config32(0x40 + (node_id<<3), base);
 807         }
 808         else if (dev)
 809         {
 810                 hoist = /* hole start address */
 811                         ((hole_startk << 10) & 0xff000000) +
 812                         /* hole address to memory controller address */
 813                         (((basek + carry_over) >> 6) & 0x0000ff00) +
 814                         /* enable */
 815                         1;
 816
 817                 pci_write_config32(dev, 0xf0, hoist);
 818         }
 819
 820         return carry_over;
 821 }
 822 #endif
 823
 824 #if CONFIG_WRITE_HIGH_TABLES==1
 825 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
 826 extern uint64_t high_tables_base, high_tables_size;
 827 #if CONFIG_GFXUMA == 1
 828 extern uint64_t uma_memory_base, uma_memory_size;
 829 #endif
 830 #endif
 831
 832 static void amdk8_domain_set_resources(device_t dev)
 833 {
 834 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 835         struct resource *io, *mem1, *mem2;
 836         struct resource *res;
 837 #endif
 838         unsigned long mmio_basek;
 839         u32 pci_tolm;
 840         int i, idx;
 841 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 842         struct hw_mem_hole_info mem_hole;
 843         u32 reset_memhole = 1;
 844 #endif
 845
 846 #if 0
 847         /* Place the IO devices somewhere safe */
 848         io = find_resource(dev, 0);
 849         io->base = DEVICE_IO_START;
 850 #endif
 851 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 852         /* Now reallocate the pci resources memory with the
 853          * highest addresses I can manage.
 854          */
 855         mem1 = find_resource(dev, 1);
 856         mem2 = find_resource(dev, 2);
 857
 858 #if 1
 859         printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 860                 mem1->base, mem1->limit, mem1->size, mem1->align);
 861         printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 862                 mem2->base, mem2->limit, mem2->size, mem2->align);
 863 #endif
 864
 865         /* See if both resources have roughly the same limits */
 866         if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
 867                 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
 868         {
 869                 /* If so place the one with the most stringent alignment first
 870                  */
 871                 if (mem2->align > mem1->align) {
 872                         struct resource *tmp;
 873                         tmp = mem1;
 874                         mem1 = mem2;
 875                         mem2 = tmp;
 876                 }
 877                 /* Now place the memory as high up as it will go */
 878                 mem2->base = resource_max(mem2);
 879                 mem1->limit = mem2->base - 1;
 880                 mem1->base = resource_max(mem1);
 881         }
 882         else {
 883                 /* Place the resources as high up as they will go */
 884                 mem2->base = resource_max(mem2);
 885                 mem1->base = resource_max(mem1);
 886         }
 887
 888 #if 1
 889         printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 890                 mem1->base, mem1->limit, mem1->size, mem1->align);
 891         printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 892                 mem2->base, mem2->limit, mem2->size, mem2->align);
 893 #endif
 894
 895         for(res = dev->resource_list; res; res = res->next)
 896         {
 897                 res->flags |= IORESOURCE_ASSIGNED;
 898                 res->flags |= IORESOURCE_STORED;
 899                 report_resource_stored(dev, res, "");
 900         }
 901 #endif
 902
 903         pci_tolm = my_find_pci_tolm(dev->link_list);
 904
 905         // FIXME handle interleaved nodes. If you fix this here, please fix
 906         // amdfam10, too.
 907         mmio_basek = pci_tolm >> 10;
 908         /* Round mmio_basek to something the processor can support */
 909         mmio_basek &= ~((1 << 6) -1);
 910
 911         // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
 912         // MMIO hole. If you fix this here, please fix amdfam10, too.
 913         /* Round the mmio hole to 64M */
 914         mmio_basek &= ~((64*1024) - 1);
 915
 916 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 917         /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
 918          * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
 919          * otherwise We reset the hole to the mmio_basek
 920          */
 921         #if CONFIG_K8_REV_F_SUPPORT == 0
 922                 if (!is_cpu_pre_e0()) {
 923         #endif
 924
 925                 mem_hole = get_hw_mem_hole_info();
 926
 927                 if ((mem_hole.node_id !=  -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
 928                         mmio_basek = mem_hole.hole_startk;
 929                         reset_memhole = 0;
 930                 }
 931
 932                 //mmio_basek = 3*1024*1024; // for debug to meet boundary
 933
 934                 if(reset_memhole) {
 935                         if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
 936                                // We need to reset our Mem Hole, because We want more big HOLE than we already set
 937                                //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
 938                                 disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
 939                         }
 940
 941                 #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
 942                         //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
 943                         u32 basek_pri;
 944                         for (i = 0; i < fx_devs; i++) {
 945                                 u32 base;
 946                                 u32 basek;
 947                                 base  = f1_read_config32(0x40 + (i << 3));
 948                                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 949                                         continue;
 950                                 }
 951
 952                                 basek = (base & 0xffff0000) >> 2;
 953                                 if(mmio_basek == basek) {
 954                                         mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node
 955                                         break;
 956                                 }
 957                                 basek_pri = basek;
 958                         }
 959                 #endif
 960                 }
 961
 962 #if CONFIG_K8_REV_F_SUPPORT == 0
 963         } // is_cpu_pre_e0
 964 #endif
 965
 966 #endif
 967
 968         idx = 0x10;
 969         for(i = 0; i < fx_devs; i++) {
 970                 u32 base, limit;
 971                 u32 basek, limitk, sizek;
 972                 base  = f1_read_config32(0x40 + (i << 3));
 973                 limit = f1_read_config32(0x44 + (i << 3));
 974                 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 975                         continue;
 976                 }
 977                 basek = (base & 0xffff0000) >> 2;
 978                 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
 979                 sizek = limitk - basek;
 980
 981                 /* see if we need a hole from 0xa0000 to 0xbffff */
 982                 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
 983                         ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
 984                         idx += 0x10;
 985                         basek = (8*64)+(16*16);
 986                         sizek = limitk - ((8*64)+(16*16));
 987
 988                 }
 989
 990
 991 #if CONFIG_GFXUMA == 1
 992                 printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
 993                 if ((uma_memory_base >> 10) < mmio_basek)
 994                         printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i);
 995 #else
 996 //              printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
 997 #endif
 998
 999                 /* See if I need to split the region to accomodate pci memory space */
1000                 if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
1001                         if (basek <= mmio_basek) {
1002                                 unsigned pre_sizek;
1003                                 pre_sizek = mmio_basek - basek;
1004                                 if(pre_sizek>0) {
1005                                         ram_resource(dev, (idx | i), basek, pre_sizek);
1006                                         idx += 0x10;
1007                                         sizek -= pre_sizek;
1008 #if CONFIG_WRITE_HIGH_TABLES==1
1009                                         if (high_tables_base==0) {
1010                                         /* Leave some space for ACPI, PIRQ and MP tables */
1011 #if CONFIG_GFXUMA == 1
1012                                                 high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
1013 #else
1014                                                 high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
1015 #endif
1016                                                 high_tables_size = HIGH_TABLES_SIZE * 1024;
1017                                                 printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
1018                                                              high_tables_base);
1019                                         }
1020 #endif
1021                                 }
1022                                 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
1023                                 if(reset_memhole)
1024                                         #if CONFIG_K8_REV_F_SUPPORT == 0
1025                                         if(!is_cpu_pre_e0() )
1026                                         #endif
1027                                                  sizek += hoist_memory(mmio_basek,i);
1028                                 #endif
1029
1030                                 basek = mmio_basek;
1031                         }
1032                         if ((basek + sizek) <= 4*1024*1024) {
1033                                 sizek = 0;
1034                         }
1035                         else {
1036                                 basek = 4*1024*1024;
1037                                 sizek -= (4*1024*1024 - mmio_basek);
1038                         }
1039                 }
1040                 /* If sizek == 0, it was split at mmio_basek without a hole.
1041                  * Don't create an empty ram_resource.
1042                  */
1043                 if (sizek)
1044                         ram_resource(dev, (idx | i), basek, sizek);
1045                 idx += 0x10;
1046 #if CONFIG_WRITE_HIGH_TABLES==1
1047                 printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
1048                              i, mmio_basek, basek, limitk);
1049                 if (high_tables_base==0) {
1050                 /* Leave some space for ACPI, PIRQ and MP tables */
1051 #if CONFIG_GFXUMA == 1
1052                         high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
1053 #else
1054                         high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
1055 #endif
1056                         high_tables_size = HIGH_TABLES_SIZE * 1024;
1057                 }
1058 #endif
1059         }
1060         assign_resources(dev->link_list);
1061
1062 }
1063
1064 static u32 amdk8_domain_scan_bus(device_t dev, u32 max)
1065 {
1066         u32 reg;
1067         int i;
1068         /* Unmap all of the HT chains */
1069         for(reg = 0xe0; reg <= 0xec; reg += 4) {
1070                 f1_write_config32(reg, 0);
1071         }
1072         max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max);
1073
1074         /* Tune the hypertransport transaction for best performance.
1075          * Including enabling relaxed ordering if it is safe.
1076          */
1077         get_fx_devs();
1078         for(i = 0; i < fx_devs; i++) {
1079                 device_t f0_dev;
1080                 f0_dev = __f0_dev[i];
1081                 if (f0_dev && f0_dev->enabled) {
1082                         u32 httc;
1083                         httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
1084                         httc &= ~HTTC_RSP_PASS_PW;
1085                         if (!dev->link_list->disable_relaxed_ordering) {
1086                                 httc |= HTTC_RSP_PASS_PW;
1087                         }
1088                         printk(BIOS_SPEW, "%s passpw: %s\n",
1089                                 dev_path(dev),
1090                                 (!dev->link_list->disable_relaxed_ordering)?
1091                                 "enabled":"disabled");
1092                         pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
1093                 }
1094         }
1095         return max;
1096 }
1097
1098 static struct device_operations pci_domain_ops = {
1099         .read_resources   = amdk8_domain_read_resources,
1100         .set_resources    = amdk8_domain_set_resources,
1101         .enable_resources = NULL,
1102         .init             = NULL,
1103         .scan_bus         = amdk8_domain_scan_bus,
1104         .ops_pci_bus      = &pci_cf8_conf1,
1105 };
1106
1107 static void add_more_links(device_t dev, unsigned total_links)
1108 {
1109         struct bus *link, *last = NULL;
1110         int link_num;
1111
1112         for (link = dev->link_list; link; link = link->next)
1113                 last = link;
1114
1115         if (last) {
1116                 int links = total_links - last->link_num;
1117                 link_num = last->link_num;
1118                 if (links > 0) {
1119                         link = malloc(links*sizeof(*link));
1120                         if (!link)
1121                                 die("Couldn't allocate more links!\n");
1122                         memset(link, 0, links*sizeof(*link));
1123                         last->next = link;
1124                 }
1125         }
1126         else {
1127                 link_num = -1;
1128                 link = malloc(total_links*sizeof(*link));
1129                 memset(link, 0, total_links*sizeof(*link));
1130                 dev->link_list = link;
1131         }
1132
1133         for (link_num = link_num + 1; link_num < total_links; link_num++) {
1134                 link->link_num = link_num;
1135                 link->dev = dev;
1136                 link->next = link + 1;
1137                 last = link;
1138                 link = link->next;
1139         }
1140         last->next = NULL;
1141 }
1142
1143 static u32 cpu_bus_scan(device_t dev, u32 max)
1144 {
1145         struct bus *cpu_bus;
1146         device_t dev_mc;
1147         int bsp_apicid;
1148         int i,j;
1149         unsigned nb_cfg_54;
1150         unsigned siblings;
1151         int e0_later_single_core;
1152         int disable_siblings;
1153
1154         nb_cfg_54 = 0;
1155         sysconf.enabled_apic_ext_id = 0;
1156         sysconf.lift_bsp_apicid = 0;
1157         siblings = 0;
1158
1159         /* Find the bootstrap processors apicid */
1160         bsp_apicid = lapicid();
1161         sysconf.apicid_offset = bsp_apicid;
1162
1163         disable_siblings = !CONFIG_LOGICAL_CPUS;
1164 #if CONFIG_LOGICAL_CPUS == 1
1165         get_option(&disable_siblings, "multi_core");
1166 #endif
1167
1168         // for pre_e0, nb_cfg_54 can not be set, (when you read it still is 0)
1169         // How can I get the nb_cfg_54 of every node's nb_cfg_54 in bsp???
1170         // and differ d0 and e0 single core
1171         nb_cfg_54 = read_nb_cfg_54();
1172
1173         dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
1174         if (!dev_mc) {
1175                 die("0:18.0 not found?");
1176         }
1177
1178         sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
1179
1180
1181         if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
1182         {
1183                 sysconf.enabled_apic_ext_id = 1;
1184                 if(bsp_apicid == 0) {
1185                         /* bsp apic id is not changed */
1186                         sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET;
1187                 } else
1188                 {
1189                         sysconf.lift_bsp_apicid = 1;
1190                 }
1191
1192         }
1193
1194         /* Find which cpus are present */
1195         cpu_bus = dev->link_list;
1196         for(i = 0; i < sysconf.nodes; i++) {
1197                 device_t cpu_dev, cpu;
1198                 struct device_path cpu_path;
1199
1200                 /* Find the cpu's pci device */
1201                 cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
1202                 if (!cpu_dev) {
1203                         /* If I am probing things in a weird order
1204                          * ensure all of the cpu's pci devices are found.
1205                          */
1206                         int local_j;
1207                         device_t dev_f0;
1208                         for(local_j = 0; local_j <= 3; local_j++) {
1209                                 cpu_dev = pci_probe_dev(NULL, dev_mc->bus,
1210                                         PCI_DEVFN(0x18 + i, local_j));
1211                         }
1212                         /* Ok, We need to set the links for that device.
1213                          * otherwise the device under it will not be scanned
1214                          */
1215                         dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0));
1216                         if(dev_f0) {
1217                                 add_more_links(dev_f0, 3);
1218                         }
1219                 }
1220
1221                 e0_later_single_core = 0;
1222                 if (cpu_dev && cpu_dev->enabled) {
1223                         j = pci_read_config32(cpu_dev, 0xe8);
1224                         j = (j >> 12) & 3; // dev is func 3
1225                         printk(BIOS_DEBUG, "  %s siblings=%d\n", dev_path(cpu_dev), j);
1226
1227                         if(nb_cfg_54) {
1228                                 // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
1229                                 //  ----> you can mixed single core e0 and dual core e0 at any sequence
1230                                 // That is the typical case
1231
1232                                 if(j == 0 ){
1233                                        #if CONFIG_K8_REV_F_SUPPORT == 0
1234                                         e0_later_single_core = is_e0_later_in_bsp(i);  // single core
1235                                        #else
1236                                         e0_later_single_core = is_cpu_f0_in_bsp(i);  // We can read cpuid(1) from Func3
1237                                        #endif
1238                                 } else {
1239                                        e0_later_single_core = 0;
1240                                 }
1241                                 if(e0_later_single_core) {
1242                                         printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");
1243
1244                                         j=1;
1245                                 }
1246
1247                                 if(siblings > j ) {
1248                                 }
1249                                 else {
1250                                         siblings = j;
1251                                 }
1252                         } else {
1253                                 siblings = j;
1254                         }
1255                 }
1256
1257                 u32 jj;
1258                 if(e0_later_single_core || disable_siblings) {
1259                         jj = 0;
1260                 } else
1261                 {
1262                         jj = siblings;
1263                 }
1264 #if 0
1265                 jj = 0; // if create cpu core1 path in amd_siblings by core0
1266 #endif
1267
1268                 for (j = 0; j <=jj; j++ ) {
1269
1270                         /* Build the cpu device path */
1271                         cpu_path.type = DEVICE_PATH_APIC;
1272                         cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
1273
1274                         /* See if I can find the cpu */
1275                         cpu = find_dev_path(cpu_bus, &cpu_path);
1276
1277                         /* Enable the cpu if I have the processor */
1278                         if (cpu_dev && cpu_dev->enabled) {
1279                                 if (!cpu) {
1280                                         cpu = alloc_dev(cpu_bus, &cpu_path);
1281                                 }
1282                                 if (cpu) {
1283                                         cpu->enabled = 1;
1284                                 }
1285                         }
1286
1287                         /* Disable the cpu if I don't have the processor */
1288                         if (cpu && (!cpu_dev || !cpu_dev->enabled)) {
1289                                 cpu->enabled = 0;
1290                         }
1291
1292                         /* Report what I have done */
1293                         if (cpu) {
1294                                 cpu->path.apic.node_id = i;
1295                                 cpu->path.apic.core_id = j;
1296                                 if(sysconf.enabled_apic_ext_id) {
1297                                         if(sysconf.lift_bsp_apicid) {
1298                                                 cpu->path.apic.apic_id += sysconf.apicid_offset;
1299                                         } else
1300                                         {
1301                                                 if (cpu->path.apic.apic_id != 0)
1302                                                         cpu->path.apic.apic_id += sysconf.apicid_offset;
1303                                         }
1304                                 }
1305                                 printk(BIOS_DEBUG, "CPU: %s %s\n",
1306                                         dev_path(cpu), cpu->enabled?"enabled":"disabled");
1307                         }
1308
1309                 } //j
1310         }
1311         return max;
1312 }
1313
1314 static void cpu_bus_init(device_t dev)
1315 {
1316         initialize_cpus(dev->link_list);
1317 }
1318
1319 static void cpu_bus_noop(device_t dev)
1320 {
1321 }
1322
1323 static struct device_operations cpu_bus_ops = {
1324         .read_resources   = cpu_bus_noop,
1325         .set_resources    = cpu_bus_noop,
1326         .enable_resources = cpu_bus_noop,
1327         .init             = cpu_bus_init,
1328         .scan_bus         = cpu_bus_scan,
1329 };
1330
1331 static void root_complex_enable_dev(struct device *dev)
1332 {
1333         /* Set the operations if it is a special bus type */
1334         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
1335                 dev->ops = &pci_domain_ops;
1336         }
1337         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
1338                 dev->ops = &cpu_bus_ops;
1339         }
1340 }
1341
1342 struct chip_operations northbridge_amd_amdk8_root_complex_ops = {
1343         CHIP_NAME("AMD K8 Root Complex")
1344         .enable_dev = root_complex_enable_dev,
1345 };