1 /* This should be done by Eric
2 2004.12 yhlu add dual core support
3 2005.01 yhlu add support move apic before pci_domain in MB Config.lb
4 2005.02 yhlu add e0 memory hole support
5 2005.11 yhlu add put sb ht chain on bus 0
8 #include <console/console.h>
11 #include <device/device.h>
12 #include <device/pci.h>
13 #include <device/pci_ids.h>
14 #include <device/hypertransport.h>
20 #include <cpu/x86/lapic.h>
22 #include <cpu/amd/dualcore.h>
23 #if CONFIG_LOGICAL_CPUS==1
24 #include <pc80/mc146818rtc.h>
28 #include "root_complex/chip.h"
29 #include "northbridge.h"
33 #include <cpu/amd/model_fxx_rev.h>
35 #include <cpu/amd/amdk8_sysconf.h>
37 struct amdk8_sysconf_t sysconf;
40 static device_t __f0_dev[MAX_FX_DEVS];
41 static device_t __f1_dev[MAX_FX_DEVS];
42 static unsigned fx_devs=0;
44 static void get_fx_devs(void)
47 for(i = 0; i < MAX_FX_DEVS; i++) {
48 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
49 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
50 if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
53 if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
54 die("Cannot find 0:0x18.[0|1]\n");
58 static uint32_t f1_read_config32(unsigned reg)
62 return pci_read_config32(__f1_dev[0], reg);
65 static void f1_write_config32(unsigned reg, uint32_t value)
70 for(i = 0; i < fx_devs; i++) {
73 if (dev && dev->enabled) {
74 pci_write_config32(dev, reg, value);
79 static unsigned int amdk8_nodeid(device_t dev)
81 return (dev->path.pci.devfn >> 3) - 0x18;
84 static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
89 uint32_t busses, config_busses;
90 unsigned free_reg, config_reg;
91 unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
96 dev->link[link].cap = 0x80 + (link *0x20);
98 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
99 } while(link_type & ConnectionPending);
100 if (!(link_type & LinkConnected)) {
104 link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
105 } while(!(link_type & InitComplete));
106 if (!(link_type & NonCoherent)) {
109 /* See if there is an available configuration space mapping
110 * register in function 1.
113 for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
115 config = f1_read_config32(config_reg);
116 if (!free_reg && ((config & 3) == 0)) {
117 free_reg = config_reg;
120 if (((config & 3) == 3) &&
121 (((config >> 4) & 7) == nodeid) &&
122 (((config >> 8) & 3) == link)) {
126 if (free_reg && (config_reg > 0xec)) {
127 config_reg = free_reg;
129 /* If we can't find an available configuration space mapping
130 * register skip this bus
132 if (config_reg > 0xec) {
136 /* Set up the primary, secondary and subordinate bus numbers.
137 * We have no idea how many busses are behind this bridge yet,
138 * so we set the subordinate bus number to 0xff for the moment.
140 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
141 // first chain will on bus 0
142 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
145 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
146 // second chain will be on 0x40, third 0x80, forth 0xc0
148 min_bus = ((max>>6) + 1) * 0x40;
162 dev->link[link].secondary = min_bus;
163 dev->link[link].subordinate = max_bus;
165 /* Read the existing primary/secondary/subordinate bus
166 * number configuration.
168 busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
169 config_busses = f1_read_config32(config_reg);
171 /* Configure the bus numbers for this bridge: the configuration
172 * transactions will not be propagates by the bridge if it is
173 * not correctly configured
175 busses &= 0xff000000;
176 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
177 ((unsigned int)(dev->link[link].secondary) << 8) |
178 ((unsigned int)(dev->link[link].subordinate) << 16));
179 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
181 config_busses &= 0x000fc88;
183 (3 << 0) | /* rw enable, no device compare */
184 (( nodeid & 7) << 4) |
185 (( link & 3 ) << 8) |
186 ((dev->link[link].secondary) << 16) |
187 ((dev->link[link].subordinate) << 24);
188 f1_write_config32(config_reg, config_busses);
190 /* Now we can scan all of the subordinate busses i.e. the
191 * chain on the hypertranport link
194 ht_unitid_base[i] = 0x20;
198 max_devfn = (0x17<<3) | 7;
200 max_devfn = (0x1f<<3) | 7;
202 max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid);
204 /* We know the number of busses behind this bridge. Set the
205 * subordinate bus number to it's real value
207 dev->link[link].subordinate = max;
208 busses = (busses & 0xff00ffff) |
209 ((unsigned int) (dev->link[link].subordinate) << 16);
210 pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
212 config_busses = (config_busses & 0x00ffffff) |
213 (dev->link[link].subordinate << 24);
214 f1_write_config32(config_reg, config_busses);
217 // config config_reg, and ht_unitid_base to update hcdn_reg;
220 index = (config_reg-0xe0) >> 2;
222 temp |= (ht_unitid_base[i] & 0xff) << (i*8);
225 sysconf.hcdn_reg[index] = temp;
232 static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
237 unsigned offset_unitid = 0;
238 nodeid = amdk8_nodeid(dev);
241 sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
242 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
243 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
246 max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
250 for(link = 0; link < dev->links; link++) {
251 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
252 if( (nodeid == 0) && (sblink == link) ) continue; //already done
255 #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
256 #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
257 if((nodeid == 0) && (sblink == link))
262 max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
269 static int reg_useable(unsigned reg,
270 device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
272 struct resource *res;
273 unsigned nodeid, link=0;
276 for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
278 dev = __f0_dev[nodeid];
281 for(link = 0; !res && (link < 3); link++) {
282 res = probe_resource(dev, IOINDEX(0x100 + reg, link));
288 if ( (goal_link == (link - 1)) &&
289 (goal_nodeid == (nodeid - 1)) &&
298 static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link,
299 unsigned min, unsigned max)
302 unsigned free_reg, reg;
305 for(reg = min; reg <= max; reg += 0x8) {
307 result = reg_useable(reg, dev, nodeid, link);
309 /* I have been allocated this one */
312 else if (result > 1) {
313 /* I have a free register pair */
321 resource = IOINDEX(0x100 + reg, link);
326 static unsigned amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
328 return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8);
331 static unsigned amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
333 return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8);
336 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
338 struct resource *resource;
340 /* Initialize the io space constraints on the current bus */
341 resource = new_resource(dev, IOINDEX(0, link));
345 resource->align = log2(HT_IO_HOST_ALIGN);
346 resource->gran = log2(HT_IO_HOST_ALIGN);
347 resource->limit = 0xffffUL;
348 resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
351 /* Initialize the prefetchable memory constraints on the current bus */
352 resource = new_resource(dev, IOINDEX(2, link));
356 resource->align = log2(HT_MEM_HOST_ALIGN);
357 resource->gran = log2(HT_MEM_HOST_ALIGN);
358 resource->limit = 0xffffffffffULL;
359 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
360 resource->flags |= IORESOURCE_BRIDGE;
363 /* Initialize the memory constraints on the current bus */
364 resource = new_resource(dev, IOINDEX(1, link));
368 resource->align = log2(HT_MEM_HOST_ALIGN);
369 resource->gran = log2(HT_MEM_HOST_ALIGN);
370 resource->limit = 0xffffffffULL;
371 resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
375 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid);
377 static void amdk8_read_resources(device_t dev)
379 unsigned nodeid, link;
380 nodeid = amdk8_nodeid(dev);
381 for(link = 0; link < dev->links; link++) {
382 if (dev->link[link].children) {
383 amdk8_link_read_bases(dev, nodeid, link);
387 amdk8_create_vga_resource(dev, nodeid);
390 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
392 resource_t rbase, rend;
396 /* Make certain the resource has actually been set */
397 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
398 printk_err("%s: can't set unassigned resource @%lx %lx\n",
399 __func__, resource->index, resource->flags);
403 /* If I have already stored this resource don't worry about it */
404 if (resource->flags & IORESOURCE_STORED) {
405 printk_err("%s: can't set stored resource @%lx %lx\n", __func__,
406 resource->index, resource->flags);
410 /* Only handle PCI memory and IO resources */
411 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
414 /* Ensure I am actually looking at a resource of function 1 */
415 if (resource->index < 0x100) {
419 if (resource->size == 0)
422 /* Get the base address */
423 rbase = resource->base;
425 /* Get the limit (rounded up) */
426 rend = resource_end(resource);
428 /* Get the register and link */
429 reg = resource->index & 0xfc;
430 link = IOINDEX_LINK(resource->index);
432 if (resource->flags & IORESOURCE_IO) {
433 uint32_t base, limit;
434 base = f1_read_config32(reg);
435 limit = f1_read_config32(reg + 0x4);
437 base |= rbase & 0x01fff000;
440 limit |= rend & 0x01fff000;
441 limit |= (link & 3) << 4;
442 limit |= (nodeid & 7);
444 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
445 printk_spew("%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
446 __func__, dev_path(dev), link);
447 base |= PCI_IO_BASE_VGA_EN;
449 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
450 base |= PCI_IO_BASE_NO_ISA;
453 f1_write_config32(reg + 0x4, limit);
454 f1_write_config32(reg, base);
456 else if (resource->flags & IORESOURCE_MEM) {
457 uint32_t base, limit;
458 base = f1_read_config32(reg);
459 limit = f1_read_config32(reg + 0x4);
461 base |= (rbase >> 8) & 0xffffff00;
464 limit |= (rend >> 8) & 0xffffff00;
465 limit |= (link & 3) << 4;
466 limit |= (nodeid & 7);
467 f1_write_config32(reg + 0x4, limit);
468 f1_write_config32(reg, base);
470 resource->flags |= IORESOURCE_STORED;
471 sprintf(buf, " <node %d link %d>",
473 report_resource_stored(dev, resource, buf);
476 #if CONFIG_CONSOLE_VGA_MULTI == 1
477 extern device_t vga_pri; // the primary vga device, defined in device.c
480 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
482 struct resource *resource;
485 /* find out which link the VGA card is connected,
486 * we only deal with the 'first' vga card */
487 for (link = 0; link < dev->links; link++) {
488 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
489 #if CONFIG_CONSOLE_VGA_MULTI == 1
490 printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
491 dev->link[link].secondary,dev->link[link].subordinate);
492 /* We need to make sure the vga_pri is under the link */
493 if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
494 (vga_pri->bus->secondary <= dev->link[link].subordinate )
501 /* no VGA card installed */
502 if (link == dev->links)
505 printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
507 /* allocate a temp resource for the legacy VGA buffer */
508 resource = new_resource(dev, IOINDEX(4, link));
510 printk_debug("VGA: %s out of resources.\n", dev_path(dev));
513 resource->base = 0xa0000;
514 resource->size = 0x20000;
515 resource->limit = 0xffffffff;
516 resource->flags = IORESOURCE_FIXED | IORESOURCE_MEM |
520 static void amdk8_set_resources(device_t dev)
522 unsigned nodeid, link;
525 /* Find the nodeid */
526 nodeid = amdk8_nodeid(dev);
528 /* Set each resource we have found */
529 for(i = 0; i < dev->resources; i++) {
530 struct resource *res = &dev->resource[i];
531 struct resource *old = NULL;
534 if (res->size == 0) /* No need to allocate registers. */
537 if (res->flags & IORESOURCE_IO)
538 index = amdk8_find_iopair(dev, nodeid,
539 IOINDEX_LINK(res->index));
541 index = amdk8_find_mempair(dev, nodeid,
542 IOINDEX_LINK(res->index));
544 old = probe_resource(dev, index);
546 res->index = old->index;
553 amdk8_set_resource(dev, res, nodeid);
556 compact_resources(dev);
558 for(link = 0; link < dev->links; link++) {
560 bus = &dev->link[link];
562 assign_resources(bus);
567 static void amdk8_enable_resources(device_t dev)
569 pci_dev_enable_resources(dev);
570 enable_childrens_resources(dev);
573 static void mcf0_control_init(struct device *dev)
576 printk_debug("NB: Function 0 Misc Control.. ");
579 printk_debug("done.\n");
583 static struct device_operations northbridge_operations = {
584 .read_resources = amdk8_read_resources,
585 .set_resources = amdk8_set_resources,
586 .enable_resources = amdk8_enable_resources,
587 .init = mcf0_control_init,
588 .scan_bus = amdk8_scan_chains,
594 static const struct pci_driver mcf0_driver __pci_driver = {
595 .ops = &northbridge_operations,
596 .vendor = PCI_VENDOR_ID_AMD,
600 struct chip_operations northbridge_amd_amdk8_ops = {
601 CHIP_NAME("AMD K8 Northbridge")
605 static void amdk8_domain_read_resources(device_t dev)
609 /* Find the already assigned resource pairs */
611 for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
612 uint32_t base, limit;
613 base = f1_read_config32(reg);
614 limit = f1_read_config32(reg + 0x04);
615 /* Is this register allocated? */
616 if ((base & 3) != 0) {
617 unsigned nodeid, link;
620 link = (limit >> 4) & 3;
621 reg_dev = __f0_dev[nodeid];
623 /* Reserve the resource */
624 struct resource *res;
625 res = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
635 pci_domain_read_resources(dev);
637 #if CONFIG_PCI_64BIT_PREF_MEM == 1
638 /* Initialize the system wide prefetchable memory resources constraints */
639 resource = new_resource(dev, 2);
640 resource->limit = 0xfcffffffffULL;
641 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
645 static void ram_resource(device_t dev, unsigned long index,
646 unsigned long basek, unsigned long sizek)
648 struct resource *resource;
653 resource = new_resource(dev, index);
654 resource->base = ((resource_t)basek) << 10;
655 resource->size = ((resource_t)sizek) << 10;
656 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
657 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
660 static void tolm_test(void *gp, struct device *dev, struct resource *new)
662 struct resource **best_p = gp;
663 struct resource *best;
666 if (!best || (best->base > new->base && new->base > 0xa0000)) {
672 static uint32_t find_pci_tolm(struct bus *bus)
674 struct resource *min;
677 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
679 if (min && tolm > min->base) {
685 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
687 struct hw_mem_hole_info {
688 unsigned hole_startk;
692 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
694 struct hw_mem_hole_info mem_hole;
697 mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
698 mem_hole.node_id = -1;
700 for (i = 0; i < fx_devs; i++) {
703 base = f1_read_config32(0x40 + (i << 3));
704 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
708 hole = pci_read_config32(__f1_dev[i], 0xf0);
709 if(hole & 1) { // we find the hole
710 mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
711 mem_hole.node_id = i; // record the node No with hole
712 break; // only one hole
716 //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
717 if(mem_hole.node_id==-1) {
718 uint32_t limitk_pri = 0;
720 uint32_t base, limit;
721 unsigned base_k, limit_k;
722 base = f1_read_config32(0x40 + (i << 3));
723 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
727 base_k = (base & 0xffff0000) >> 2;
728 if(limitk_pri != base_k) { // we find the hole
729 mem_hole.hole_startk = limitk_pri;
730 mem_hole.node_id = i;
731 break; //only one hole
734 limit = f1_read_config32(0x44 + (i << 3));
735 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
736 limitk_pri = limit_k;
744 static void disable_hoist_memory(unsigned long hole_startk, int node_id)
748 uint32_t base, limit;
753 //1. find which node has hole
754 //2. change limit in that node.
755 //3. change base and limit in later node
756 //4. clear that node f0
758 //if there is not mem hole enabled, we need to change it's base instead
760 hole_sizek = (4*1024*1024) - hole_startk;
762 for(i=7;i>node_id;i--) {
764 base = f1_read_config32(0x40 + (i << 3));
765 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
768 limit = f1_read_config32(0x44 + (i << 3));
769 f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
770 f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
772 limit = f1_read_config32(0x44 + (node_id << 3));
773 f1_write_config32(0x44 + (node_id << 3),limit - (hole_sizek << 2));
774 dev = __f1_dev[node_id];
776 printk_err("%s: node %x is NULL!\n", __func__, node_id);
779 hoist = pci_read_config32(dev, 0xf0);
781 pci_write_config32(dev, 0xf0, 0);
783 base = pci_read_config32(dev, 0x40 + (node_id << 3));
784 f1_write_config32(0x40 + (node_id << 3),base - (hole_sizek << 2));
788 static uint32_t hoist_memory(unsigned long hole_startk, int node_id)
793 uint32_t base, limit;
797 carry_over = (4*1024*1024) - hole_startk;
799 for(i=7;i>node_id;i--) {
801 base = f1_read_config32(0x40 + (i << 3));
802 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
805 limit = f1_read_config32(0x44 + (i << 3));
806 f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
807 f1_write_config32(0x40 + (i << 3),base + (carry_over << 2));
809 limit = f1_read_config32(0x44 + (node_id << 3));
810 f1_write_config32(0x44 + (node_id << 3),limit + (carry_over << 2));
811 dev = __f1_dev[node_id];
812 base = pci_read_config32(dev, 0x40 + (node_id << 3));
813 basek = (base & 0xffff0000) >> 2;
814 if(basek == hole_startk) {
815 //don't need set memhole here, because hole off set will be 0, overflow
816 //so need to change base reg instead, new basek will be 4*1024*1024
818 base |= (4*1024*1024)<<2;
819 f1_write_config32(0x40 + (node_id<<3), base);
823 hoist = /* hole start address */
824 ((hole_startk << 10) & 0xff000000) +
825 /* hole address to memory controller address */
826 (((basek + carry_over) >> 6) & 0x0000ff00) +
830 pci_write_config32(dev, 0xf0, hoist);
837 #if CONFIG_WRITE_HIGH_TABLES==1
838 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
839 extern uint64_t high_tables_base, high_tables_size;
840 #if CONFIG_GFXUMA == 1
841 extern uint64_t uma_memory_base, uma_memory_size;
845 static void amdk8_domain_set_resources(device_t dev)
847 #if CONFIG_PCI_64BIT_PREF_MEM == 1
848 struct resource *io, *mem1, *mem2;
849 struct resource *resource, *last;
851 unsigned long mmio_basek;
854 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
855 struct hw_mem_hole_info mem_hole;
856 unsigned reset_memhole = 1;
860 /* Place the IO devices somewhere safe */
861 io = find_resource(dev, 0);
862 io->base = DEVICE_IO_START;
864 #if CONFIG_PCI_64BIT_PREF_MEM == 1
865 /* Now reallocate the pci resources memory with the
866 * highest addresses I can manage.
868 mem1 = find_resource(dev, 1);
869 mem2 = find_resource(dev, 2);
872 printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
873 mem1->base, mem1->limit, mem1->size, mem1->align);
874 printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
875 mem2->base, mem2->limit, mem2->size, mem2->align);
878 /* See if both resources have roughly the same limits */
879 if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
880 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
882 /* If so place the one with the most stringent alignment first
884 if (mem2->align > mem1->align) {
885 struct resource *tmp;
890 /* Now place the memory as high up as it will go */
891 mem2->base = resource_max(mem2);
892 mem1->limit = mem2->base - 1;
893 mem1->base = resource_max(mem1);
896 /* Place the resources as high up as they will go */
897 mem2->base = resource_max(mem2);
898 mem1->base = resource_max(mem1);
902 printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
903 mem1->base, mem1->limit, mem1->size, mem1->align);
904 printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
905 mem2->base, mem2->limit, mem2->size, mem2->align);
908 last = &dev->resource[dev->resources];
909 for(resource = &dev->resource[0]; resource < last; resource++)
911 resource->flags |= IORESOURCE_ASSIGNED;
912 resource->flags |= IORESOURCE_STORED;
913 report_resource_stored(dev, resource, "");
919 pci_tolm = find_pci_tolm(&dev->link[0]);
921 #warning "FIXME handle interleaved nodes"
922 mmio_basek = pci_tolm >> 10;
923 /* Round mmio_basek to something the processor can support */
924 mmio_basek &= ~((1 << 6) -1);
927 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
928 /* Round the mmio hold to 64M */
929 mmio_basek &= ~((64*1024) - 1);
932 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
933 /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
934 * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
935 * otherwise We reset the hole to the mmio_basek
937 #if CONFIG_K8_REV_F_SUPPORT == 0
938 if (!is_cpu_pre_e0()) {
941 mem_hole = get_hw_mem_hole_info();
943 if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
944 mmio_basek = mem_hole.hole_startk;
948 //mmio_basek = 3*1024*1024; // for debug to meet boundary
951 if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
952 // We need to reset our Mem Hole, because We want more big HOLE than we already set
953 //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
954 disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
957 #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
958 //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
960 for (i = 0; i < fx_devs; i++) {
963 base = f1_read_config32(0x40 + (i << 3));
964 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
968 basek = (base & 0xffff0000) >> 2;
969 if(mmio_basek == basek) {
970 mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node
978 #if CONFIG_K8_REV_F_SUPPORT == 0
985 for(i = 0; i < fx_devs; i++) {
986 uint32_t base, limit;
987 unsigned basek, limitk, sizek;
988 base = f1_read_config32(0x40 + (i << 3));
989 limit = f1_read_config32(0x44 + (i << 3));
990 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
993 basek = (base & 0xffff0000) >> 2;
994 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
995 sizek = limitk - basek;
997 /* see if we need a hole from 0xa0000 to 0xbffff */
998 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
999 ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
1001 basek = (8*64)+(16*16);
1002 sizek = limitk - ((8*64)+(16*16));
1007 #if CONFIG_GFXUMA == 1
1008 printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
1009 if ((uma_memory_base >> 10) < mmio_basek)
1010 printk_alert("node %d: UMA memory starts below mmio_basek\n", i);
1012 // printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
1015 /* See if I need to split the region to accomodate pci memory space */
1016 if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
1017 if (basek <= mmio_basek) {
1019 pre_sizek = mmio_basek - basek;
1021 ram_resource(dev, (idx | i), basek, pre_sizek);
1024 #if CONFIG_WRITE_HIGH_TABLES==1
1025 if (i==0 && high_tables_base==0) {
1026 /* Leave some space for ACPI, PIRQ and MP tables */
1027 #if CONFIG_GFXUMA == 1
1028 high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
1030 high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
1032 high_tables_size = HIGH_TABLES_SIZE * 1024;
1033 printk_debug(" split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
1038 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
1040 #if CONFIG_K8_REV_F_SUPPORT == 0
1041 if(!is_cpu_pre_e0() )
1043 sizek += hoist_memory(mmio_basek,i);
1048 if ((basek + sizek) <= 4*1024*1024) {
1052 basek = 4*1024*1024;
1053 sizek -= (4*1024*1024 - mmio_basek);
1056 /* If sizek == 0, it was split at mmio_basek without a hole.
1057 * Don't create an empty ram_resource.
1060 ram_resource(dev, (idx | i), basek, sizek);
1062 #if CONFIG_WRITE_HIGH_TABLES==1
1063 printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
1064 i, mmio_basek, basek, limitk);
1065 if (i==0 && high_tables_base==0) {
1066 /* Leave some space for ACPI, PIRQ and MP tables */
1067 #if CONFIG_GFXUMA == 1
1068 high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
1070 high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
1072 high_tables_size = HIGH_TABLES_SIZE * 1024;
1076 assign_resources(&dev->link[0]);
1080 static unsigned int amdk8_domain_scan_bus(device_t dev, unsigned int max)
1084 /* Unmap all of the HT chains */
1085 for(reg = 0xe0; reg <= 0xec; reg += 4) {
1086 f1_write_config32(reg, 0);
1088 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
1090 /* Tune the hypertransport transaction for best performance.
1091 * Including enabling relaxed ordering if it is safe.
1094 for(i = 0; i < fx_devs; i++) {
1096 f0_dev = __f0_dev[i];
1097 if (f0_dev && f0_dev->enabled) {
1099 httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
1100 httc &= ~HTTC_RSP_PASS_PW;
1101 if (!dev->link[0].disable_relaxed_ordering) {
1102 httc |= HTTC_RSP_PASS_PW;
1104 printk_spew("%s passpw: %s\n",
1106 (!dev->link[0].disable_relaxed_ordering)?
1107 "enabled":"disabled");
1108 pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
1114 static struct device_operations pci_domain_ops = {
1115 .read_resources = amdk8_domain_read_resources,
1116 .set_resources = amdk8_domain_set_resources,
1117 .enable_resources = enable_childrens_resources,
1119 .scan_bus = amdk8_domain_scan_bus,
1120 .ops_pci_bus = &pci_cf8_conf1,
1123 static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
1125 struct bus *cpu_bus;
1131 int e0_later_single_core;
1132 int disable_siblings;
1135 sysconf.enabled_apic_ext_id = 0;
1136 sysconf.lift_bsp_apicid = 0;
1139 /* Find the bootstrap processors apicid */
1140 bsp_apicid = lapicid();
1141 sysconf.apicid_offset = bsp_apicid;
1143 disable_siblings = !CONFIG_LOGICAL_CPUS;
1144 #if CONFIG_LOGICAL_CPUS == 1
1145 get_option(&disable_siblings, "dual_core");
1148 // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)
1149 // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core
1151 nb_cfg_54 = read_nb_cfg_54();
1153 dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
1155 die("0:18.0 not found?");
1158 sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
1161 if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
1163 sysconf.enabled_apic_ext_id = 1;
1164 if(bsp_apicid == 0) {
1165 /* bsp apic id is not changed */
1166 sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET;
1169 sysconf.lift_bsp_apicid = 1;
1174 /* Find which cpus are present */
1175 cpu_bus = &dev->link[0];
1176 for(i = 0; i < sysconf.nodes; i++) {
1177 device_t cpu_dev, cpu;
1178 struct device_path cpu_path;
1180 /* Find the cpu's pci device */
1181 cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
1183 /* If I am probing things in a weird order
1184 * ensure all of the cpu's pci devices are found.
1188 for(local_j = 0; local_j <= 3; local_j++) {
1189 cpu_dev = pci_probe_dev(NULL, dev_mc->bus,
1190 PCI_DEVFN(0x18 + i, local_j));
1192 /* Ok, We need to set the links for that device.
1193 * otherwise the device under it will not be scanned
1195 dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0));
1198 for(local_j=0;local_j<3;local_j++) {
1199 dev_f0->link[local_j].link = local_j;
1200 dev_f0->link[local_j].dev = dev_f0;
1206 e0_later_single_core = 0;
1207 if (cpu_dev && cpu_dev->enabled) {
1208 j = pci_read_config32(cpu_dev, 0xe8);
1209 j = (j >> 12) & 3; // dev is func 3
1210 printk_debug(" %s siblings=%d\n", dev_path(cpu_dev), j);
1213 // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
1214 // ----> you can mixed single core e0 and dual core e0 at any sequence
1215 // That is the typical case
1218 #if CONFIG_K8_REV_F_SUPPORT == 0
1219 e0_later_single_core = is_e0_later_in_bsp(i); // single core
1221 e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
1224 e0_later_single_core = 0;
1226 if(e0_later_single_core) {
1227 printk_debug("\tFound Rev E or Rev F later single core\r\n");
1243 if(e0_later_single_core || disable_siblings) {
1250 jj = 0; // if create cpu core1 path in amd_siblings by core0
1253 for (j = 0; j <=jj; j++ ) {
1255 /* Build the cpu device path */
1256 cpu_path.type = DEVICE_PATH_APIC;
1257 cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
1259 /* See if I can find the cpu */
1260 cpu = find_dev_path(cpu_bus, &cpu_path);
1262 /* Enable the cpu if I have the processor */
1263 if (cpu_dev && cpu_dev->enabled) {
1265 cpu = alloc_dev(cpu_bus, &cpu_path);
1272 /* Disable the cpu if I don't have the processor */
1273 if (cpu && (!cpu_dev || !cpu_dev->enabled)) {
1277 /* Report what I have done */
1279 cpu->path.apic.node_id = i;
1280 cpu->path.apic.core_id = j;
1281 if(sysconf.enabled_apic_ext_id) {
1282 if(sysconf.lift_bsp_apicid) {
1283 cpu->path.apic.apic_id += sysconf.apicid_offset;
1286 if (cpu->path.apic.apic_id != 0)
1287 cpu->path.apic.apic_id += sysconf.apicid_offset;
1290 printk_debug("CPU: %s %s\n",
1291 dev_path(cpu), cpu->enabled?"enabled":"disabled");
1299 static void cpu_bus_init(device_t dev)
1301 initialize_cpus(&dev->link[0]);
1304 static void cpu_bus_noop(device_t dev)
1308 static struct device_operations cpu_bus_ops = {
1309 .read_resources = cpu_bus_noop,
1310 .set_resources = cpu_bus_noop,
1311 .enable_resources = cpu_bus_noop,
1312 .init = cpu_bus_init,
1313 .scan_bus = cpu_bus_scan,
1316 static void root_complex_enable_dev(struct device *dev)
1318 /* Set the operations if it is a special bus type */
1319 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
1320 dev->ops = &pci_domain_ops;
1322 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
1323 dev->ops = &cpu_bus_ops;
1327 struct chip_operations northbridge_amd_amdk8_root_complex_ops = {
1328 CHIP_NAME("AMD K8 Root Complex")
1329 .enable_dev = root_complex_enable_dev,