1 /* Turn off machine check triggers when reading
2 * pci space where there are no devices.
3 * This is necessary when scaning the bus for
4 * devices which is done by the kernel */
6 #include <console/console.h>
7 #include <device/device.h>
8 #include <device/pci.h>
9 #include <device/pci_ids.h>
10 #include <device/pci_ops.h>
11 #include "./cpu_rev.c"
13 static void misc_control_init(struct device *dev)
17 printk_debug("NB: Function 3 Misc Control.. ");
19 /* disable error reporting */
20 cmd = pci_read_config32(dev, 0x44);
21 cmd |= (1<<6) | (1<<25);
22 pci_write_config32(dev, 0x44, cmd );
23 if (is_cpu_pre_c0()) {
25 cmd = pci_read_config32(dev, 0x80);
27 pci_write_config32(dev, 0x80, cmd );
28 cmd = pci_read_config32(dev, 0x84);
31 pci_write_config32(dev, 0x84, cmd );
33 cmd = pci_read_config32(dev, 0x70);
36 pci_write_config32(dev, 0x70, cmd );
37 cmd = pci_read_config32(dev, 0x7c);
39 pci_write_config32(dev, 0x7c, cmd );
44 cmd = pci_read_config32(dev, 0xd4);
45 if(cmd != 0x04e20707) {
47 pci_write_config32(dev, 0xd4, cmd );
53 pci_write_config32(dev, 0xd4, cmd );
57 * FIXME: This preprocessor check is a mere workaround.
58 * The right fix is to walk over all links on all nodes
59 * and set the FIFO read pointer optimization value to
60 * 0x25 for each link connected to an AMD HT device.
62 * The reason this is only enabled for machines with more
63 * than one CPU is that Athlon64 machines don't have the
64 * link at all that is optimized in the code.
67 #if CONFIG_MAX_CPUS > 1
68 cmd = pci_read_config32(dev, 0xdc);
69 if((cmd & 0x0000ff00) != 0x02500) {
72 pci_write_config32(dev, 0xdc, cmd );
73 printk_debug("resetting cpu\n");
77 printk_debug("done.\n");
80 static struct device_operations mcf3_ops = {
81 .read_resources = pci_dev_read_resources,
82 .set_resources = pci_dev_set_resources,
83 .enable_resources = pci_dev_enable_resources,
84 .init = misc_control_init,
88 static struct pci_driver mcf3_driver __pci_driver = {
90 .vendor = PCI_VENDOR_ID_AMD,