src/northbridge/amd/amdk8/misc_control.c

   1 /* Turn off machine check triggers when reading
   2  * pci space where there are no devices.
   3  * This is necessary when scaning the bus for
   4  * devices which is done by the kernel
   5  *
   6  * written in 2003 by Eric Biederman
   7  *
   8  *  - Athlon64 workarounds by Stefan Reinauer
   9  *  - "reset once" logic by Yinghai Lu
  10  */
  11
  12 #include <console/console.h>
  13 #include <device/device.h>
  14 #include <device/pci.h>
  15 #include <device/pci_ids.h>
  16 #include <device/pci_ops.h>
  17 #include <part/hard_reset.h>
  18 #include <pc80/mc146818rtc.h>
  19 #include <bitops.h>
  20 #include "./cpu_rev.c"
  21 #include "amdk8.h"
  22
  23 /**
  24  * @brief Read resources for AGP aperture
  25  *
  26  * @param
  27  *
  28  * There is only one AGP aperture resource needed. The resoruce is added to
  29  * the northbridge of BSP.
  30  *
  31  * The same trick can be used to augment legacy VGA resources which can
  32  * be detect by generic pci reousrce allocator for VGA devices.
  33  * BAD: it is more tricky than I think, the resource allocation code is
  34  * implemented in a way to NOT DOING legacy VGA resource allcation on
  35  * purpose :-(.
  36  */
  37 static void mcf3_read_resources(device_t dev)
  38 {
  39         struct resource *resource;
  40         unsigned char iommu;
  41         /* Read the generic PCI resources */
  42         pci_dev_read_resources(dev);
  43
  44         /* If we are not the first processor don't allocate the gart apeture */
  45         if (dev->path.u.pci.devfn != PCI_DEVFN(0x18, 3)) {
  46                 return;
  47         }
  48
  49         iommu = 1;
  50         get_option(&iommu, "iommu");
  51
  52         if (iommu) {
  53                 /* Add a Gart apeture resource */
  54                 resource = new_resource(dev, 0x94);
  55                 resource->size = iommu?AGP_APERTURE_SIZE:1;
  56                 resource->align = log2(resource->size);
  57                 resource->gran  = log2(resource->size);
  58                 resource->limit = 0xffffffff; /* 4G */
  59                 resource->flags = IORESOURCE_MEM;
  60         }
  61 }
  62
  63 static void set_agp_aperture(device_t dev)
  64 {
  65         struct resource *resource;
  66
  67         resource = probe_resource(dev, 0x94);
  68         if (resource) {
  69                 device_t pdev;
  70                 uint32_t gart_base, gart_acr;
  71
  72                 /* Remember this resource has been stored */
  73                 resource->flags |= IORESOURCE_STORED;
  74
  75                 /* Find the size of the GART aperture */
  76                 gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
  77
  78                 /* Get the base address */
  79                 gart_base = ((resource->base) >> 25) & 0x00007fff;
  80
  81                 /* Update the other northbriges */
  82                 pdev = 0;
  83                 while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
  84                         /* Store the GART size but don't enable it */
  85                         pci_write_config32(pdev, 0x90, gart_acr);
  86
  87                         /* Store the GART base address */
  88                         pci_write_config32(pdev, 0x94, gart_base);
  89
  90                         /* Don't set the GART Table base address */
  91                         pci_write_config32(pdev, 0x98, 0);
  92
  93                         /* Report the resource has been stored... */
  94                         report_resource_stored(pdev, resource, " <gart>");
  95                 }
  96         }
  97 }
  98
  99 static void mcf3_set_resources(device_t dev)
 100 {
 101         /* Set the gart apeture */
 102         set_agp_aperture(dev);
 103
 104         /* Set the generic PCI resources */
 105         pci_dev_set_resources(dev);
 106 }
 107
 108 static void misc_control_init(struct device *dev)
 109 {
 110         uint32_t cmd, cmd_ref;
 111         int needs_reset;
 112         struct device *f0_dev, *f2_dev;
 113
 114         printk_debug("NB: Function 3 Misc Control.. ");
 115         needs_reset = 0;
 116
 117         /* Disable Machine checks from Invalid Locations.
 118          * This is needed for PC backwards compatibility.
 119          */
 120         cmd = pci_read_config32(dev, 0x44);
 121         cmd |= (1<<6) | (1<<25);
 122         pci_write_config32(dev, 0x44, cmd );
 123         if (is_cpu_pre_c0()) {
 124
 125                 /* Errata 58
 126                  * Disable CPU low power states C2, C1 and throttling
 127                  */
 128                 cmd = pci_read_config32(dev, 0x80);
 129                 cmd &= ~(1<<0);
 130                 pci_write_config32(dev, 0x80, cmd );
 131                 cmd = pci_read_config32(dev, 0x84);
 132                 cmd &= ~(1<<24);
 133                 cmd &= ~(1<<8);
 134                 pci_write_config32(dev, 0x84, cmd );
 135
 136                 /* Errata 66
 137                  * Limit the number of downstream posted requests to 1
 138                  */
 139                 cmd = pci_read_config32(dev, 0x70);
 140                 if ((cmd & (3 << 0)) != 2) {
 141                         cmd &= ~(3<<0);
 142                         cmd |= (2<<0);
 143                         pci_write_config32(dev, 0x70, cmd );
 144                         needs_reset = 1;
 145                 }
 146                 cmd = pci_read_config32(dev, 0x7c);
 147                 if ((cmd & (3 << 4)) != 0) {
 148                         cmd &= ~(3<<4);
 149                         cmd |= (0<<4);
 150                         pci_write_config32(dev, 0x7c, cmd );
 151                         needs_reset = 1;
 152                 }
 153                 /* Clock Power/Timing Low */
 154                 cmd = pci_read_config32(dev, 0xd4);
 155                 if (cmd != 0x000D0001) {
 156                         cmd = 0x000D0001;
 157                         pci_write_config32(dev, 0xd4, cmd);
 158                         needs_reset = 1; /* Needed? */
 159                 }
 160         }
 161         else if(is_cpu_pre_d0()) {
 162                 uint32_t dcl;
 163                 f2_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3 + 2);
 164                 /* Errata 98
 165                  * Set Clk Ramp Hystersis to 7
 166                  * Clock Power/Timing Low
 167                  */
 168                 cmd_ref = 0x04e20707; /* Registered */
 169                 dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
 170                 if (dcl & DCL_UnBufDimm) {
 171                         cmd_ref = 0x000D0701; /* Unbuffered */
 172                 }
 173                 cmd = pci_read_config32(dev, 0xd4);
 174                 if(cmd != cmd_ref) {
 175                         pci_write_config32(dev, 0xd4, cmd_ref );
 176                         needs_reset = 1; /* Needed? */
 177                 }
 178         }
 179         /* Optimize the Link read pointers */
 180         f0_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3);
 181         if (f0_dev) {
 182                 int link;
 183                 cmd_ref = cmd = pci_read_config32(dev, 0xdc);
 184                 for(link = 0; link < 3; link++) {
 185                         uint32_t link_type;
 186                         unsigned reg;
 187                         /* This works on an Athlon64 because unimplemented links return 0 */
 188                         reg = 0x98 + (link * 0x20);
 189                         link_type = pci_read_config32(f0_dev, reg);
 190                         if ((link_type & 7) == 3) { /* Only handle coherent link here */
 191                                 cmd &= ~(0xff << (link *8));
 192                                 /* FIXME this assumes the device on the other side is an AMD device */
 193                                 cmd |= 0x25 << (link *8);
 194                         }
 195                 }
 196                 if (cmd != cmd_ref) {
 197                         pci_write_config32(dev, 0xdc, cmd);
 198                         needs_reset = 1;
 199                 }
 200         }
 201         else {
 202                 printk_err("Missing f0 device!\n");
 203         }
 204         if (needs_reset) {
 205                 printk_debug("resetting cpu\n");
 206                 hard_reset();
 207         }
 208         printk_debug("done.\n");
 209 }
 210
 211
 212 static struct device_operations mcf3_ops  = {
 213         .read_resources   = mcf3_read_resources,
 214         .set_resources    = mcf3_set_resources,
 215         .enable_resources = pci_dev_enable_resources,
 216         .init             = misc_control_init,
 217         .scan_bus         = 0,
 218         .ops_pci          = 0,
 219 };
 220
 221 static struct pci_driver mcf3_driver __pci_driver = {
 222         .ops    = &mcf3_ops,
 223         .vendor = PCI_VENDOR_ID_AMD,
 224         .device = 0x1103,
 225 };