src/northbridge/amd/amdk8/misc_control.c

   1 /* Turn off machine check triggers when reading
   2  * pci space where there are no devices.
   3  * This is necessary when scaning the bus for
   4  * devices which is done by the kernel */
   5
   6 #include <console/console.h>
   7 #include <device/device.h>
   8 #include <device/pci.h>
   9 #include <device/pci_ids.h>
  10 #include <device/pci_ops.h>
  11 #include "./cpu_rev.c"
  12
  13 static cpu_reset_count = 0; //By LYH
  14 static void misc_control_init(struct device *dev)
  15 {
  16         uint32_t cmd;
  17
  18         printk_debug("NB: Function 3 Misc Control.. ");
  19
  20         /* disable error reporting */
  21         cmd = pci_read_config32(dev, 0x44);
  22         cmd |= (1<<6) | (1<<25);
  23         pci_write_config32(dev, 0x44, cmd );
  24         if (is_cpu_pre_c0()) {
  25                 /* errata 58 */
  26                 cmd = pci_read_config32(dev, 0x80);
  27                 cmd &= ~(1<<0);
  28                 pci_write_config32(dev, 0x80, cmd );
  29                 cmd = pci_read_config32(dev, 0x84);
  30                 cmd &= ~(1<<24);
  31                 cmd &= ~(1<<8);
  32                 pci_write_config32(dev, 0x84, cmd );
  33                 /* errata 66 */
  34                 cmd = pci_read_config32(dev, 0x70);
  35                 cmd &= ~(1<<0);
  36                 cmd |= (1<<1);
  37                 pci_write_config32(dev, 0x70, cmd );
  38                 cmd = pci_read_config32(dev, 0x7c);
  39                 cmd &= ~(3<<4);
  40                 pci_write_config32(dev, 0x7c, cmd );
  41         }
  42         else {
  43                 /* errata 98 */
  44 #if 0
  45                 cmd = pci_read_config32(dev, 0xd4);
  46                 if(cmd != 0x04e20707) {
  47                         cmd = 0x04e20707;
  48                         pci_write_config32(dev, 0xd4, cmd );
  49                         hard_reset();
  50                 }
  51 #endif
  52
  53                 cmd = 0x04e20707;
  54                 pci_write_config32(dev, 0xd4, cmd );
  55         }
  56 #if 1
  57 #if HAVE_HARD_RESET==1
  58         cpu_reset_count++;  //by LYH
  59         cmd = pci_read_config32(dev, 0xdc);
  60         if((cmd & 0x0000ff00) != 0x02500) {
  61                 cmd &= 0xffff00ff;
  62                 cmd |= 0x00002500;
  63                 pci_write_config32(dev, 0xdc, cmd );
  64                 if(cpu_reset_count==CONFIG_MAX_CPUS) { //By LYH
  65                         printk_debug("resetting cpu\n");
  66                         hard_reset();
  67                 } //By LYH
  68         }
  69 #endif
  70 #endif
  71         printk_debug("done.\n");
  72 }
  73
  74 static struct device_operations mcf3_ops  = {
  75         .read_resources   = pci_dev_read_resources,
  76         .set_resources    = pci_dev_set_resources,
  77         .enable_resources = pci_dev_enable_resources,
  78         .init             = misc_control_init,
  79         .scan_bus         = 0,
  80 };
  81
  82 static struct pci_driver mcf3_driver __pci_driver = {
  83         .ops    = &mcf3_ops,
  84         .vendor = PCI_VENDOR_ID_AMD,
  85         .device = 0x1103,
  86 };
  87