1 /* Turn off machine check triggers when reading
2 * pci space where there are no devices.
3 * This is necessary when scaning the bus for
4 * devices which is done by the kernel */
6 #include <console/console.h>
7 #include <device/device.h>
8 #include <device/pci.h>
9 #include <device/pci_ids.h>
10 #include <device/pci_ops.h>
11 #include "./cpu_rev.c"
13 static void misc_control_init(struct device *dev)
17 printk_debug("NB: Function 3 Misc Control.. ");
18 cmd = pci_read_config32(dev, 0x44);
19 cmd |= (1<<6) | (1<<25);
20 pci_write_config32(dev, 0x44, cmd );
21 if (is_cpu_pre_c0()) {
23 cmd = pci_read_config32(dev, 0x80);
25 pci_write_config32(dev, 0x80, cmd );
26 cmd = pci_read_config32(dev, 0x84);
29 pci_write_config32(dev, 0x84, cmd );
31 cmd = pci_read_config32(dev, 0x70);
34 pci_write_config32(dev, 0x70, cmd );
35 cmd = pci_read_config32(dev, 0x7c);
37 pci_write_config32(dev, 0x7c, cmd );
42 cmd = pci_read_config32(dev, 0xd4);
43 if(cmd != 0x04e20707) {
45 pci_write_config32(dev, 0xd4, cmd );
51 pci_write_config32(dev, 0xd4, cmd );
55 * FIXME: This preprocessor check is a mere workaround.
56 * The right fix is to walk over all links on all nodes
57 * and set the FIFO read pointer optimization value to
58 * 0x25 for each link connected to an AMD HT device.
60 * The reason this is only enabled for machines with more
61 * than one CPU is that Athlon64 machines don't have the
62 * link at all that is optimized in the code.
65 #if CONFIG_MAX_CPUS > 1
66 cmd = pci_read_config32(dev, 0xdc);
67 if((cmd & 0x0000ff00) != 0x02500) {
70 pci_write_config32(dev, 0xdc, cmd );
71 printk_debug("resetting cpu\n");
75 printk_debug("done.\n");
78 static struct device_operations mcf3_ops = {
79 .read_resources = pci_dev_read_resources,
80 .set_resources = pci_dev_set_resources,
81 .enable_resources = pci_dev_enable_resources,
82 .init = misc_control_init,
86 static struct pci_driver mcf3_driver __pci_driver = {
88 .vendor = PCI_VENDOR_ID_AMD,