src/northbridge/amd/amdk8/exit_from_self.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 void exit_from_self(int controllers, const struct mem_controller *ctrl,
  21                     struct sys_info *sysinfo)
  22 {
  23         int i;
  24         u32 dcl, dch;
  25         u32 pcidev;
  26         u8 bitmask;
  27         u8 is_post_rev_g;
  28         u32 local_cpuid;
  29
  30         for (i = 0; i < controllers; i++) {
  31                 if (!sysinfo->ctrl_present[i])
  32                         continue;
  33                 /* Skip everything if I don't have any memory on this controller */
  34                 dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
  35                 if (!(dch & DCH_MemClkFreqVal)) {
  36                         continue;
  37                 }
  38
  39                 local_cpuid = pci_read_config32(ctrl[i].f3, 0xfc);
  40                 is_post_rev_g = ((local_cpuid & 0xfff00) > 0x50f00);
  41
  42                 /* ChipKill */
  43                 dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
  44                 if (dcl & DCL_DimmEccEn) {
  45                         u32 mnc;
  46                         printk(BIOS_SPEW, "ECC enabled\n");
  47                         mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
  48                         mnc |= MNC_ECC_EN;
  49                         if (dcl & DCL_Width128) {
  50                                 mnc |= MNC_CHIPKILL_EN;
  51                         }
  52                         pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
  53                 }
  54
  55                 printk(BIOS_DEBUG, "before resume errata #%d\n",
  56                              (is_post_rev_g) ? 270 : 125);
  57                 /*
  58                    1. Restore memory controller registers as normal.
  59                    2. Set the DisAutoRefresh bit (Dev:2x8C[18]). (270 only)
  60                    3. Set the EnDramInit bit (Dev:2x7C[31]), clear all other bits in the same register).
  61                    4. Wait at least 750 us.
  62                    5. Clear the EnDramInit bit.
  63                    6. Clear the DisAutoRefresh bit. (270 only)
  64                    7. Read the value of Dev:2x80 and write that value back to Dev:2x80.
  65                    8. Set the exit from the self refresh bit (Dev:2x90[1]).
  66                    9. Clear the exit from self refresh bit immediately.
  67                    Note: Steps 8 and 9 must be executed in a single 64-byte aligned uninterrupted instruction stream.
  68                  */
  69
  70                 enable_lapic();
  71                 init_timer();
  72
  73                 printk(BIOS_DEBUG, "before exit errata - timer enabled\n");
  74
  75                 if (is_post_rev_g) {
  76                         dcl =
  77                             pci_read_config32(ctrl[i].f2,
  78                                               DRAM_TIMING_HIGH);
  79                         dcl |= (1 << 18);
  80                         pci_write_config32(ctrl[i].f2, DRAM_TIMING_HIGH,
  81                                            dcl);
  82                 }
  83
  84                 dcl = DI_EnDramInit;
  85                 pci_write_config32(ctrl[i].f2, DRAM_INIT, dcl);
  86
  87                 udelay(800);
  88
  89                 printk(BIOS_DEBUG, "before exit errata - after mdelay\n");
  90
  91                 dcl = pci_read_config32(ctrl[i].f2, DRAM_INIT);
  92                 dcl &= ~DI_EnDramInit;
  93                 pci_write_config32(ctrl[i].f2, DRAM_INIT, dcl);
  94
  95                 if (is_post_rev_g) {
  96                         dcl =
  97                             pci_read_config32(ctrl[i].f2,
  98                                               DRAM_TIMING_HIGH);
  99                         dcl &= ~(1 << 18);
 100                         pci_write_config32(ctrl[i].f2, DRAM_TIMING_HIGH,
 101                                            dcl);
 102                 }
 103
 104                 dcl = pci_read_config32(ctrl[i].f2, DRAM_BANK_ADDR_MAP);
 105                 pci_write_config32(ctrl[i].f2, DRAM_BANK_ADDR_MAP, dcl);
 106
 107                 /* I was unable to do that like: ctrl[i].f2->path.pci.devfn << 8 */
 108                 pcidev =
 109                     0x80000000 | ((((ctrl[i].node_id + 0x18) << 3) | 0x2)
 110                                   << 8) | 0x90;
 111                 printk(BIOS_DEBUG, "pcidev is %x\n", pcidev);
 112                 bitmask = 2;
 113                 __asm__ __volatile__("pushl %0\n\t"
 114                                      "movw $0xcf8, %%dx\n\t"
 115                                      "out %%eax, (%%dx)\n\t"
 116                                      "movw $0xcfc, %%dx\n\t"
 117                                      "inl %%dx, %%eax\n\t"
 118                                      "orb %1, %%al\n\t"
 119                                      "not %1\n\t"
 120                                      ".align 64\n\t"
 121                                      "outl  %%eax, (%%dx) \n\t"
 122                                      "andb %1, %%al\n\t"
 123                                      "outl %%eax, (%%dx)\n\t"
 124                                      "popl %0\n\t"::"a"(pcidev),
 125                                      "q"(bitmask):"edx");
 126         }
 127
 128         printk(BIOS_DEBUG, "after exit errata\n");
 129
 130
 131         for (i = 0; i < controllers; i++) {
 132                 u32 dcm;
 133                 if (!sysinfo->ctrl_present[i])
 134                         continue;
 135                 /* Skip everything if I don't have any memory on this controller */
 136                 if (sysinfo->meminfo[i].dimm_mask == 0x00)
 137                         continue;
 138
 139                 printk(BIOS_DEBUG, "Exiting memory from self refresh: ");
 140                 int loops = 0;
 141                 do {
 142                         loops++;
 143                         if ((loops & 1023) == 0) {
 144                                 printk(BIOS_DEBUG, ".");
 145                         }
 146                         dcm =
 147                             pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
 148                 } while (((dcm & DCM_MemClrStatus) ==
 149                           0) /* || ((dcm & DCM_DramEnabled) == 0) */ );
 150
 151                 if (loops >= TIMEOUT_LOOPS) {
 152                         printk(BIOS_DEBUG, "timeout with with cntrl[%d]\n", i);
 153                         continue;
 154                 }
 155
 156                 printk(BIOS_DEBUG, " done\n");
 157         }
 158
 159 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 160         /* init hw mem hole here */
 161         /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
 162         set_hw_mem_hole(controllers, ctrl);
 163 #endif
 164
 165         /* store tom to sysinfo, and it will be used by dqs_timing */
 166         {
 167                 msr_t msr;
 168                 //[1M, TOM)
 169                 msr = rdmsr(TOP_MEM);
 170                 sysinfo->tom_k = ((msr.hi << 24) | (msr.lo >> 8)) >> 2;
 171
 172                 //[4G, TOM2)
 173                 msr = rdmsr(TOP_MEM2);
 174                 sysinfo->tom2_k = ((msr.hi << 24) | (msr.lo >> 8)) >> 2;
 175         }
 176
 177         for (i = 0; i < controllers; i++) {
 178
 179                 if (!sysinfo->ctrl_present[i])
 180                         continue;
 181
 182                 /* Skip everything if I don't have any memory on this controller */
 183                 if (sysinfo->meminfo[i].dimm_mask == 0x00)
 184                         continue;
 185
 186                 dqs_restore_MC_NVRAM((ctrl + i)->f2);
 187                 sysinfo->mem_trained[i] = 1;    // mem was trained
 188         }
 189 }