1 /* coherent hypertransport initialization for AMD64
3 * written by Stefan Reinauer <stepan@openbios.org>
4 * (c) 2003-2004 by SuSE Linux AG
6 * (c) 2004 Tyan Computer
7 * 2004.12 yhlu added support to create routing table dynamically.
8 * it also support 8 ways too. (8 ways ladder or 8 ways crossbar)
10 * This code is licensed under GPL.
14 * This algorithm assumes a grid configuration as follows:
17 * org. : 1x1 2x1 2x2 2x3 2x4
66 #include <device/pci_def.h>
67 #include <device/pci_ids.h>
68 #include <device/hypertransport_def.h>
70 #include "arch/romcc_io.h"
74 #define enable_bsp_routing() enable_routing(0)
76 #define NODE_HT(x) PCI_DEV(0,24+x,0)
77 #define NODE_MP(x) PCI_DEV(0,24+x,1)
78 #define NODE_MC(x) PCI_DEV(0,24+x,3)
80 #define DEFAULT 0x00010101 /* default row entry */
83 #ifndef CROSS_BAR_47_56
84 #define CROSS_BAR_47_56 0
87 #ifndef TRY_HIGH_FIRST
88 #define TRY_HIGH_FIRST 0
91 #ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT
92 #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0
95 #ifndef K8_HT_CHECK_PENDING_LINK
96 #if CONFIG_MAX_PHYSICAL_CPUS >= 4
97 #define K8_HT_CHECK_PENDING_LINK 1
99 #define K8_HT_CHECK_PENDING_LINK 0
103 #ifndef CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
104 #define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0
107 #ifndef CONFIG_ENABLE_APIC_EXT_ID
108 #define CONFIG_ENABLE_APIC_EXT_ID 0
112 static inline void print_linkn (const char *strval, uint8_t byteval)
114 printk(BIOS_DEBUG, "%s%02x\n", strval, byteval);
117 static void disable_probes(void)
119 /* disable read/write/fill probes for uniprocessor setup
120 * they don't make sense if only one cpu is available
123 /* Hypetransport Transaction Control Register
125 * [ 0: 0] Disable read byte probe
127 * 1 = Probes not issued
128 * [ 1: 1] Disable Read Doubleword probe
130 * 1 = Probes not issued
131 * [ 2: 2] Disable write byte probes
133 * 1 = Probes not issued
134 * [ 3: 3] Disable Write Doubleword Probes
136 * 1 = Probes not issued.
137 * [10:10] Disable Fill Probe
138 * 0 = Probes issued for cache fills
139 * 1 = Probes not issued for cache fills.
144 print_spew("Disabling read/write/fill probes for UP... ");
146 val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL);
147 val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C |
148 HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P |
149 HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
150 pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);
152 print_spew("done.\n");
157 static void enable_apic_ext_id(u8 node)
159 #if CONFIG_ENABLE_APIC_EXT_ID==1
160 #warning "FIXME Is the right place to enable apic ext id here?"
164 val = pci_read_config32(NODE_HT(node), 0x68);
165 val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
166 pci_write_config32(NODE_HT(node), 0x68, val);
171 static void enable_routing(u8 node)
175 /* HT Initialization Control Register
177 * [ 0: 0] Routing Table Disable
178 * 0 = Packets are routed according to routing tables
179 * 1 = Packets are routed according to the default link field
180 * [ 1: 1] Request Disable (BSP should clear this)
181 * 0 = Request packets may be generated
182 * 1 = Request packets may not be generated.
183 * [ 3: 2] Default Link (Read-only)
187 * 11 = CPU on same node
189 * - Scratch bit cleared by a cold reset
190 * [ 5: 5] BIOS Reset Detect
191 * - Scratch bit cleared by a cold reset
192 * [ 6: 6] INIT Detect
193 * - Scratch bit cleared by a warm or cold reset not by an INIT
197 /* Enable routing table */
198 print_spew("Enabling routing table for node ");
199 print_spew_hex8(node);
201 val=pci_read_config32(NODE_HT(node), 0x6c);
202 val &= ~((1<<1)|(1<<0));
203 pci_write_config32(NODE_HT(node), 0x6c, val);
205 print_spew(" done.\n");
208 static void fill_row(u8 node, u8 row, u32 value)
210 pci_write_config32(NODE_HT(node), 0x40+(row<<2), value);
213 #if CONFIG_MAX_PHYSICAL_CPUS > 1
214 static u8 link_to_register(int ldt)
217 * [ 0: 3] Request Route
218 * [0] Route to this node
219 * [1] Route to Link 0
220 * [2] Route to Link 1
221 * [3] Route to Link 2
224 if (ldt&0x08) return 0x40;
225 if (ldt&0x04) return 0x20;
226 if (ldt&0x02) return 0x00;
228 /* we should never get here */
229 print_spew("Unknown Link\n");
233 static u32 get_row(u8 node, u8 row)
235 return pci_read_config32(NODE_HT(node), 0x40+(row<<2));
238 static int link_connection(u8 src, u8 dest)
240 return get_row(src, dest) & 0x0f;
243 static void rename_temp_node(u8 node)
247 print_spew("Renaming current temporary node to ");
248 print_spew_hex8(node);
250 val=pci_read_config32(NODE_HT(7), 0x60);
251 val &= (~7); /* clear low bits. */
252 val |= node; /* new node */
253 pci_write_config32(NODE_HT(7), 0x60, val);
255 print_spew(" done.\n");
258 static int verify_connection(u8 dest)
260 /* See if we have a valid connection to dest */
263 /* Verify that the coherent hypertransport link is
264 * established and actually working by reading the
265 * remode node's vendor/device id
267 val = pci_read_config32(NODE_HT(dest),0);
268 if(val != 0x11001022)
274 static uint16_t read_freq_cap(device_t dev, uint8_t pos)
276 /* Handle bugs in valid hypertransport frequency reporting */
280 freq_cap = pci_read_config16(dev, pos);
281 freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
283 #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
284 #if CONFIG_K8_REV_F_SUPPORT == 0
285 if (!is_cpu_pre_e0())
292 id = pci_read_config32(dev, 0);
294 /* AMD K8 Unsupported 1Ghz? */
295 if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
296 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
302 static int optimize_connection(device_t node1, uint8_t link1, device_t node2, uint8_t link2)
304 static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
305 static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
306 uint16_t freq_cap1, freq_cap2;
307 uint8_t width_cap1, width_cap2, width, old_width, ln_width1, ln_width2;
308 uint8_t freq, old_freq;
310 /* Set link width and frequency */
312 /* Initially assume everything is already optimized and I don't need a reset */
315 /* Get the frequency capabilities */
316 freq_cap1 = read_freq_cap(node1, link1 + PCI_HT_CAP_HOST_FREQ_CAP);
317 freq_cap2 = read_freq_cap(node2, link2 + PCI_HT_CAP_HOST_FREQ_CAP);
319 /* Calculate the highest possible frequency */
320 freq = log2(freq_cap1 & freq_cap2);
322 /* See if I am changing the link freqency */
323 old_freq = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ);
325 needs_reset |= old_freq != freq;
326 old_freq = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ);
328 needs_reset |= old_freq != freq;
330 /* Set the Calulcated link frequency */
331 pci_write_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ, freq);
332 pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ, freq);
334 /* Get the width capabilities */
335 width_cap1 = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH);
336 width_cap2 = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH);
338 /* Calculate node1's input width */
339 ln_width1 = link_width_to_pow2[width_cap1 & 7];
340 ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
341 if (ln_width1 > ln_width2) {
342 ln_width1 = ln_width2;
344 width = pow2_to_link_width[ln_width1];
345 /* Calculate node1's output width */
346 ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
347 ln_width2 = link_width_to_pow2[width_cap2 & 7];
348 if (ln_width1 > ln_width2) {
349 ln_width1 = ln_width2;
351 width |= pow2_to_link_width[ln_width1] << 4;
353 /* See if I am changing node1's width */
354 old_width = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1);
356 needs_reset |= old_width != width;
358 /* Set node1's widths */
359 pci_write_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1, width);
361 // * Calculate node2's width */
362 width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
364 /* See if I am changing node2's width */
365 old_width = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1);
367 needs_reset |= old_width != width;
369 /* Set node2's widths */
370 pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1, width);
375 static uint8_t get_linkn_first(uint8_t byte)
377 if(byte & 0x02) { byte = 0; }
378 else if(byte & 0x04) { byte = 1; }
379 else if(byte & 0x08) { byte = 2; }
383 #if TRY_HIGH_FIRST == 1
384 static uint8_t get_linkn_last(uint8_t byte)
386 if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; }
387 if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; }
388 if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; }
393 #if (CONFIG_MAX_PHYSICAL_CPUS > 2) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
394 static uint8_t get_linkn_last_count(uint8_t byte)
397 if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; }
398 if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; }
399 if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
404 static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/
409 for(linkn = 0; linkn<3; linkn++) {
412 regpos = 0x98 + 0x20 * linkn;
413 reg = pci_read_config32(NODE_HT(source), regpos);
414 if ((reg & 0x17) != 3) continue; /* it is not conherent or not connected*/
419 fill_row(source,row, val);
422 static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn)
427 val |= 1<<(linkn+1+8); /*for direct connect response route should equal to request table*/
429 if(((source &1)!=(dest &1))
431 && ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here
432 //(6,5) (7,4) should be here
437 /*for CROSS_BAR_47_56 47, 56, should be here too
438 and for 47, 56, 57, 75, 46, 64 we need to substract another link to
441 val_s = get_row(temp, source);
442 val |= ((val_s>>16) - (1<<(linkn+1)))<<16;
445 fill_row(temp,dest, val );
449 static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) {
451 val = get_row(source, dest);
452 val -= link_connection(source, kickout)<<16;
453 fill_row(source, dest, val);
456 static void opt_broadcast_rt_group(const u8 *conn, int num) {
459 for(i=0; i<num; i+=3) {
460 opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
463 static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) {
465 val = get_row(source, dest);
466 val += link_connection(source, kickout)<<16;
467 fill_row(source, dest, val);
470 static void opt_broadcast_rt_plus_group(const u8 *conn, int num) {
473 for(i=0; i<num; i+=3) {
474 opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]);
479 static void setup_row_direct(u8 source, u8 dest, u8 linkn){
480 setup_row_direct_x(source, source, dest, linkn);
483 static void setup_remote_row_direct(u8 source, u8 dest, u8 linkn){
484 setup_row_direct_x(7, source, dest, linkn);
487 static void setup_temp_row(u8 source, u8 dest)
489 /* copy val from (source, dest) to (source,7) */
490 fill_row(source,7,get_row(source,dest));
494 static void clear_temp_row(u8 source)
496 fill_row(source, 7, DEFAULT);
500 static void setup_remote_node(u8 node)
502 static const uint8_t pci_reg[] = {
503 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c,
504 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78,
505 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc,
506 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8,
507 0xc4, 0xcc, 0xd4, 0xdc,
508 0xc0, 0xc8, 0xd0, 0xd8,
509 0xe0, 0xe4, 0xe8, 0xec,
513 print_spew("setup_remote_node: ");
515 /* copy the default resource map from node 0 */
516 for(i = 0; i < ARRAY_SIZE(pci_reg); i++) {
520 value = pci_read_config32(NODE_MP(0), reg);
521 pci_write_config32(NODE_MP(7), reg, value);
524 print_spew("done\n");
527 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/
530 #if CONFIG_MAX_PHYSICAL_CPUS > 2
532 static void setup_row_indirect_x(u8 temp, u8 source, u8 dest)
534 static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 diff)
537 /*for indirect connection, we need to compute the val from val_s(source, source), and val_g(source, gateway) */
544 gateway = source + 2;
546 gateway = source - 2;
549 val_s = get_row(temp, source);
550 val = get_row(temp, gateway);
557 diff = ((source&1)!=(dest &1));
560 if(diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/
562 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
564 /* Some node have two links left
565 * don't worry we only have (2, (3 as source need to handle
568 byte = get_linkn_last_count(byte);
569 if((byte>>2)>1) { /* make sure not the corner*/
571 val_s-=link_connection(temp, source-2); /* -down*/
576 val_s-=link_connection(temp, 6); // for 7,2 via 5
577 } else if (source==6){
578 val_s-=link_connection(temp, 7); // for 6,3 via 4
581 if (source < gateway) { // for 5, 4 via 7
582 val_s-=link_connection(temp, source-2);
585 val_s-=link_connection(temp, source+2); /* -up*/
593 if(diff) { /* cross rung?*/
597 val_s = get_row(temp, source);
598 val |= ((val_s>>16) - link_connection(temp, gateway))<<16;
601 fill_row(temp, dest, val);
606 static void setup_row_indirect(u8 source, u8 dest)
608 setup_row_indirect_x(source, source, dest);
611 static void setup_row_indirect(u8 source, u8 dest, u8 gateway, u8 diff)
613 setup_row_indirect_x(source, source, dest, gateway, diff);
617 static void setup_row_indirect_group(const u8 *conn, int num)
622 for(i=0; i<num; i+=2) {
623 setup_row_indirect(conn[i], conn[i+1]);
625 for(i=0; i<num; i+=4) {
626 setup_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]);
633 static void setup_remote_row_indirect(u8 source, u8 dest)
635 setup_row_indirect_x(7, source, dest);
638 static void setup_remote_row_indirect(u8 source, u8 dest, u8 gateway, u8 diff)
640 setup_row_indirect_x(7, source, dest, gateway, diff);
644 static void setup_remote_row_indirect_group(const u8 *conn, int num)
649 for(i=0; i<num; i+=2) {
650 setup_remote_row_indirect(conn[i], conn[i+1]);
652 for(i=0; i<num; i+=4) {
653 setup_remote_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]);
658 #endif /*CONFIG_MAX_PHYSICAL_CPUS > 2*/
661 static void setup_uniprocessor(void)
663 print_spew("Enabling UP settings\n");
664 #if CONFIG_LOGICAL_CPUS==1
665 unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
671 #if CONFIG_MAX_PHYSICAL_CPUS > 2
672 static int optimize_connection_group(const u8 *opt_conn, int num) {
675 for(i=0; i<num; i+=2) {
676 needs_reset = optimize_connection(
677 NODE_HT(opt_conn[i]), 0x80 + link_to_register(link_connection(opt_conn[i],opt_conn[i+1])),
678 NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])) );
684 #if CONFIG_MAX_PHYSICAL_CPUS > 1
685 static unsigned setup_smp2(void)
692 setup_row_local(0, 0); /* it will update the broadcast RT*/
695 byte = (val>>16) & 0xfe;
696 if(byte<0x2) { /* no coherent connection so get out.*/
701 /* Setup and check a temporary connection to node 1 */
702 #if TRY_HIGH_FIRST == 1
703 byte = get_linkn_last(byte); /* Max Link to node1 */
705 byte = get_linkn_first(byte); /*Min Link to node1 --- according to AMD*/
707 print_linkn("(0,1) link=", byte);
708 setup_row_direct(0,1, byte);
709 setup_temp_row(0, 1);
711 verify_connection(7);
713 /* We found 2 nodes so far */
714 val = pci_read_config32(NODE_HT(7), 0x6c);
715 byte = (val>>2) & 0x3; /*get default link on node7 to node0*/
716 print_linkn("(1,0) link=", byte);
717 setup_row_local(7,1);
718 setup_remote_row_direct(1, 0, byte);
720 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
722 byte = (val>>16) & 0xfe;
723 byte = get_linkn_last_count(byte);
724 if((byte>>2)==3) { /* Oh! we need to treat it as node2. So use another link*/
726 byte = (val>>16) & 0xfe;
727 #if TRY_HIGH_FIRST == 1
728 byte = get_linkn_first(byte); /* Min link to Node1 */
730 byte = get_linkn_last(byte); /* Max link to Node1*/
732 print_linkn("\t-->(0,1) link=", byte);
733 setup_row_direct(0,1, byte);
734 setup_temp_row(0, 1);
736 verify_connection(7);
738 /* We found 2 nodes so far */
739 val = pci_read_config32(NODE_HT(7), 0x6c);
740 byte = (val>>2) & 0x3; /* get default link on node7 to node0*/
741 print_linkn("\t-->(1,0) link=", byte);
742 setup_row_local(7,1);
743 setup_remote_row_direct(1, 0, byte);
747 setup_remote_node(1); /* Setup the regs on the remote node */
748 rename_temp_node(1); /* Rename Node 7 to Node 1 */
749 enable_routing(1); /* Enable routing on Node 1 */
751 /*don't need and it is done by clear_dead_links */
757 #endif /*CONFIG_MAX_PHYSICAL_CPUS > 1 */
759 #if CONFIG_MAX_PHYSICAL_CPUS > 2
761 static unsigned setup_smp4(void)
769 /* Setup and check temporary connection from Node 0 to Node 2 */
771 byte = ((val>>16) & 0xfe) - link_connection(0,1);
772 byte = get_linkn_last_count(byte);
774 if((byte>>2)==0) { /* We should have two coherent for 4p and above*/
779 byte &= 3; /* bit [3,2] is count-1*/
780 print_linkn("(0,2) link=", byte);
781 setup_row_direct(0, 2, byte); /*(0,2) direct link done*/
783 /* We found 3 nodes so far. Now setup a temporary
784 * connection from node 0 to node 3 via node 1
786 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
787 /* here should setup_row_direct(1,3) at first, before that we should find the link in node 1 to 3*/
789 byte = ((val>>16) & 0xfe) - link_connection(1,0);
790 byte = get_linkn_first(byte);
791 print_linkn("(1,3) link=", byte);
792 setup_row_direct(1,3,byte); /* (1, 3) direct link done*/
794 /* We found 4 nodes so far. Now setup all nodes for 4p */
795 // We need to make sure 0,2 and 1,3 link is set already
797 static const u8 conn4_1[] = {
802 static const u8 conn4_1[] = {
808 setup_row_indirect_group(conn4_1, ARRAY_SIZE(conn4_1));
811 verify_connection(7);
812 val = pci_read_config32(NODE_HT(7), 0x6c);
813 byte = (val>>2) & 0x3; /* get default link on 7 to 0*/
814 print_linkn("(2,0) link=", byte);
816 setup_row_local(7,2);
817 setup_remote_row_direct(2, 0, byte); /* node 2 to node 0 direct link done */
818 setup_remote_node(2); /* Setup the regs on the remote node */
820 rename_temp_node(2); /* Rename Node 7 to Node 2 */
821 enable_routing(2); /* Enable routing on Node 2 */
825 verify_connection(7);
827 val = pci_read_config32(NODE_HT(7), 0x6c);
828 byte = (val>>2) & 0x3; /* get default link on 7 to 1*/
829 print_linkn("(3,1) link=", byte);
831 setup_row_local(7,3);
832 setup_remote_row_direct(3, 1, byte); /* node 3 to node 1 direct link done */
833 setup_remote_node(3); /* Setup the regs on the remote node */
835 /* We need to init link between 2, and 3 direct link */
837 byte = ((val>>16) & 0xfe) - link_connection(2,0);
838 byte = get_linkn_last_count(byte);
839 print_linkn("(2,3) link=", byte & 3);
841 setup_row_direct(2,3, byte & 0x3);
844 verify_connection(7); /* to 3*/
846 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
847 /* We need to find out which link is to node3 */
848 if((byte>>2)==2) { /* one to node3, one to node0, one to node4*/
850 if((val>>16) == 1) { /* that link is to node4, because via node1 it has been set, recompute it*/
852 byte = ((val>>16) & 0xfe) - link_connection(2,0);
853 byte = get_linkn_first(byte);
854 print_linkn("\t-->(2,3) link=", byte);
855 setup_row_direct(2,3,byte);
857 verify_connection(7); /* to 3*/
862 val = pci_read_config32(NODE_HT(7), 0x6c);
863 byte = (val>>2) & 0x3; /* get default link on 7 to 2*/
864 print_linkn("(3,2) link=", byte);
865 setup_remote_row_direct(3,2, byte);
867 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
868 /* set link from 3 to 5 before enable it*/
870 byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1);
871 byte = get_linkn_last_count(byte);
872 if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/
873 byte &= 3; /*bit [3,2] is count-2*/
874 print_linkn("(3,5) link=", byte);
875 setup_remote_row_direct(3, 5, byte);
879 byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
880 byte = get_linkn_last_count(byte);
882 if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/
883 byte &= 3; /* bit [3,2] is count-2*/
884 print_linkn("(2,4) link=", byte);
885 setup_row_direct(2, 4, byte);
889 //Beside 3, 1 is set, We need to make sure 3, 5 is set already in case has three link in 3
891 static const u8 conn4_3[] = {
895 static const u8 conn4_3[] = {
899 setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3));
901 /* ready to enable RT for Node 3 */
903 enable_routing(3); /* enable routing on node 3 (temp.) */
905 // beside 2, 0 is set, We need to make sure 2, 4 link is set already in case has three link in 2
907 static const u8 conn4_2[] = {
911 static const u8 conn4_2[] = {
915 setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2));
918 /*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */
919 /* it will be done by clear_dead_links */
928 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 2 */
930 #if CONFIG_MAX_PHYSICAL_CPUS > 4
932 static unsigned setup_smp6(void)
940 /* Setup and check temporary connection from Node 0 to Node 4 through 2*/
942 byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
943 byte = get_linkn_last_count(byte);
945 if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
950 /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3*/
951 /* set link from 3 to 5 before enable it*/
953 byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
954 byte = get_linkn_last_count(byte);
955 if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
960 /* We found 6 nodes so far. Now setup all nodes for 6p */
961 #warning "FIXME we need to find out the correct gateway for 6p"
962 static const u8 conn6_1[] = {
980 setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1));
982 for(byte=0; byte<4; byte+=2) {
983 setup_temp_row(byte,byte+2);
985 verify_connection(7);
986 val = pci_read_config32(NODE_HT(7), 0x6c);
987 byte = (val>>2) & 0x3; /*get default link on 7 to 2*/
988 print_linkn("(4,2) link=", byte);
990 setup_row_local(7,4);
991 setup_remote_row_direct(4, 2, byte);
992 setup_remote_node(4); /* Setup the regs on the remote node */
994 /* Set indirect connection to 0, to 3 */
995 //we only need to set 4,0 here
996 static const u8 conn6_2[] = {
1004 setup_remote_row_indirect_group(conn6_2, ARRAY_SIZE(conn6_2));
1006 rename_temp_node(4);
1009 setup_temp_row(0,1);
1010 for(byte=0; byte<4; byte+=2) {
1011 setup_temp_row(byte+1,byte+3);
1013 verify_connection(7);
1015 val = pci_read_config32(NODE_HT(7), 0x6c);
1016 byte = (val>>2) & 0x3; /* get default link on 7 to 3*/
1017 print_linkn("(5,3) link=", byte);
1018 setup_row_local(7,5);
1019 setup_remote_row_direct(5, 3, byte);
1020 setup_remote_node(5); /* Setup the regs on the remote node */
1022 #if !CROSS_BAR_47_56
1023 /* We need to init link between 4, and 5 direct link */
1025 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1026 byte = get_linkn_last_count(byte);
1027 print_linkn("(4,5) link=", byte & 3);
1029 setup_row_direct(4,5, byte & 0x3);
1030 setup_temp_row(0,2);
1031 setup_temp_row(2,4);
1032 setup_temp_row(4,5);
1033 verify_connection(7); /* to 5*/
1035 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1036 /* We need to find out which link is to node5 */
1038 if((byte>>2)==2) { /* one to node5, one to node2, one to node6*/
1040 if((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/
1042 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1043 byte = get_linkn_first(byte);
1044 print_linkn("\t-->(4,5) link=", byte);
1045 setup_row_direct(4,5,byte);
1046 setup_temp_row(4,5);
1047 verify_connection(7); /* to 5*/
1052 val = pci_read_config32(NODE_HT(7), 0x6c);
1053 byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
1054 print_linkn("(5,4) link=", byte);
1055 setup_remote_row_direct(5,4, byte);
1059 byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3);
1060 byte = get_linkn_last_count(byte);
1061 if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/
1062 byte &= 3; /*bit [3,2] is count-2*/
1063 print_linkn("(5,7) link=", byte);
1064 setup_remote_row_direct(5, 7, byte);
1069 byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
1070 byte = get_linkn_last_count(byte);
1072 if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/
1073 byte &= 3; /* bit [3,2] is count-2*/
1074 print_linkn("(4,6) link=", byte);
1075 setup_row_direct(4, 6, byte);
1080 //We need to set 5,0 here only, We need to set up 5, 7 to make 5,0
1081 /* Set indirect connection to 0, to 3 for indirect we will use clockwise routing */
1082 static const u8 conn6_3[] = {
1083 #if !CROSS_BAR_47_56
1090 setup_remote_row_indirect_group(conn6_3, ARRAY_SIZE(conn6_3));
1092 /* ready to enable RT for 5 */
1093 rename_temp_node(5);
1094 enable_routing(5); /* enable routing on node 5 (temp.) */
1096 static const u8 conn6_4[] = {
1097 #if !CROSS_BAR_47_56
1116 setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4));
1119 /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5)
1120 * It will be done by clear_dead_links
1122 for(byte=0; byte<4; byte++) {
1123 clear_temp_row(byte);
1131 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 4 */
1133 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1135 static unsigned setup_smp8(void)
1143 /* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */
1146 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1148 byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
1149 byte = get_linkn_last_count(byte); /* Max link to 6*/
1150 if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
1157 byte = get_linkn_last_count(byte); /* Max link to 6*/
1158 if((byte>>2)<2) { /* We should have two or three coherent links on node 4 for 8p*/
1162 #if TRY_HIGH_FIRST == 1
1163 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1164 byte = get_linkn_first(byte); /*Min link to 6*/
1166 byte &= 3; /* bit [3,2] is count-1 or 2*/
1168 print_linkn("(4,6) link=", byte);
1169 setup_row_direct(4, 6, byte);
1172 #if !CROSS_BAR_47_56
1173 /* Setup and check temporary connection from Node 0 to Node 7 through 1, 3, 5*/
1175 byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
1176 byte = get_linkn_last_count(byte);
1177 if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
1183 /* We found 8 nodes so far. Now setup all nodes for 8p */
1184 static const u8 conn8_1[] = {
1185 #if !CROSS_BAR_47_56
1208 setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1));
1210 for(byte=0; byte<6; byte+=2) {
1211 setup_temp_row(byte,byte+2);
1213 verify_connection(7);
1214 val = pci_read_config32(NODE_HT(7), 0x6c);
1215 byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
1216 print_linkn("(6,4) link=", byte);
1218 setup_row_local(7,6);
1219 setup_remote_row_direct(6, 4, byte);
1220 setup_remote_node(6); /* Setup the regs on the remote node */
1221 /* Set indirect connection to 0, to 3 */
1222 #warning "FIXME we need to find out the correct gateway for 8p"
1223 static const u8 conn8_2[] = {
1224 #if !CROSS_BAR_47_56
1231 setup_remote_row_indirect_group(conn8_2, ARRAY_SIZE(conn8_2));
1235 /* here init 5, 6 */
1236 /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/
1238 byte = ((val>>16) & 0xfe) - link_connection(5,3);
1239 #if TRY_HIGH_FIRST == 1
1240 byte = get_linkn_first(byte);
1242 byte = get_linkn_last(byte);
1244 print_linkn("(5,6) link=", byte);
1245 setup_row_direct(5, 6, byte);
1247 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
1248 for(byte=0; byte<4; byte+=2) {
1249 setup_temp_row(byte+1,byte+3);
1251 setup_temp_row(5,6);
1253 verify_connection(7);
1255 val = get_row(7,6); // to chect it if it is node6 before renaming
1256 if( (val>>16) == 1) { // it is real node 7 so swap it
1257 /* We need to recompute link to 6 */
1259 byte = ((val>>16) & 0xfe) - link_connection(5,3);
1260 #if TRY_HIGH_FIRST == 1
1261 byte = get_linkn_first(byte);
1263 byte = get_linkn_last(byte);
1265 print_linkn("\t-->(5,6) link=", byte);
1266 setup_row_direct(5, 6, byte);
1268 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
1269 for(byte=0; byte<4; byte+=2) {
1270 setup_temp_row(byte+1,byte+3);
1273 setup_temp_row(5,6);
1275 verify_connection(7);
1277 val = pci_read_config32(NODE_HT(7), 0x6c);
1278 byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
1279 print_linkn("(6,5) link=", byte);
1280 setup_remote_row_direct(6, 5, byte);
1281 /*Till now 56, 65 done */
1284 rename_temp_node(6);
1287 #if !CROSS_BAR_47_56
1288 setup_temp_row(0,1);
1289 for(byte=0; byte<6; byte+=2) {
1290 setup_temp_row(byte+1,byte+3);
1293 verify_connection(7);
1295 val = pci_read_config32(NODE_HT(7), 0x6c);
1296 byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
1297 print_linkn("(7,5) link=", byte);
1298 setup_row_local(7,7);
1299 setup_remote_row_direct(7, 5, byte);
1303 byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6);
1304 byte = get_linkn_first(byte);
1305 print_linkn("(4,7) link=", byte);
1306 setup_row_direct(4, 7, byte);
1308 /* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/
1309 for(byte=0; byte<4; byte+=2) {
1310 setup_temp_row(byte,byte+2);
1313 verify_connection(7);
1315 val = pci_read_config32(NODE_HT(7), 0x6c);
1316 byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
1317 print_linkn("(7,4) link=", byte);
1318 setup_row_local(7,7);
1319 setup_remote_row_direct(7, 4, byte);
1320 /* till now 4-7, 7-4 done. */
1322 setup_remote_node(7); /* Setup the regs on the remote node */
1325 /* here init 5, 7 */
1326 /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/
1328 byte = ((val>>16) & 0xfe) - link_connection(5,3) - link_connection(5,6);
1329 byte = get_linkn_first(byte);
1330 print_linkn("(5,7) link=", byte);
1331 setup_row_direct(5, 7, byte);
1333 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
1334 for(byte=0; byte<4; byte+=2) {
1335 setup_temp_row(byte+1,byte+3);
1338 verify_connection(7);
1340 val = pci_read_config32(NODE_HT(7), 0x6c);
1341 byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
1342 print_linkn("(7,5) link=", byte);
1343 setup_remote_row_direct(7, 5, byte);
1344 /*Till now 57, 75 done */
1348 /* We need to init link between 6, and 7 direct link */
1350 #if !CROSS_BAR_47_56
1351 byte = ((val>>16) & 0xfe) - link_connection(6,4);
1353 byte = ((val>>16) & 0xfe) - link_connection(6,4) - link_connection(6,5);
1355 byte = get_linkn_first(byte);
1356 print_linkn("(6,7) link=", byte);
1357 setup_row_direct(6,7, byte);
1360 #if !CROSS_BAR_47_56
1361 byte = ((val>>16) & 0xfe) - link_connection(7,5);
1363 byte = ((val>>16) & 0xfe) - link_connection(7,5) - link_connection(7,4);
1365 byte = get_linkn_first(byte);
1366 print_linkn("(7,6) link=", byte);
1367 setup_row_direct(7,6, byte);
1369 /* Set indirect connection to 0, to 3 for indirect we will use clockwise routing */
1370 static const u8 conn8_3[] = {
1371 #if !CROSS_BAR_47_56
1372 0, 7, /* restore it*/
1394 6, 1, 5, 0, // or 4, 1
1396 6, 3, 5, 0, // or 4, 1
1398 7, 0, 4, 0, // or 5, 1
1400 7, 2, 4, 0, // or 5, 1
1403 0, 7, 2, 0, /* restore it*/
1408 2, 5, 4, 1, /* reset it */
1411 4, 1, 2, 1, /* reset it */
1414 5, 2, 3, 1, /* reset it */
1420 setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3));
1423 /* for 47, 56, 57, 75, 46, 64 we need to substract another link to
1425 static const u8 conn8_4[] = {
1448 6, 1, 7, // needed for via 5
1451 6, 3, 7, // needed for via 5
1453 7, 0, 6, // needed for via 4
1456 7, 2, 6, // needed for via 4
1461 opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4));
1463 static const u8 conn8_5[] = {
1469 opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5));
1474 /* ready to enable RT for Node 7 */
1475 enable_routing(7); /* enable routing on node 7 (temp.) */
1480 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 6 */
1483 #if CONFIG_MAX_PHYSICAL_CPUS > 1
1485 static unsigned setup_smp(void)
1489 print_spew("Enabling SMP settings\n");
1491 nodes = setup_smp2();
1492 #if CONFIG_MAX_PHYSICAL_CPUS > 2
1494 nodes = setup_smp4();
1497 #if CONFIG_MAX_PHYSICAL_CPUS > 4
1499 nodes = setup_smp6();
1502 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1504 nodes = setup_smp8();
1507 printk(BIOS_DEBUG, "%02x nodes initialized.\n", nodes);
1512 static unsigned verify_mp_capabilities(unsigned nodes)
1514 unsigned node, mask;
1516 mask = 0x06; /* BigMPCap */
1518 for (node=0; node<nodes; node++) {
1519 mask &= pci_read_config32(NODE_MC(node), 0xe8);
1523 #if CONFIG_MAX_PHYSICAL_CPUS > 2
1524 case 0x02: /* MPCap */
1526 print_err("Going back to DP\n");
1531 case 0x00: /* Non SMP */
1533 print_err("Going back to UP\n");
1544 static void clear_dead_routes(unsigned nodes)
1548 #if CONFIG_MAX_PHYSICAL_CPUS == 8
1549 if(nodes==8) return;/* don't touch (7,7)*/
1555 for(node = 7; node >= 0; node--) {
1556 for(row = 7; row >= last_row; row--) {
1557 fill_row(node, row, DEFAULT);
1561 /* Update the local row */
1562 for( node=0; node<nodes; node++) {
1564 for(row =0; row<nodes; row++) {
1565 val |= get_row(node, row);
1567 fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101);
1570 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
1572 #if CONFIG_LOGICAL_CPUS==1
1573 static unsigned verify_dualcore(unsigned nodes)
1575 unsigned node, totalcpus, tmp;
1578 for (node=0; node<nodes; node++) {
1579 tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ;
1580 totalcpus += (tmp + 1);
1588 static void coherent_ht_finalize(unsigned nodes)
1591 #if CONFIG_K8_REV_F_SUPPORT == 0
1594 #if CONFIG_LOGICAL_CPUS==1
1595 unsigned total_cpus;
1597 if ((!CONFIG_HAVE_OPTION_TABLE) ||
1598 read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */
1599 total_cpus = verify_dualcore(nodes);
1606 /* set up cpu count and node count and enable Limit
1607 * Config Space Range for all available CPUs.
1608 * Also clear non coherent hypertransport bus range
1609 * registers on Hammer A0 revision.
1612 print_spew("coherent_ht_finalize\n");
1613 #if CONFIG_K8_REV_F_SUPPORT == 0
1614 rev_a0 = is_cpu_rev_a0();
1616 for (node = 0; node < nodes; node++) {
1619 dev = NODE_HT(node);
1621 /* Set the Total CPU and Node count in the system */
1622 val = pci_read_config32(dev, 0x60);
1623 val &= (~0x000F0070);
1624 #if CONFIG_LOGICAL_CPUS==1
1625 val |= ((total_cpus-1)<<16)|((nodes-1)<<4);
1627 val |= ((nodes-1)<<16)|((nodes-1)<<4);
1629 pci_write_config32(dev, 0x60, val);
1631 /* Only respond to real cpu pci configuration cycles
1632 * and optimize the HT settings
1634 val=pci_read_config32(dev, HT_TRANSACTION_CONTROL);
1635 val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) |
1636 (HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) |
1637 (HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT));
1638 val |= HTTC_LIMIT_CLDT_CFG |
1639 (HTTC_BUF_REL_PRI_8 << HTTC_BUF_REL_PRI_SHIFT) |
1640 (3 << HTTC_MED_PRI_BYP_CNT_SHIFT) |
1641 (3 << HTTC_HI_PRI_BYP_CNT_SHIFT);
1642 pci_write_config32(dev, HT_TRANSACTION_CONTROL, val);
1644 #if CONFIG_K8_REV_F_SUPPORT == 0
1646 pci_write_config32(dev, 0x94, 0);
1647 pci_write_config32(dev, 0xb4, 0);
1648 pci_write_config32(dev, 0xd4, 0);
1653 print_spew("done\n");
1656 static int apply_cpu_errata_fixes(unsigned nodes)
1659 int needs_reset = 0;
1660 for(node = 0; node < nodes; node++) {
1661 #if CONFIG_K8_REV_F_SUPPORT == 0
1664 dev = NODE_MC(node);
1665 if (is_cpu_pre_c0()) {
1668 * Limit the number of downstream posted requests to 1
1670 cmd = pci_read_config32(dev, 0x70);
1671 if ((cmd & (3 << 0)) != 2) {
1674 pci_write_config32(dev, 0x70, cmd );
1677 cmd = pci_read_config32(dev, 0x7c);
1678 if ((cmd & (3 << 4)) != 0) {
1681 pci_write_config32(dev, 0x7c, cmd );
1684 /* Clock Power/Timing Low */
1685 cmd = pci_read_config32(dev, 0xd4);
1686 if (cmd != 0x000D0001) {
1688 pci_write_config32(dev, 0xd4, cmd);
1689 needs_reset = 1; /* Needed? */
1693 else if (is_cpu_pre_d0()) { // d0 later don't need it
1696 * Set Clk Ramp Hystersis to 7
1697 * Clock Power/Timing Low
1699 cmd_ref = 0x04e20707; /* Registered */
1700 cmd = pci_read_config32(dev, 0xd4);
1701 if(cmd != cmd_ref) {
1702 pci_write_config32(dev, 0xd4, cmd_ref );
1703 needs_reset = 1; /* Needed? */
1711 static int optimize_link_read_pointers(unsigned nodes)
1714 int needs_reset = 0;
1715 for(node = 0; node < nodes; node++) {
1716 device_t f0_dev, f3_dev;
1717 uint32_t cmd_ref, cmd;
1719 f0_dev = NODE_HT(node);
1720 f3_dev = NODE_MC(node);
1721 cmd_ref = cmd = pci_read_config32(f3_dev, 0xdc);
1722 for(link = 0; link < 3; link++) {
1725 /* This works on an Athlon64 because unimplemented links return 0 */
1726 reg = 0x98 + (link * 0x20);
1727 link_type = pci_read_config32(f0_dev, reg);
1728 /* Only handle coherent links */
1729 if ((link_type & (LinkConnected | InitComplete|NonCoherent)) ==
1730 (LinkConnected|InitComplete))
1732 cmd &= ~(0xff << (link *8));
1733 cmd |= 0x25 << (link *8);
1736 if (cmd != cmd_ref) {
1737 pci_write_config32(f3_dev, 0xdc, cmd);
1744 static inline unsigned get_nodes(void)
1746 return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
1749 static int optimize_link_coherent_ht(void)
1751 int needs_reset = 0;
1755 nodes = get_nodes();
1757 #if CONFIG_MAX_PHYSICAL_CPUS > 1
1759 needs_reset |= optimize_connection(
1760 NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
1761 NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
1764 #if CONFIG_MAX_PHYSICAL_CPUS > 2
1766 /* optimize physical connections - by LYH */
1767 static const u8 opt_conn4[] = {
1772 needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4));
1776 #if CONFIG_MAX_PHYSICAL_CPUS > 4
1778 static const uint8_t opt_conn6[] ={
1781 #if !CROSS_BAR_47_56
1785 needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6));
1789 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1791 static const uint8_t opt_conn8[] ={
1800 needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8));
1806 needs_reset |= apply_cpu_errata_fixes(nodes);
1807 needs_reset |= optimize_link_read_pointers(nodes);
1812 #if RAMINIT_SYSINFO == 1
1813 static void setup_coherent_ht_domain(void)
1815 static int setup_coherent_ht_domain(void)
1821 enable_bsp_routing();
1823 #if CONFIG_MAX_PHYSICAL_CPUS > 1
1824 nodes = setup_smp();
1825 nodes = verify_mp_capabilities(nodes);
1826 clear_dead_routes(nodes);
1830 setup_uniprocessor();
1832 coherent_ht_finalize(nodes);
1834 #if RAMINIT_SYSINFO == 0
1835 return optimize_link_coherent_ht();