1 static void setup_coherent_ht_domain(void)
3 static const unsigned int register_values[] = {
4 /* Routing Table Node i
13 * [ 0: 3] Request Route
14 * [0] Route to this node
18 * [11: 8] Response Route
19 * [0] Route to this node
23 * [19:16] Broadcast route
24 * [0] Route to this node
29 PCI_ADDR(0, 0x18, 0, 0x40), 0xfff0f0f0, 0x00010101,
30 PCI_ADDR(0, 0x18, 0, 0x44), 0xfff0f0f0, 0x00010101,
31 PCI_ADDR(0, 0x18, 0, 0x48), 0xfff0f0f0, 0x00010101,
32 PCI_ADDR(0, 0x18, 0, 0x4c), 0xfff0f0f0, 0x00010101,
33 PCI_ADDR(0, 0x18, 0, 0x50), 0xfff0f0f0, 0x00010101,
34 PCI_ADDR(0, 0x18, 0, 0x54), 0xfff0f0f0, 0x00010101,
35 PCI_ADDR(0, 0x18, 0, 0x58), 0xfff0f0f0, 0x00010101,
36 PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101,
38 /* Hypetransport Transaction Control Register
40 * [ 0: 0] Disable read byte probe
42 * 1 = Probes not issued
43 * [ 1: 1] Disable Read Doubleword probe
45 * 1 = Probes not issued
46 * [ 2: 2] Disable write byte probes
48 * 1 = Probes not issued
49 * [ 3: 3] Disable Write Doubleword Probes
51 * 1 = Probes not issued.
52 * [ 4: 4] Disable Memroy Controller Target Start
53 * 0 = TgtStart packets are generated
54 * 1 = TgtStart packets are not generated.
56 * 0 = Second CPU disabled or not present
57 * 1 = Second CPU enabled.
58 * [ 6: 6] CPU Request PassPW
59 * 0 = CPU requests do not pass posted writes
60 * 1 = CPU requests pass posted writes.
61 * [ 7: 7] CPU read Respons PassPW
62 * 0 = CPU Responses do not pass posted writes
63 * 1 = CPU responses pass posted writes.
64 * [ 8: 8] Disable Probe Memory Cancel
65 * 0 = Probes may generate MemCancels
66 * 1 = Probes may not generate MemCancels
67 * [ 9: 9] Disable Remote Probe Memory Cancel.
68 * 0 = Probes hitting dirty blocks generate memory cancel packets
69 * 1 = Only probed caches on the same node as the memory controller
70 * generate cancel packets.
71 * [10:10] Disable Fill Probe
72 * 0 = Probes issued for cache fills
73 * 1 = Probes not issued for cache fills.
74 * [11:11] Response PassPw
75 * 0 = Downstream response PassPW based on original request
76 * 1 = Downstream response PassPW set to 1
77 * [12:12] Change ISOC to Ordered
78 * 0 = Bit 1 of coherent HT RdSz/WrSz command used for iosynchronous prioritization
79 * 1 = Bit 1 of coherent HT RdSz/WrSz command used for ordering.
80 * [14:13] Buffer Release Priority select
85 * [15:15] Limit Coherent HT Configuration Space Range
86 * 0 = No coherent HT configuration space restrictions
87 * 1 = Limit coherent HT configuration space based on node count
88 * [16:16] Local Interrupt Conversion Enable.
89 * 0 = ExtInt/NMI interrups unaffected.
90 * 1 = ExtInt/NMI broadcat interrupts converted to LINT0/1
91 * [17:17] APIC Extended Broadcast Enable.
92 * 0 = APIC broadcast is 0F
93 * 1 = APIC broadcast is FF
94 * [18:18] APIC Extended ID Enable
95 * 0 = APIC ID is 4 bits.
96 * 1 = APIC ID is 8 bits.
97 * [19:19] APIC Extended Spurious Vector Enable
98 * 0 = Lower 4 bits of spurious vector are read-only 1111
99 * 1 = Lower 4 bits of spurious vecotr are writeable.
100 * [20:20] Sequence ID Source Node Enable
101 * 0 = Normal operation
102 * 1 = Keep SeqID on routed packets for debugging.
103 * [22:21] Downstream non-posted request limit
109 * [25:24] Medium-Priority Bypass Count
110 * - Maximum # of times a medium priority access can pass a low
111 * priority access before Medium-Priority mode is disabled for one access.
112 * [27:26] High-Priority Bypass Count
113 * - Maximum # of times a high prioirty access can pass a medium or low
114 * priority access before High-prioirty mode is disabled for one access.
115 * [28:28] Enable High Priority CPU Reads
116 * 0 = Cpu reads are medium prioirty
117 * 1 = Cpu reads are high prioirty
118 * [29:29] Disable Low Priority Writes
119 * 0 = Non-isochronous writes are low priority
120 * 1 = Non-isochronous writes are medium prioirty
121 * [30:30] Disable High Priority Isochronous writes
122 * 0 = Isochronous writes are high priority
123 * 1 = Isochronous writes are medium priority
124 * [31:31] Disable Medium Priority Isochronous writes
125 * 0 = Isochronous writes are medium are high
126 * 1 = With bit 30 set makes Isochrouns writes low priority.
128 PCI_ADDR(0, 0x18, 0, 0x68), 0x00800000, 0x0f00840f,
129 /* HT Initialization Control Register
131 * [ 0: 0] Routing Table Disable
132 * 0 = Packets are routed according to routing tables
133 * 1 = Packets are routed according to the default link field
134 * [ 1: 1] Request Disable (BSP should clear this)
135 * 0 = Request packets may be generated
136 * 1 = Request packets may not be generated.
137 * [ 3: 2] Default Link (Read-only)
141 * 11 = CPU on same node
143 * - Scratch bit cleared by a cold reset
144 * [ 5: 5] BIOS Reset Detect
145 * - Scratch bit cleared by a cold reset
146 * [ 6: 6] INIT Detect
147 * - Scratch bit cleared by a warm or cold reset not by an INIT
150 PCI_ADDR(0, 0x18, 0, 0x6C), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4),
151 /* LDTi Capabilities Registers
156 /* LDTi Link Control Registrs
160 * [ 1: 1] CRC Flood Enable
161 * 0 = Do not generate sync packets on CRC error
162 * 1 = Generate sync packets on CRC error
163 * [ 2: 2] CRC Start Test (Read-Only)
164 * [ 3: 3] CRC Force Frame Error
165 * 0 = Do not generate bad CRC
166 * 1 = Generate bad CRC
167 * [ 4: 4] Link Failure
168 * 0 = No link failure detected
169 * 1 = Link failure detected
170 * [ 5: 5] Initialization Complete
171 * 0 = Initialization not complete
172 * 1 = Initialization complete
173 * [ 6: 6] Receiver off
176 * [ 7: 7] Transmitter Off
178 * 1 = Transmitter off
181 * [0] = 1 Error on byte lane 0
182 * [1] = 1 Error on byte lane 1
183 * [12:12] Isochrnous Enable (Read-Only)
184 * [13:13] HT Stop Tristate Enable
185 * 0 = Driven during an LDTSTOP_L
186 * 1 = Tristated during and LDTSTOP_L
187 * [14:14] Extended CTL Time
188 * 0 = CTL is asserted for 16 bit times during link initialization
189 * 1 = CTL is asserted for 50us during link initialization
190 * [18:16] Max Link Width In (Read-Only?)
193 * [19:19] Doubleword Flow Control in (Read-Only)
194 * 0 = This link does not support doubleword flow control
195 * 1 = This link supports doubleword flow control
196 * [22:20] Max Link Width Out (Read-Only?)
199 * [23:23] Doubleworld Flow Control out (Read-Only)
200 * 0 = This link does not support doubleword flow control
201 * 1 = This link supports doubleworkd flow control
202 * [26:24] Link Width In
210 * 111 = Link physically not connected
211 * [27:27] Doubleword Flow Control In Enable
212 * 0 = Doubleword flow control disabled
213 * 1 = Doubleword flow control enabled (Not currently supported)
214 * [30:28] Link Width Out
222 * 111 = Link physically not connected
223 * [31:31] Doubleworld Flow Control Out Enable
224 * 0 = Doubleworld flow control disabled
225 * 1 = Doubleword flow control enabled (Not currently supported)
227 PCI_ADDR(0, 0x18, 0, 0x84), 0x00009c05, 0x11110020,
228 /* LDTi Frequency/Revision Registers
232 * [ 4: 0] Minor Revision
233 * Contains the HT Minor revision
234 * [ 7: 5] Major Revision
235 * Contains the HT Major revision
236 * [11: 8] Link Frequency (Takes effect the next time the link is reconnected)
253 * [15:12] Error (Not currently Implemented)
254 * [31:16] Indicates the frequency capabilities of the link
255 * [16] = 1 encoding 0000 of freq supported
256 * [17] = 1 encoding 0001 of freq supported
257 * [18] = 1 encoding 0010 of freq supported
258 * [19] = 1 encoding 0011 of freq supported
259 * [20] = 1 encoding 0100 of freq supported
260 * [21] = 1 encoding 0101 of freq supported
261 * [22] = 1 encoding 0110 of freq supported
262 * [23] = 1 encoding 0111 of freq supported
263 * [24] = 1 encoding 1000 of freq supported
264 * [25] = 1 encoding 1001 of freq supported
265 * [26] = 1 encoding 1010 of freq supported
266 * [27] = 1 encoding 1011 of freq supported
267 * [28] = 1 encoding 1100 of freq supported
268 * [29] = 1 encoding 1101 of freq supported
269 * [30] = 1 encoding 1110 of freq supported
270 * [31] = 1 encoding 1111 of freq supported
272 PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000200,
273 /* LDTi Feature Capability
278 /* LDTi Buffer Count Registers
283 /* LDTi Bus Number Registers
287 * For NonCoherent HT specifies the bus number downstream (behind the host bridge)
288 * [ 0: 7] Primary Bus Number
289 * [15: 8] Secondary Bus Number
290 * [23:15] Subordiante Bus Number
293 PCI_ADDR(0, 0x18, 0, 0x94), 0xff000000, 0x00ff0000,
294 /* LDTi Type Registers
299 /* Careful set limit registers before base registers which contain the enables */
300 /* DRAM Limit i Registers
309 * [ 2: 0] Destination Node ID
319 * [10: 8] Interleave select
320 * specifies the values of A[14:12] to use with interleave enable.
322 * [31:16] DRAM Limit Address i Bits 39-24
323 * This field defines the upper address bits of a 40 bit address
324 * that define the end of the DRAM region.
327 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000,
330 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x001f0000,
332 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
333 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
334 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
335 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
336 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
337 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
338 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
339 /* DRAM Base i Registers
348 * [ 0: 0] Read Enable
351 * [ 1: 1] Write Enable
352 * 0 = Writes Disabled
355 * [10: 8] Interleave Enable
356 * 000 = No interleave
357 * 001 = Interleave on A[12] (2 nodes)
359 * 011 = Interleave on A[12] and A[14] (4 nodes)
363 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
365 * [13:16] DRAM Base Address i Bits 39-24
366 * This field defines the upper address bits of a 40-bit address
367 * that define the start of the DRAM region.
369 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000003,
371 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400000,
372 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00400000,
373 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00400000,
374 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00400000,
375 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00400000,
376 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00400000,
377 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00400000,
380 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00200000,
381 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00200000,
382 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00200000,
383 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00200000,
384 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00200000,
385 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00200000,
386 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00200000,
389 /* Memory-Mapped I/O Limit i Registers
398 * [ 2: 0] Destination Node ID
408 * [ 5: 4] Destination Link ID
415 * 0 = CPU writes may be posted
416 * 1 = CPU writes must be non-posted
417 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
418 * This field defines the upp adddress bits of a 40-bit address that
419 * defines the end of a memory-mapped I/O region n
421 PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00,
422 PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00dfff00,
423 PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00e3ff00,
424 PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
425 PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
426 PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
427 PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000b00,
428 PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00fe0b00,
430 /* Memory-Mapped I/O Base i Registers
439 * [ 0: 0] Read Enable
442 * [ 1: 1] Write Enable
443 * 0 = Writes disabled
445 * [ 2: 2] Cpu Disable
446 * 0 = Cpu can use this I/O range
447 * 1 = Cpu requests do not use this I/O range
449 * 0 = base/limit registers i are read/write
450 * 1 = base/limit registers i are read-only
452 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
453 * This field defines the upper address bits of a 40bit address
454 * that defines the start of memory-mapped I/O region i
456 PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003,
457 PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00d80003,
458 PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00e20003,
459 PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
460 PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
461 PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
462 PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000a03,
464 PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00400003,
467 PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00200003,
470 /* PCI I/O Limit i Registers
475 * [ 2: 0] Destination Node ID
485 * [ 5: 4] Destination Link ID
491 * [24:12] PCI I/O Limit Address i
492 * This field defines the end of PCI I/O region n
495 PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x0000d000,
496 PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x000ff000,
497 PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
498 PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
500 /* PCI I/O Base i Registers
505 * [ 0: 0] Read Enable
508 * [ 1: 1] Write Enable
509 * 0 = Writes Disabled
513 * 0 = VGA matches Disabled
514 * 1 = matches all address < 64K and where A[9:0] is in the
515 * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
517 * 0 = ISA matches Disabled
518 * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
519 * from matching agains this base/limit pair
521 * [24:12] PCI I/O Base i
522 * This field defines the start of PCI I/O region n
525 PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003,
526 PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00001013,
527 PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
528 PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
530 /* Config Base and Limit i Registers
535 * [ 0: 0] Read Enable
538 * [ 1: 1] Write Enable
539 * 0 = Writes Disabled
541 * [ 2: 2] Device Number Compare Enable
542 * 0 = The ranges are based on bus number
543 * 1 = The ranges are ranges of devices on bus 0
545 * [ 6: 4] Destination Node
555 * [ 9: 8] Destination Link
561 * [23:16] Bus Number Base i
562 * This field defines the lowest bus number in configuration region i
563 * [31:24] Bus Number Limit i
564 * This field defines the highest bus number in configuration regin i
566 PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
567 PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
568 PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
569 PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
574 print_debug("setting up coherent ht domain....\r\n");
575 max = sizeof(register_values)/sizeof(register_values[0]);
576 for(i = 0; i < max; i += 3) {
579 print_debug_hex32(register_values[i]);
581 print_debug_hex32(register_values[i+2]);
584 reg = pci_read_config32(register_values[i]);
585 reg &= register_values[i+1];
586 reg |= register_values[i+2] & ~register_values[i+1];
587 pci_write_config32(register_values[i], reg);
589 print_debug("done.\r\n");