1 /* Definitions of various K8 registers */
3 #define HT_TRANSACTION_CONTROL 0x68
4 #define HTTC_DIS_RD_B_P (1 << 0)
5 #define HTTC_DIS_RD_DW_P (1 << 1)
6 #define HTTC_DIS_WR_B_P (1 << 2)
7 #define HTTC_DIS_WR_DW_P (1 << 3)
8 #define HTTC_DIS_MTS (1 << 4)
9 #define HTTC_CPU1_EN (1 << 5)
10 #define HTTC_CPU_REQ_PASS_PW (1 << 6)
11 #define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
12 #define HTTC_DIS_P_MEM_C (1 << 8)
13 #define HTTC_DIS_RMT_MEM_C (1 << 9)
14 #define HTTC_DIS_FILL_P (1 << 10)
15 #define HTTC_RSP_PASS_PW (1 << 11)
16 #define HTTC_CHG_ISOC_TO_ORD (1 << 12)
17 #define HTTC_BUF_REL_PRI_SHIFT 13
18 #define HTTC_BUF_REL_PRI_MASK 3
19 #define HTTC_BUF_REL_PRI_64 0
20 #define HTTC_BUF_REL_PRI_16 1
21 #define HTTC_BUF_REL_PRI_8 2
22 #define HTTC_BUF_REL_PRI_2 3
23 #define HTTC_LIMIT_CLDT_CFG (1 << 15)
24 #define HTTC_LINT_EN (1 << 16)
25 #define HTTC_APIC_EXT_BRD_CST (1 << 17)
26 #define HTTC_APIC_EXT_ID (1 << 18)
27 #define HTTC_APIC_EXT_SPUR (1 << 19)
28 #define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
29 #define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
30 #define HTTC_DS_NP_REQ_LIMIT_MASK 3
31 #define HTTC_DS_NP_REQ_LIMIT_NONE 0
32 #define HTTC_DS_NP_REQ_LIMIT_1 1
33 #define HTTC_DS_NP_REQ_LIMIT_4 2
34 #define HTTC_DS_NP_REQ_LIMIT_8 3
35 #define HTTC_MED_PRI_BYP_CNT_SHIFT 24
36 #define HTTC_MED_PRI_BYP_CNT_MASK 3
37 #define HTTC_HI_PRI_BYP_CNT_SHIFT 26
38 #define HTTC_HI_PRI_BYP_CNT_MASK 3
42 #define PCI_IO_BASE0 0xc0
43 #define PCI_IO_BASE1 0xc8
44 #define PCI_IO_BASE2 0xd0
45 #define PCI_IO_BASE3 0xd8
46 #define PCI_IO_BASE_VGA_EN (1 << 4)
47 #define PCI_IO_BASE_NO_ISA (1 << 5)
51 #define DRAM_CSBASE 0x40
52 #define DRAM_CSMASK 0x60
53 #define DRAM_BANK_ADDR_MAP 0x80
54 #define DRAM_TIMING_LOW 0x88
55 #define DTL_TCL_SHIFT 0
56 #define DTL_TCL_MASK 0x7
60 #define DTL_TRC_SHIFT 4
61 #define DTL_TRC_MASK 0xf
62 #define DTL_TRC_BASE 7
64 #define DTL_TRC_MAX 22
65 #define DTL_TRFC_SHIFT 8
66 #define DTL_TRFC_MASK 0xf
67 #define DTL_TRFC_BASE 9
68 #define DTL_TRFC_MIN 9
69 #define DTL_TRFC_MAX 24
70 #define DTL_TRCD_SHIFT 12
71 #define DTL_TRCD_MASK 0x7
72 #define DTL_TRCD_BASE 0
73 #define DTL_TRCD_MIN 2
74 #define DTL_TRCD_MAX 6
75 #define DTL_TRRD_SHIFT 16
76 #define DTL_TRRD_MASK 0x7
77 #define DTL_TRRD_BASE 0
78 #define DTL_TRRD_MIN 2
79 #define DTL_TRRD_MAX 4
80 #define DTL_TRAS_SHIFT 20
81 #define DTL_TRAS_MASK 0xf
82 #define DTL_TRAS_BASE 0
83 #define DTL_TRAS_MIN 5
84 #define DTL_TRAS_MAX 15
85 #define DTL_TRP_SHIFT 24
86 #define DTL_TRP_MASK 0x7
87 #define DTL_TRP_BASE 0
90 #define DTL_TWR_SHIFT 28
91 #define DTL_TWR_MASK 0x1
92 #define DTL_TWR_BASE 2
95 #define DRAM_TIMING_HIGH 0x8c
96 #define DTH_TWTR_SHIFT 0
97 #define DTH_TWTR_MASK 0x1
98 #define DTH_TWTR_BASE 1
99 #define DTH_TWTR_MIN 1
100 #define DTH_TWTR_MAX 2
101 #define DTH_TRWT_SHIFT 4
102 #define DTH_TRWT_MASK 0x7
103 #define DTH_TRWT_BASE 1
104 #define DTH_TRWT_MIN 1
105 #define DTH_TRWT_MAX 6
106 #define DTH_TREF_SHIFT 8
107 #define DTH_TREF_MASK 0x1f
108 #define DTH_TREF_100MHZ_4K 0x00
109 #define DTH_TREF_133MHZ_4K 0x01
110 #define DTH_TREF_166MHZ_4K 0x02
111 #define DTH_TREF_200MHZ_4K 0x03
112 #define DTH_TREF_100MHZ_8K 0x08
113 #define DTH_TREF_133MHZ_8K 0x09
114 #define DTH_TREF_166MHZ_8K 0x0A
115 #define DTH_TREF_200MHZ_8K 0x0B
116 #define DTH_TWCL_SHIFT 20
117 #define DTH_TWCL_MASK 0x7
118 #define DTH_TWCL_BASE 1
119 #define DTH_TWCL_MIN 1
120 #define DTH_TWCL_MAX 2
121 #define DRAM_CONFIG_LOW 0x90
122 #define DCL_DLL_Disable (1<<0)
123 #define DCL_D_DRV (1<<1)
124 #define DCL_QFC_EN (1<<2)
125 #define DCL_DisDqsHys (1<<3)
126 #define DCL_DramInit (1<<8)
127 #define DCL_DramEnable (1<<10)
128 #define DCL_MemClrStatus (1<<11)
129 #define DCL_ESR (1<<12)
130 #define DCL_SRS (1<<13)
131 #define DCL_128BitEn (1<<16)
132 #define DCL_DimmEccEn (1<<17)
133 #define DCL_UnBufDimm (1<<18)
134 #define DCL_32ByteEn (1<<19)
135 #define DCL_x4DIMM_SHIFT 20
136 #define DCL_DisInRcvrs (1<<24)
137 #define DCL_BypMax_SHIFT 25
138 #define DCL_En2T (1<<28)
139 #define DRAM_CONFIG_HIGH 0x94
140 #define DCH_ASYNC_LAT_SHIFT 0
141 #define DCH_ASYNC_LAT_MASK 0xf
142 #define DCH_ASYNC_LAT_BASE 0
143 #define DCH_ASYNC_LAT_MIN 0
144 #define DCH_ASYNC_LAT_MAX 15
145 #define DCH_RDPREAMBLE_SHIFT 8
146 #define DCH_RDPREAMBLE_MASK 0xf
147 #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */
148 #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */
149 #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */
150 #define DCH_IDLE_LIMIT_SHIFT 16
151 #define DCH_IDLE_LIMIT_MASK 0x7
152 #define DCH_IDLE_LIMIT_0 0
153 #define DCH_IDLE_LIMIT_4 1
154 #define DCH_IDLE_LIMIT_8 2
155 #define DCH_IDLE_LIMIT_16 3
156 #define DCH_IDLE_LIMIT_32 4
157 #define DCH_IDLE_LIMIT_64 5
158 #define DCH_IDLE_LIMIT_128 6
159 #define DCH_IDLE_LIMIT_256 7
160 #define DCH_DYN_IDLE_CTR_EN (1 << 19)
161 #define DCH_MEMCLK_SHIFT 20
162 #define DCH_MEMCLK_MASK 0x7
163 #define DCH_MEMCLK_100MHZ 0
164 #define DCH_MEMCLK_133MHZ 2
165 #define DCH_MEMCLK_166MHZ 5
166 #define DCH_MEMCLK_200MHZ 7
167 #define DCH_MEMCLK_VALID (1 << 25)
168 #define DCH_MEMCLK_EN0 (1 << 26)
169 #define DCH_MEMCLK_EN1 (1 << 27)
170 #define DCH_MEMCLK_EN2 (1 << 28)
171 #define DCH_MEMCLK_EN3 (1 << 29)
174 #define MCA_NB_CONFIG 0x44
175 #define MNC_ECC_EN (1 << 22)
176 #define MNC_CHIPKILL_EN (1 << 23)
177 #define SCRUB_CONTROL 0x58
181 #define SCRUB_160ns 3
182 #define SCRUB_320ns 4
183 #define SCRUB_640ns 5
184 #define SCRUB_1_28us 6
185 #define SCRUB_2_56us 7
186 #define SCRUB_5_12us 8
187 #define SCRUB_10_2us 9
188 #define SCRUB_20_5us 10
189 #define SCRUB_41_0us 11
190 #define SCRUB_81_9us 12
191 #define SCRUB_163_8us 13
192 #define SCRUB_327_7us 14
193 #define SCRUB_655_4us 15
194 #define SCRUB_1_31ms 16
195 #define SCRUB_2_62ms 17
196 #define SCRUB_5_24ms 18
197 #define SCRUB_10_49ms 19
198 #define SCRUB_20_97ms 20
199 #define SCRUB_42ms 21
200 #define SCRUB_84ms 22
201 #define SC_DRAM_SCRUB_RATE_SHFIT 0
202 #define SC_DRAM_SCRUB_RATE_MASK 0x1f
203 #define SC_L2_SCRUB_RATE_SHIFT 8
204 #define SC_L2_SCRUB_RATE_MASK 0x1f
205 #define SC_L1D_SCRUB_RATE_SHIFT 16
206 #define SC_L1D_SCRUB_RATE_MASK 0x1f
207 #define SCRUB_ADDR_LOW 0x5C
208 #define SCRUB_ADDR_HIGH 0x60
209 #define NORTHBRIDGE_CAP 0xE8
210 #define NBCAP_128Bit (1 << 0)
211 #define NBCAP_MP (1 << 1)
212 #define NBCAP_BIG_MP (1 << 2)
213 #define NBCAP_ECC (1 << 3)
214 #define NBCAP_CHIPKILL_ECC (1 << 4)
215 #define NBCAP_MEMCLK_SHIFT 5
216 #define NBCAP_MEMCLK_MASK 3
217 #define NBCAP_MEMCLK_100MHZ 3
218 #define NBCAP_MEMCLK_133MHZ 2
219 #define NBCAP_MEMCLK_166MHZ 1
220 #define NBCAP_MEMCLK_200MHZ 0
221 #define NBCAP_MEMCTRL (1 << 8)
224 #define LinkConnected (1 << 0)
225 #define InitComplete (1 << 1)
226 #define NonCoherent (1 << 2)
227 #define ConnectionPending (1 << 4)