2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 /*----------------------------------------------------------------------------
22 * TYPEDEFS, DEFINITIONS AND MACROS
24 *----------------------------------------------------------------------------
27 /* Single CPU system? */
28 #if (CONFIG_MAX_PHYSICAL_CPUS == 1)
29 #define HT_BUILD_NC_ONLY 1
32 /* Debugging Options */
34 //#define AMD_DEBUG_ERROR_STOP 1
36 /*----------------------------------------------------------------------------
39 *----------------------------------------------------------------------------
43 #define FILECODE 0xFF01
48 /* include the main HT source file */
52 /*----------------------------------------------------------------------------
55 *----------------------------------------------------------------------------
58 /* FIXME: Find a better place for these pre-ram functions. */
59 #define NODE_HT(x) NODE_PCI(x,0)
60 #define NODE_MP(x) NODE_PCI(x,1)
61 #define NODE_MC(x) NODE_PCI(x,3)
62 #define NODE_LC(x) NODE_PCI(x,4)
63 static u32 get_nodes(void)
68 dev = PCI_DEV(CBB, CDB, 0);
69 nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) ;
70 #if CONFIG_MAX_PHYSICAL_CPUS > 8
71 nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3);
78 static void enable_apic_ext_id(u32 node)
81 val = pci_read_config32(NODE_HT(node), 0x68);
82 val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
83 pci_write_config32(NODE_HT(node), 0x68, val);
87 static void setup_link_trans_cntrl()
89 /* FIXME: Not sure that this belongs here but it is HT related */
91 val = pci_read_config32(NODE_HT(0), 0x68);
92 val |= 0x00206800; // DSNpReqLimit, LimitCldtCfg, BufRefPri, RespPassPW per BKDG;
93 pci_write_config32(NODE_HT(0), 0x68, val);
100 * void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0)
102 * Needs to be fixed to output the debug structures.
105 void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0)
107 printk_debug("AMD_CB_EventNotify()\n");
108 printk_debug("event class: %02x event: %04x\n", evtClass, event);
113 * void getAmdTopolist(u8 ***p)
115 * point to the stock topo list array
118 void getAmdTopolist(u8 ***p)
120 *p = (u8 **)amd_topo_list;
125 * void amd_ht_init(struct sys_info *sysinfo)
127 * AMD HT init LinuxBIOS wrapper
130 void amd_ht_init(struct sys_info *sysinfo)
132 AMD_HTBLOCK ht_wrapper = {
133 NULL, // u8 **topolist;
134 0, // u8 AutoBusStart;
135 32, // u8 AutoBusMax;
136 6, // u8 AutoBusIncrement;
137 NULL, // BOOL (*AMD_CB_IgnoreLink)();
138 NULL, // BOOL (*AMD_CB_OverrideBusNumbers)();
139 NULL, // BOOL (*AMD_CB_ManualBUIDSwapList)();
140 NULL, // void (*AMD_CB_DeviceCapOverride)();
141 NULL, // void (*AMD_CB_Cpu2CpuPCBLimits)();
142 NULL, // void (*AMD_CB_IOPCBLimits)();
143 NULL, // BOOL (*AMD_CB_SkipRegang)();
144 NULL, // BOOL (*AMD_CB_CustomizeTrafficDistribution)();
145 NULL, // BOOL (*AMD_CB_CustomizeBuffers)();
146 NULL, // void (*AMD_CB_OverrideDevicePort)();
147 NULL, // void (*AMD_CB_OverrideCpuPort)();
148 AMD_CB_EventNotify // void (*AMD_CB_EventNotify) ();
151 printk_debug("Enter amd_ht_init()\n");
152 amdHtInitialize(&ht_wrapper);
153 printk_debug("Exit amd_ht_init()\n");