src/northbridge/amd/amdfam10/raminit_amdmct.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 static  void print_tx(const char *strval, u32 val)
  21 {
  22 #if CONFIG_DEBUG_RAM_SETUP
  23         printk(BIOS_DEBUG, "%s%08x\n", strval, val);
  24 #endif
  25 }
  26
  27 static  void print_t(const char *strval)
  28 {
  29 #if CONFIG_DEBUG_RAM_SETUP
  30         printk(BIOS_DEBUG, "%s", strval);
  31 #endif
  32 }
  33
  34 #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
  35 #include "amdfam10.h"
  36 #include "../amdmct/wrappers/mcti.h"
  37 #include "../amdmct/amddefs.h"
  38 #include "../amdmct/mct_ddr3/mwlc_d.h"
  39 #include "../amdmct/mct_ddr3/mct_d.h"
  40 #include "../amdmct/mct_ddr3/mct_d_gcc.h"
  41
  42 #include "../amdmct/wrappers/mcti_d.c"
  43 #include "../amdmct/mct_ddr3/mct_d.c"
  44
  45 #include "../amdmct/mct_ddr3/mctmtr_d.c"
  46 #include "../amdmct/mct_ddr3/mctcsi_d.c"
  47 #include "../amdmct/mct_ddr3/mctecc_d.c"
  48 #include "../amdmct/mct_ddr3/mctdqs_d.c"
  49 #include "../amdmct/mct_ddr3/mctsrc.c"
  50 #include "../amdmct/mct_ddr3/mctsdi.c"
  51 #include "../amdmct/mct_ddr3/mctproc.c"
  52 #include "../amdmct/mct_ddr3/mctprob.c"
  53 #include "../amdmct/mct_ddr3/mcthwl.c"
  54 #include "../amdmct/mct_ddr3/mctwl.c"
  55 #include "../amdmct/mct_ddr3/mport_d.c"
  56 #include "../amdmct/mct_ddr3/mutilc_d.c"
  57 #include "../amdmct/mct_ddr3/modtrdim.c"
  58 #include "../amdmct/mct_ddr3/mhwlc_d.c"
  59 #include "../amdmct/mct_ddr3/mctrci.c"
  60 #include "../amdmct/mct_ddr3/mctsrc1p.c"
  61 #include "../amdmct/mct_ddr3/mcttmrl.c"
  62 #include "../amdmct/mct_ddr3/mcthdi.c"
  63 #include "../amdmct/mct_ddr3/mctndi_d.c"
  64 #include "../amdmct/mct_ddr3/mctchi_d.c"
  65
  66 #if CONFIG_CPU_SOCKET_TYPE == 0x10
  67 //TODO: S1G1?
  68 #elif CONFIG_CPU_SOCKET_TYPE == 0x11
  69 //AM3
  70 #include "../amdmct/mct_ddr3/mctardk5.c"
  71 #elif CONFIG_CPU_SOCKET_TYPE == 0x12
  72 //F (1207), Fr2, G (1207)
  73 #include "../amdmct/mct_ddr3/mctardk6.c"
  74 #elif CONFIG_CPU_SOCKET_TYPE == 0x13
  75 //ASB2
  76 #include "../amdmct/mct_ddr3/mctardk5.c"
  77 #endif
  78
  79 #else  /* DDR2 */
  80
  81 #include "amdfam10.h"
  82 #include "../amdmct/wrappers/mcti.h"
  83 #include "../amdmct/amddefs.h"
  84 #include "../amdmct/mct/mct_d.h"
  85 #include "../amdmct/mct/mct_d_gcc.h"
  86
  87 #include "../amdmct/wrappers/mcti_d.c"
  88 #include "../amdmct/mct/mct_d.c"
  89
  90
  91 #include "../amdmct/mct/mctmtr_d.c"
  92 #include "../amdmct/mct/mctcsi_d.c"
  93 #include "../amdmct/mct/mctecc_d.c"
  94 #include "../amdmct/mct/mctpro_d.c"
  95 #include "../amdmct/mct/mctdqs_d.c"
  96 #include "../amdmct/mct/mctsrc.c"
  97 #include "../amdmct/mct/mctsrc1p.c"
  98 #include "../amdmct/mct/mcttmrl.c"
  99 #include "../amdmct/mct/mcthdi.c"
 100 #include "../amdmct/mct/mctndi_d.c"
 101 #include "../amdmct/mct/mctchi_d.c"
 102
 103 #if CONFIG_CPU_SOCKET_TYPE == 0x10
 104 //L1
 105 #include "../amdmct/mct/mctardk3.c"
 106 #elif CONFIG_CPU_SOCKET_TYPE == 0x11
 107 //AM2
 108 #include "../amdmct/mct/mctardk4.c"
 109 //#elif SYSTEM_TYPE == MOBILE
 110 //s1g1
 111 //#include "../amdmct/mct/mctardk5.c"
 112 #endif
 113
 114 #endif  /* DDR2 */
 115
 116 int mctRead_SPD(u32 smaddr, u32 reg)
 117 {
 118         return spd_read_byte(smaddr, reg);
 119 }
 120
 121
 122 void mctSMBhub_Init(u32 node)
 123 {
 124         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 125         struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
 126         activate_spd_rom(ctrl);
 127 }
 128
 129
 130 void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
 131 {
 132         int j;
 133         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 134         struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
 135
 136         for(j=0;j<DIMM_SOCKETS;j++) {
 137                 pDCTstat->DIMMAddr[j*2] = ctrl->spd_addr[j] & 0xff;
 138                 pDCTstat->DIMMAddr[j*2+1] = ctrl->spd_addr[DIMM_SOCKETS + j] & 0xff;
 139         }
 140
 141 }
 142
 143
 144 u32 mctGetLogicalCPUID(u32 Node)
 145 {
 146         /* FIXME: Move this to a more generic place. Maybe to the CPU code */
 147         /* Converts the CPUID to a logical ID MASK that is used to check
 148          CPU version support versions */
 149         u32 dev;
 150         u32 val, valx;
 151         u32 family, model, stepping;
 152         u32 ret;
 153
 154         if (Node == 0xFF) { /* current node */
 155                 val = cpuid_eax(0x80000001);
 156         } else {
 157                 dev = PA_NBMISC(Node);
 158                 val = Get_NB32(dev, 0xfc);
 159         }
 160
 161         family = ((val >> 8) & 0x0f) + ((val >> 20) & 0xff);
 162         model = ((val >> 4) & 0x0f) | ((val >> (16-4)) & 0xf0);
 163         stepping = val & 0x0f;
 164
 165         valx = (family << 12) | (model << 4) | (stepping);
 166
 167         switch (valx) {
 168         case 0x10000:
 169                 ret = AMD_DR_A0A;
 170                 break;
 171         case 0x10001:
 172                 ret = AMD_DR_A1B;
 173                 break;
 174         case 0x10002:
 175                 ret = AMD_DR_A2;
 176                 break;
 177         case 0x10020:
 178                 ret = AMD_DR_B0;
 179                 break;
 180         case 0x10021:
 181                 ret = AMD_DR_B1;
 182                 break;
 183         case 0x10022:
 184                 ret = AMD_DR_B2;
 185                 break;
 186         case 0x10023:
 187                 ret = AMD_DR_B3;
 188                 break;
 189         case 0x10042:
 190                 ret = AMD_RB_C2;
 191                 break;
 192         case 0x10043:
 193                 ret = AMD_RB_C3;
 194                 break;
 195         case 0x10062:
 196                 ret = AMD_DA_C2;
 197                 break;
 198         case 0x10063:
 199                 ret = AMD_DA_C3;
 200                 break;
 201         case 0x10080:
 202                 ret = AMD_HY_D0;
 203                 break;
 204         default:
 205                 /* FIXME: mabe we should die() here. */
 206                 print_err("FIXME! CPU Version unknown or not supported! \n");
 207                 ret = 0;
 208         }
 209
 210         return ret;
 211 }
 212
 213
 214 static void raminit_amdmct(struct sys_info *sysinfo)
 215 {
 216         struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat);
 217         struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA;
 218
 219         print_debug("raminit_amdmct begin:\n");
 220
 221         mctAutoInitMCT_D(pMCTstat, pDCTstatA);
 222
 223         print_debug("raminit_amdmct end:\n");
 224 }