src/northbridge/amd/amdfam10/raminit_amdmct.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 #if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */
  22 static  void print_tx(const char *strval, u32 val)
  23 {
  24 #if CONFIG_DEBUG_RAM_SETUP
  25         printk(BIOS_DEBUG, "%s%08x\n", strval, val);
  26 #endif
  27 }
  28 #endif
  29
  30 static  void print_t(const char *strval)
  31 {
  32 #if CONFIG_DEBUG_RAM_SETUP
  33         printk(BIOS_DEBUG, "%s", strval);
  34 #endif
  35 }
  36
  37 #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
  38 #include "amdfam10.h"
  39 #include "../amdmct/wrappers/mcti.h"
  40 #include "../amdmct/amddefs.h"
  41 #include "../amdmct/mct_ddr3/mwlc_d.h"
  42 #include "../amdmct/mct_ddr3/mct_d.h"
  43 #include "../amdmct/mct_ddr3/mct_d_gcc.h"
  44
  45 #include "../amdmct/wrappers/mcti_d.c"
  46 #include "../amdmct/mct_ddr3/mct_d.c"
  47
  48 #include "../amdmct/mct_ddr3/mctmtr_d.c"
  49 #include "../amdmct/mct_ddr3/mctcsi_d.c"
  50 #include "../amdmct/mct_ddr3/mctecc_d.c"
  51 #include "../amdmct/mct_ddr3/mctdqs_d.c"
  52 #include "../amdmct/mct_ddr3/mctsrc.c"
  53 #include "../amdmct/mct_ddr3/mctsdi.c"
  54 #include "../amdmct/mct_ddr3/mctproc.c"
  55 #include "../amdmct/mct_ddr3/mctprob.c"
  56 #include "../amdmct/mct_ddr3/mcthwl.c"
  57 #include "../amdmct/mct_ddr3/mctwl.c"
  58 #include "../amdmct/mct_ddr3/mport_d.c"
  59 #include "../amdmct/mct_ddr3/mutilc_d.c"
  60 #include "../amdmct/mct_ddr3/modtrdim.c"
  61 #include "../amdmct/mct_ddr3/mhwlc_d.c"
  62 #include "../amdmct/mct_ddr3/mctrci.c"
  63 #include "../amdmct/mct_ddr3/mctsrc1p.c"
  64 #include "../amdmct/mct_ddr3/mcttmrl.c"
  65 #include "../amdmct/mct_ddr3/mcthdi.c"
  66 #include "../amdmct/mct_ddr3/mctndi_d.c"
  67 #include "../amdmct/mct_ddr3/mctchi_d.c"
  68
  69 #if CONFIG_CPU_SOCKET_TYPE == 0x10
  70 //TODO: S1G1?
  71 #elif CONFIG_CPU_SOCKET_TYPE == 0x11
  72 //AM3
  73 #include "../amdmct/mct_ddr3/mctardk5.c"
  74 #elif CONFIG_CPU_SOCKET_TYPE == 0x12
  75 //F (1207), Fr2, G (1207)
  76 #include "../amdmct/mct_ddr3/mctardk6.c"
  77 #elif CONFIG_CPU_SOCKET_TYPE == 0x13
  78 //ASB2
  79 #include "../amdmct/mct_ddr3/mctardk5.c"
  80 #endif
  81
  82 #else  /* DDR2 */
  83
  84 #include "amdfam10.h"
  85 #include "../amdmct/wrappers/mcti.h"
  86 #include "../amdmct/amddefs.h"
  87 #include "../amdmct/mct/mct_d.h"
  88 #include "../amdmct/mct/mct_d_gcc.h"
  89
  90 #include "../amdmct/wrappers/mcti_d.c"
  91 #include "../amdmct/mct/mct_d.c"
  92
  93
  94 #include "../amdmct/mct/mctmtr_d.c"
  95 #include "../amdmct/mct/mctcsi_d.c"
  96 #include "../amdmct/mct/mctecc_d.c"
  97 #include "../amdmct/mct/mctpro_d.c"
  98 #include "../amdmct/mct/mctdqs_d.c"
  99 #include "../amdmct/mct/mctsrc.c"
 100 #include "../amdmct/mct/mctsrc1p.c"
 101 #include "../amdmct/mct/mcttmrl.c"
 102 #include "../amdmct/mct/mcthdi.c"
 103 #include "../amdmct/mct/mctndi_d.c"
 104 #include "../amdmct/mct/mctchi_d.c"
 105
 106 #if CONFIG_CPU_SOCKET_TYPE == 0x10
 107 //L1
 108 #include "../amdmct/mct/mctardk3.c"
 109 #elif CONFIG_CPU_SOCKET_TYPE == 0x11
 110 //AM2
 111 #include "../amdmct/mct/mctardk4.c"
 112 //#elif SYSTEM_TYPE == MOBILE
 113 //s1g1
 114 //#include "../amdmct/mct/mctardk5.c"
 115 #endif
 116
 117 #endif  /* DDR2 */
 118
 119 int mctRead_SPD(u32 smaddr, u32 reg)
 120 {
 121         return spd_read_byte(smaddr, reg);
 122 }
 123
 124
 125 void mctSMBhub_Init(u32 node)
 126 {
 127         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 128         struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
 129         activate_spd_rom(ctrl);
 130 }
 131
 132
 133 void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
 134 {
 135         int j;
 136         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 137         struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
 138
 139         for(j=0;j<DIMM_SOCKETS;j++) {
 140                 pDCTstat->DIMMAddr[j*2] = ctrl->spd_addr[j] & 0xff;
 141                 pDCTstat->DIMMAddr[j*2+1] = ctrl->spd_addr[DIMM_SOCKETS + j] & 0xff;
 142         }
 143
 144 }
 145
 146
 147 u32 mctGetLogicalCPUID(u32 Node)
 148 {
 149         /* FIXME: Move this to a more generic place. Maybe to the CPU code */
 150         /* Converts the CPUID to a logical ID MASK that is used to check
 151          CPU version support versions */
 152         u32 dev;
 153         u32 val, valx;
 154         u32 family, model, stepping;
 155         u32 ret;
 156
 157         if (Node == 0xFF) { /* current node */
 158                 val = cpuid_eax(0x80000001);
 159         } else {
 160                 dev = PA_NBMISC(Node);
 161                 val = Get_NB32(dev, 0xfc);
 162         }
 163
 164         family = ((val >> 8) & 0x0f) + ((val >> 20) & 0xff);
 165         model = ((val >> 4) & 0x0f) | ((val >> (16-4)) & 0xf0);
 166         stepping = val & 0x0f;
 167
 168         valx = (family << 12) | (model << 4) | (stepping);
 169
 170         switch (valx) {
 171         case 0x10000:
 172                 ret = AMD_DR_A0A;
 173                 break;
 174         case 0x10001:
 175                 ret = AMD_DR_A1B;
 176                 break;
 177         case 0x10002:
 178                 ret = AMD_DR_A2;
 179                 break;
 180         case 0x10020:
 181                 ret = AMD_DR_B0;
 182                 break;
 183         case 0x10021:
 184                 ret = AMD_DR_B1;
 185                 break;
 186         case 0x10022:
 187                 ret = AMD_DR_B2;
 188                 break;
 189         case 0x10023:
 190                 ret = AMD_DR_B3;
 191                 break;
 192         case 0x10042:
 193                 ret = AMD_RB_C2;
 194                 break;
 195         case 0x10043:
 196                 ret = AMD_RB_C3;
 197                 break;
 198         case 0x10062:
 199                 ret = AMD_DA_C2;
 200                 break;
 201         case 0x10063:
 202                 ret = AMD_DA_C3;
 203                 break;
 204         case 0x10080:
 205                 ret = AMD_HY_D0;
 206                 break;
 207         default:
 208                 /* FIXME: mabe we should die() here. */
 209                 print_err("FIXME! CPU Version unknown or not supported! \n");
 210                 ret = 0;
 211         }
 212
 213         return ret;
 214 }
 215
 216
 217 static void raminit_amdmct(struct sys_info *sysinfo)
 218 {
 219         struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat);
 220         struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA;
 221
 222         print_debug("raminit_amdmct begin:\n");
 223
 224         mctAutoInitMCT_D(pMCTstat, pDCTstatA);
 225
 226         print_debug("raminit_amdmct end:\n");
 227 }