src/northbridge/amd/amdfam10/raminit_amdmct.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 static  void print_tx(const char *strval, u32 val)
  21 {
  22 #if CONFIG_DEBUG_RAM_SETUP
  23         printk(BIOS_DEBUG, "%s%08x\n", strval, val);
  24 #endif
  25 }
  26
  27 static  void print_t(const char *strval)
  28 {
  29 #if CONFIG_DEBUG_RAM_SETUP
  30         printk(BIOS_DEBUG, "%s", strval);
  31 #endif
  32 }
  33 #include "amdfam10.h"
  34 #include "../amdmct/wrappers/mcti.h"
  35 #include "../amdmct/amddefs.h"
  36 #include "../amdmct/mct/mct_d.h"
  37 #include "../amdmct/mct/mct_d_gcc.h"
  38
  39 #include "../amdmct/wrappers/mcti_d.c"
  40 #include "../amdmct/mct/mct_d.c"
  41
  42
  43 #include "../amdmct/mct/mctmtr_d.c"
  44 #include "../amdmct/mct/mctcsi_d.c"
  45 #include "../amdmct/mct/mctecc_d.c"
  46 #include "../amdmct/mct/mctpro_d.c"
  47 #include "../amdmct/mct/mctdqs_d.c"
  48 #include "../amdmct/mct/mctsrc.c"
  49 #include "../amdmct/mct/mctsrc1p.c"
  50 #include "../amdmct/mct/mcttmrl.c"
  51 #include "../amdmct/mct/mcthdi.c"
  52 #include "../amdmct/mct/mctndi_d.c"
  53 #include "../amdmct/mct/mctchi_d.c"
  54
  55 #if CONFIG_CPU_SOCKET_TYPE == 0x10
  56 //L1
  57 #include "../amdmct/mct/mctardk3.c"
  58 #elif CONFIG_CPU_SOCKET_TYPE == 0x11
  59 //AM2
  60 #include "../amdmct/mct/mctardk4.c"
  61 //#elif SYSTEM_TYPE == MOBILE
  62 //s1g1
  63 //#include "../amdmct/mct/mctardk5.c"
  64 #endif
  65
  66 #include "../amdmct/mct/mct_fd.c"
  67
  68 int mctRead_SPD(u32 smaddr, u32 reg)
  69 {
  70         return spd_read_byte(smaddr, reg);
  71 }
  72
  73
  74 void mctSMBhub_Init(u32 node)
  75 {
  76         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  77         struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
  78         activate_spd_rom(ctrl);
  79 }
  80
  81
  82 void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
  83 {
  84         int j;
  85         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  86         struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
  87
  88         for(j=0;j<DIMM_SOCKETS;j++) {
  89                 pDCTstat->DIMMAddr[j*2] = ctrl->spd_addr[j] & 0xff;
  90                 pDCTstat->DIMMAddr[j*2+1] = ctrl->spd_addr[DIMM_SOCKETS + j] & 0xff;
  91         }
  92
  93 }
  94
  95
  96 u32 mctGetLogicalCPUID(u32 Node)
  97 {
  98         /* FIXME: Move this to a more generic place. Maybe to the CPU code */
  99         /* Converts the CPUID to a logical ID MASK that is used to check
 100          CPU version support versions */
 101         u32 dev;
 102         u32 val, valx;
 103         u32 family, model, stepping;
 104         u32 ret;
 105
 106         if (Node == 0xFF) { /* current node */
 107                 val = cpuid_eax(0x80000001);
 108         } else {
 109                 dev = PA_NBMISC(Node);
 110                 val = Get_NB32(dev, 0xfc);
 111         }
 112
 113         family = ((val >> 8) & 0x0f) + ((val >> 20) & 0xff);
 114         model = ((val >> 4) & 0x0f) | ((val >> (16-4)) & 0xf0);
 115         stepping = val & 0x0f;
 116
 117         valx = (family << 12) | (model << 4) | (stepping);
 118
 119         switch (valx) {
 120         case 0x10000:
 121                 ret = AMD_DR_A0A;
 122                 break;
 123         case 0x10001:
 124                 ret = AMD_DR_A1B;
 125                 break;
 126         case 0x10002:
 127                 ret = AMD_DR_A2;
 128                 break;
 129         case 0x10020:
 130                 ret = AMD_DR_B0;
 131                 break;
 132         case 0x10021:
 133                 ret = AMD_DR_B1;
 134                 break;
 135         case 0x10022:
 136                 ret = AMD_DR_B2;
 137                 break;
 138         case 0x10023:
 139                 ret = AMD_DR_B3;
 140                 break;
 141         case 0x10042:
 142                 ret = AMD_RB_C2;
 143                 break;
 144         case 0x10062:
 145                 ret = AMD_DA_C2;
 146                 break;
 147         case 0x10080:
 148                 ret = AMD_HY_D0;
 149                 break;
 150         default:
 151                 /* FIXME: mabe we should die() here. */
 152                 print_err("FIXME! CPU Version unknown or not supported! \n");
 153                 ret = 0;
 154         }
 155
 156         return ret;
 157 }
 158
 159
 160 static void raminit_amdmct(struct sys_info *sysinfo)
 161 {
 162         struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat);
 163         struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA;
 164
 165         print_debug("raminit_amdmct begin:\n");
 166
 167         mctAutoInitMCT_D(pMCTstat, pDCTstatA);
 168
 169         print_debug("raminit_amdmct end:\n");
 170 }