src/northbridge/amd/amdfam10/early_ht.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 // For SB HT chain only
  21 // mmconf is not ready yet
  22 static  void set_bsp_node_CHtExtNodeCfgEn(void)
  23 {
  24 #if EXT_RT_TBL_SUPPORT == 1
  25         u32 dword;
  26         dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68);
  27         dword |= (1<<27) | (1<<25);
  28         /* CHtExtNodeCfgEn: coherent link extended node configuration enable,
  29            Nodes[31:0] will be 0xff:[31:0], Nodes[63:32] will be 0xfe:[31:0]
  30               ---- 32 nodes now only
  31            It can be used even nodes less than 8 nodes.
  32            We can have 8 more device on bus 0 in that case
  33          */
  34
  35         /* CHtExtAddrEn */
  36         pci_io_write_config32(PCI_DEV(0, 0x18, 0), 0x68, dword);
  37         // CPU on bus 0xff and 0xfe now. For now on we can use CBB and CDB.
  38 #endif
  39 }
  40
  41 static void enumerate_ht_chain(void)
  42 {
  43 #if HT_CHAIN_UNITID_BASE != 0
  44 /* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain),
  45    if so, don't need to go through the chain  */
  46
  47         /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
  48          * On most boards this just happens.  If a cpu has multiple
  49          * non Coherent links the appropriate bus registers for the
  50          * links needs to be programed to point at bus 0.
  51          */
  52         unsigned next_unitid, last_unitid = 0;
  53 #if HT_CHAIN_END_UNITID_BASE != 0x20
  54         // let't record the device of last ht device, So we can set the
  55         // Unitid to HT_CHAIN_END_UNITID_BASE
  56         unsigned real_last_unitid = 0;
  57         u8 real_last_pos = 0;
  58         int ht_dev_num = 0; // except host_bridge
  59         u8 end_used = 0;
  60 #endif
  61
  62         next_unitid = HT_CHAIN_UNITID_BASE;
  63         do {
  64                 u32 id;
  65                 u8 hdr_type, pos;
  66                 last_unitid = next_unitid;
  67
  68                 id = pci_io_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID);
  69                 /* If the chain is enumerated quit */
  70                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
  71                         (((id >> 16) & 0xffff) == 0xffff) ||
  72                         (((id >> 16) & 0xffff) == 0x0000))
  73                 {
  74                         break;
  75                 }
  76
  77                 hdr_type = pci_io_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
  78                 pos = 0;
  79                 hdr_type &= 0x7f;
  80
  81                 if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
  82                         (hdr_type == PCI_HEADER_TYPE_BRIDGE))
  83                 {
  84                         pos = pci_io_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
  85                 }
  86                 while(pos != 0) {
  87                         u8 cap;
  88                         cap = pci_io_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID);
  89                         if (cap == PCI_CAP_ID_HT) {
  90                                 u16 flags;
  91                                 /* Read and write and reread flags so the link
  92                                  * direction bit is valid.
  93                                  */
  94                                 flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
  95                                 pci_io_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags);
  96                                 flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
  97                                 if ((flags >> 13) == 0) {
  98                                         unsigned count;
  99                                         unsigned ctrl, ctrl_off;
 100                                         device_t devx;
 101
 102 #if HT_CHAIN_END_UNITID_BASE != 0x20
 103                                         if(next_unitid>=0x18) {
 104                                                 if(!end_used) {
 105                                                         next_unitid = HT_CHAIN_END_UNITID_BASE;
 106                                                         end_used = 1;
 107                                                 } else {
 108                                                         goto out;
 109                                                 }
 110                                         }
 111                                         real_last_unitid = next_unitid;
 112                                         real_last_pos = pos;
 113                                         ht_dev_num++ ;
 114 #endif
 115                 #if HT_CHAIN_END_UNITID_BASE == 0
 116                                         if (!next_unitid)
 117                                                 goto out;
 118                 #endif
 119                                         flags &= ~0x1f;
 120                                         flags |= next_unitid & 0x1f;
 121                                         count = (flags >> 5) & 0x1f;
 122                                         devx = PCI_DEV(0, next_unitid, 0);
 123                                         next_unitid += count;
 124
 125                                         pci_io_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags);
 126
 127                                         /* Test for end of chain */
 128                                         ctrl_off = ((flags >> 10) & 1)?
 129                                                 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
 130
 131                                         do {
 132                                                 ctrl = pci_read_config16(devx, pos + ctrl_off);
 133                                                 /* Is this the end of the hypertransport chain? */
 134                                                 if (ctrl & (1 << 6)) {
 135                                                         goto out;
 136                                                 }
 137
 138                                                 if (ctrl & ((1 << 4) | (1 << 8))) {
 139                                                         /*
 140                                                          * Either the link has failed, or we have
 141                                                          * a CRC error.
 142                                                          * Sometimes this can happen due to link
 143                                                          * retrain, so lets knock it down and see
 144                                                          * if its transient
 145                                                          */
 146                                                         ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
 147                                                         pci_write_config16(devx, pos + ctrl_off, ctrl);
 148                                                         ctrl = pci_read_config16(devx, pos + ctrl_off);
 149                                                         if (ctrl & ((1 << 4) | (1 << 8))) {
 150                                                                 // can not clear the error
 151                                                                 break;
 152                                                         }
 153                                                 }
 154                                         } while((ctrl & (1 << 5)) == 0);
 155
 156                                         break;
 157                                 }
 158                         }
 159                         pos = pci_io_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
 160                 }
 161         } while(last_unitid != next_unitid);
 162
 163 out:    ;
 164 #if HT_CHAIN_END_UNITID_BASE != 0x20
 165         if((ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used) {
 166                 u16 flags;
 167                 flags = pci_io_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
 168                 flags &= ~0x1f;
 169                 flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
 170                 pci_io_write_config16(PCI_DEV(0, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
 171         }
 172 #endif
 173
 174 #endif
 175 }