src/northbridge/amd/amdfam10/debug.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /*
  21  * Generic FAM10 debug code, used by mainboard specific romstage.c
  22  */
  23
  24 #include "amdfam10_pci.c"
  25
  26 static void udelay_tsc(u32 us);
  27
  28 static  void print_debug_addr(const char *str, void *val)
  29 {
  30 #if CACHE_AS_RAM_ADDRESS_DEBUG == 1
  31                 printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val);
  32 #endif
  33 }
  34
  35 static void print_debug_pci_dev(u32 dev)
  36 {
  37 #if CONFIG_PCI_BUS_SEGN_BITS==0
  38         printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
  39 #else
  40         printk(BIOS_DEBUG, "PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
  41 #endif
  42 }
  43
  44 static void print_pci_devices(void)
  45 {
  46         device_t dev;
  47         for(dev = PCI_DEV(0, 0, 0);
  48                 dev <= PCI_DEV(0xff, 0x1f, 0x7);
  49                 dev += PCI_DEV(0,0,1)) {
  50                 u32 id;
  51                 id = pci_read_config32(dev, PCI_VENDOR_ID);
  52                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
  53                         (((id >> 16) & 0xffff) == 0xffff) ||
  54                         (((id >> 16) & 0xffff) == 0x0000)) {
  55                         continue;
  56                 }
  57                 print_debug_pci_dev(dev);
  58                 printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
  59                 if(((dev>>12) & 0x07) == 0) {
  60                         u8 hdr_type;
  61                         hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
  62                         if((hdr_type & 0x80) != 0x80) {
  63                                 dev += PCI_DEV(0,0,7);
  64                         }
  65                 }
  66         }
  67 }
  68
  69 static void print_pci_devices_on_bus(u32 busn)
  70 {
  71         device_t dev;
  72         for(dev = PCI_DEV(busn, 0, 0);
  73                 dev <= PCI_DEV(busn, 0x1f, 0x7);
  74                 dev += PCI_DEV(0,0,1)) {
  75                 u32 id;
  76                 id = pci_read_config32(dev, PCI_VENDOR_ID);
  77                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
  78                    (((id >> 16) & 0xffff) == 0xffff) ||
  79                    (((id >> 16) & 0xffff) == 0x0000)) {
  80                         continue;
  81                 }
  82                 print_debug_pci_dev(dev);
  83                 printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
  84                 if(((dev>>12) & 0x07) == 0) {
  85                         u8 hdr_type;
  86                         hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
  87                         if((hdr_type & 0x80) != 0x80) {
  88                                  dev += PCI_DEV(0,0,7);
  89                         }
  90                 }
  91         }
  92 }
  93
  94
  95
  96 static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
  97 {
  98         int i;
  99         print_debug_pci_dev(dev);
 100         int j;
 101         int end = start_reg + size;
 102
 103         for(i = start_reg; i < end; i+=4) {
 104                 u32 val;
 105                 if ((i & 0x0f) == 0) {
 106                         printk(BIOS_DEBUG, "\n%04x:",i);
 107                 }
 108                 val = pci_read_config32(dev, i);
 109                 for(j=0;j<4;j++) {
 110                         printk(BIOS_DEBUG, " %02x", val & 0xff);
 111                         val >>= 8;
 112                 }
 113         }
 114         print_debug("\n");
 115 }
 116 static void dump_pci_device(u32 dev)
 117 {
 118         dump_pci_device_range(dev, 0, 4096);
 119 }
 120 static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index);
 121 static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
 122                                         u32 size)
 123 {
 124         int i;
 125         int end = start + size;
 126         print_debug_pci_dev(dev);
 127         print_debug(" -- index_reg="); print_debug_hex32(index_reg);
 128
 129         for(i = start; i < end; i++) {
 130                 u32 val;
 131                 int j;
 132                 printk(BIOS_DEBUG, "\n%02x:",i);
 133                 val = pci_read_config32_index_wait(dev, index_reg, i);
 134                 for(j=0;j<4;j++) {
 135                         printk(BIOS_DEBUG, " %02x", val & 0xff);
 136                         val >>= 8;
 137                 }
 138
 139         }
 140         print_debug("\n");
 141 }
 142 static void dump_pci_device_index_wait(u32 dev, u32 index_reg)
 143 {
 144         dump_pci_device_index_wait_range(dev, index_reg, 0, 0x54);
 145         dump_pci_device_index_wait_range(dev, index_reg, 0x100, 0x08); //DIMM1 when memclk > 400Hz
 146 //      dump_pci_device_index_wait_range(dev, index_reg, 0x200, 0x08); //DIMM2
 147 //      dump_pci_device_index_wait_range(dev, index_reg, 0x300, 0x08); //DIMM3
 148
 149 }
 150
 151 static void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length)
 152 {
 153         int i;
 154         print_debug_pci_dev(dev);
 155
 156         print_debug(" index reg: "); print_debug_hex16(index_reg); print_debug(" type: "); print_debug_hex8(type);
 157
 158         type<<=28;
 159
 160         for(i = 0; i < length; i++) {
 161                 u32 val;
 162                 if ((i & 0x0f) == 0) {
 163                         printk(BIOS_DEBUG, "\n%02x:",i);
 164                 }
 165                 val = pci_read_config32_index(dev, index_reg, i|type);
 166                 printk(BIOS_DEBUG, " %08x", val);
 167         }
 168         print_debug("\n");
 169 }
 170
 171
 172 static void dump_pci_devices(void)
 173 {
 174         device_t dev;
 175         for(dev = PCI_DEV(0, 0, 0);
 176                 dev <= PCI_DEV(0xff, 0x1f, 0x7);
 177                 dev += PCI_DEV(0,0,1)) {
 178                 u32 id;
 179                 id = pci_read_config32(dev, PCI_VENDOR_ID);
 180                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
 181                         (((id >> 16) & 0xffff) == 0xffff) ||
 182                         (((id >> 16) & 0xffff) == 0x0000)) {
 183                         continue;
 184                 }
 185                 dump_pci_device(dev);
 186
 187                 if(((dev>>12) & 0x07) == 0) {
 188                         u8 hdr_type;
 189                         hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
 190                         if((hdr_type & 0x80) != 0x80) {
 191                                 dev += PCI_DEV(0,0,7);
 192                         }
 193                 }
 194         }
 195 }
 196
 197
 198 static void dump_pci_devices_on_bus(u32 busn)
 199 {
 200         device_t dev;
 201         for(dev = PCI_DEV(busn, 0, 0);
 202                 dev <= PCI_DEV(busn, 0x1f, 0x7);
 203                 dev += PCI_DEV(0,0,1)) {
 204                 u32 id;
 205                 id = pci_read_config32(dev, PCI_VENDOR_ID);
 206                 if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
 207                    (((id >> 16) & 0xffff) == 0xffff) ||
 208                    (((id >> 16) & 0xffff) == 0x0000)) {
 209                         continue;
 210                 }
 211                 dump_pci_device(dev);
 212
 213                 if(((dev>>12) & 0x07) == 0) {
 214                         u8 hdr_type;
 215                         hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
 216                         if((hdr_type & 0x80) != 0x80) {
 217                                 dev += PCI_DEV(0,0,7);
 218                         }
 219                 }
 220         }
 221 }
 222
 223 #if CONFIG_DEBUG_SMBUS
 224
 225 static void dump_spd_registers(const struct mem_controller *ctrl)
 226 {
 227         int i;
 228         print_debug("\n");
 229         for(i = 0; i < DIMM_SOCKETS; i++) {
 230                 u32 device;
 231                 device = ctrl->spd_addr[i];
 232                 if (device) {
 233                         int j;
 234                         printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
 235                         for(j = 0; j < 128; j++) {
 236                                 int status;
 237                                 u8 byte;
 238                                 if ((j & 0xf) == 0) {
 239                                         printk(BIOS_DEBUG, "\n%02x: ", j);
 240                                 }
 241                                 status = smbus_read_byte(device, j);
 242                                 if (status < 0) {
 243                                         break;
 244                                 }
 245                                 byte = status & 0xff;
 246                                 printk(BIOS_DEBUG, "%02x ", byte);
 247                         }
 248                         print_debug("\n");
 249                 }
 250                 device = ctrl->spd_addr[i+DIMM_SOCKETS];
 251                 if (device) {
 252                         int j;
 253                         printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
 254                         for(j = 0; j < 128; j++) {
 255                                 int status;
 256                                 u8 byte;
 257                                 if ((j & 0xf) == 0) {
 258                                         printk(BIOS_DEBUG, "\n%02x: ", j);
 259                                 }
 260                                 status = smbus_read_byte(device, j);
 261                                 if (status < 0) {
 262                                         break;
 263                                 }
 264                                 byte = status & 0xff;
 265                                 printk(BIOS_DEBUG, "%02x ", byte);
 266                         }
 267                         print_debug("\n");
 268                 }
 269         }
 270 }
 271 static void dump_smbus_registers(void)
 272 {
 273         u32 device;
 274         print_debug("\n");
 275         for(device = 1; device < 0x80; device++) {
 276                 int j;
 277                 if( smbus_read_byte(device, 0) < 0 ) continue;
 278                 printk(BIOS_DEBUG, "smbus: %02x", device);
 279                 for(j = 0; j < 256; j++) {
 280                         int status;
 281                         u8 byte;
 282                         status = smbus_read_byte(device, j);
 283                         if (status < 0) {
 284                                 break;
 285                         }
 286                         if ((j & 0xf) == 0) {
 287                                 printk(BIOS_DEBUG, "\n%02x: ",j);
 288                         }
 289                         byte = status & 0xff;
 290                         printk(BIOS_DEBUG, "%02x ", byte);
 291                 }
 292                 print_debug("\n");
 293         }
 294 }
 295 #endif
 296 static void dump_io_resources(u32 port)
 297 {
 298
 299         int i;
 300         udelay_tsc(2000);
 301         printk(BIOS_DEBUG, "%04x:\n", port);
 302         for(i=0;i<256;i++) {
 303                 u8 val;
 304                 if ((i & 0x0f) == 0) {
 305                         printk(BIOS_DEBUG, "%02x:", i);
 306                 }
 307                 val = inb(port);
 308                 printk(BIOS_DEBUG, " %02x",val);
 309                 if ((i & 0x0f) == 0x0f) {
 310                         print_debug("\n");
 311                 }
 312                 port++;
 313         }
 314 }
 315
 316 static void dump_mem(u32 start, u32 end)
 317 {
 318         u32 i;
 319         print_debug("dump_mem:");
 320         for(i=start;i<end;i++) {
 321                 if((i & 0xf)==0) {
 322                         printk(BIOS_DEBUG, "\n%08x:", i);
 323                 }
 324                 printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
 325         }
 326         print_debug("\n");
 327 }