2 * This file is part of the coreboot project.
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4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
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6 * This program is free software; you can redistribute it and/or modify
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7 * it under the terms of the GNU General Public License as published by
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8 * the Free Software Foundation; version 2 of the License.
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10 * This program is distributed in the hope that it will be useful,
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 * GNU General Public License for more details.
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15 * You should have received a copy of the GNU General Public License
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16 * along with this program; if not, write to the Free Software
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17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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23 /* Definitions of various FAM10 registers */
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25 #define HT_TRANSACTION_CONTROL 0x68
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26 #define HTTC_DIS_RD_B_P (1 << 0)
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27 #define HTTC_DIS_RD_DW_P (1 << 1)
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28 #define HTTC_DIS_WR_B_P (1 << 2)
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29 #define HTTC_DIS_WR_DW_P (1 << 3)
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30 #define HTTC_DIS_MTS (1 << 4)
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31 #define HTTC_CPU1_EN (1 << 5)
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32 #define HTTC_CPU_REQ_PASS_PW (1 << 6)
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33 #define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
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34 #define HTTC_DIS_P_MEM_C (1 << 8)
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35 #define HTTC_DIS_RMT_MEM_C (1 << 9)
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36 #define HTTC_DIS_FILL_P (1 << 10)
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37 #define HTTC_RSP_PASS_PW (1 << 11)
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38 #define HTTC_BUF_REL_PRI_SHIFT 13
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39 #define HTTC_BUF_REL_PRI_MASK 3
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40 #define HTTC_BUF_REL_PRI_64 0
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41 #define HTTC_BUF_REL_PRI_16 1
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42 #define HTTC_BUF_REL_PRI_8 2
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43 #define HTTC_BUF_REL_PRI_2 3
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44 #define HTTC_LIMIT_CLDT_CFG (1 << 15)
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45 #define HTTC_LINT_EN (1 << 16)
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46 #define HTTC_APIC_EXT_BRD_CST (1 << 17)
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47 #define HTTC_APIC_EXT_ID (1 << 18)
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48 #define HTTC_APIC_EXT_SPUR (1 << 19)
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49 #define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
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50 #define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
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51 #define HTTC_DS_NP_REQ_LIMIT_MASK 3
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52 #define HTTC_DS_NP_REQ_LIMIT_NONE 0
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53 #define HTTC_DS_NP_REQ_LIMIT_1 1
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54 #define HTTC_DS_NP_REQ_LIMIT_4 2
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55 #define HTTC_DS_NP_REQ_LIMIT_8 3
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59 #define PCI_IO_BASE0 0xc0
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60 #define PCI_IO_BASE1 0xc8
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61 #define PCI_IO_BASE2 0xd0
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62 #define PCI_IO_BASE3 0xd8
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63 #define PCI_IO_BASE_VGA_EN (1 << 4)
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64 #define PCI_IO_BASE_NO_ISA (1 << 5)
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67 // 0x1xx is for DCT1
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68 #define DRAM_CSBASE 0x40
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69 #define DRAM_CSMASK 0x60
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70 #define DRAM_BANK_ADDR_MAP 0x80
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72 #define DRAM_CTRL 0x78
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73 #define DC_RdPtrInit_SHIFT 0
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74 #define DC_RdPrtInit_MASK 0xf
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75 #define DC_Twrrd3_2_SHIFT 8 /*DDR3 */
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76 #define DC_Twrrd3_2_MASK 3
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77 #define DC_Twrwr3_2_SHIFT 10 /*DDR3 */
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78 #define DC_Twrwr3_2_MASK 3
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79 #define DC_Trdrd3_2_SHIFT 12 /*DDR3 */
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80 #define DC_Trdrd3_2_MASK 3
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81 #define DC_AltVidC3MemClkTriEn (1<<16)
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82 #define DC_DqsRcvEnTrain (1<<18)
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83 #define DC_MaxRdLatency_SHIFT 22
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84 #define DC_MaxRdLatency_MASK 0x3ff
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86 #define DRAM_INIT 0x7c
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87 #define DI_MrsAddress_SHIFT 0
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88 #define DI_MrsAddress_MASK 0xffff
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89 #define DI_MrsBank_SHIFT 16
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90 #define DI_MrsBank_MASK 7
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91 #define DI_MrsChipSel_SHIFT 20
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92 #define DI_MrsChipSel_MASK 7
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93 #define DI_SendRchgAll (1<<24)
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94 #define DI_SendAutoRefresh (1<<25)
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95 #define DI_SendMrsCmd (1<<26)
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96 #define DI_DeassertMemRstX (1<<27)
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97 #define DI_AssertCke (1<<28)
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98 #define DI_SendZQCmd (1<<29) /*DDR3 */
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99 #define DI_EnMrsCmd (1<<30)
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100 #define DI_EnDramInit (1<<31)
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102 #define DRAM_MRS 0x84
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103 #define DM_BurstCtrl_SHIFT 0
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104 #define DM_BurstCtrl_MASK 3
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105 #define DM_DrvImpCtrl_SHIFT 2 /* DDR3 */
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106 #define DM_DrvImpCtrl_MASK 3
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107 #define DM_Twr_SHIFT 4 /* DDR3 */
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108 #define DM_Twr_MASK 7
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109 #define DM_Twr_BASE 4
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110 #define DM_Twr_MIN 5
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111 #define DM_Twr_MAX 12
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112 #define DM_DramTerm_SHIFT 7 /*DDR3 */
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113 #define DM_DramTerm_MASK 7
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114 #define DM_DramTermDyn_SHIFT 10 /* DDR3 */
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115 #define DM_DramTermDyn_MASK 3
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116 #define DM_Ooff (1<<13)
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117 #define DM_ASR (1<<18)
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118 #define DM_SRT (1<<19)
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119 #define DM_Tcwl_SHIFT 20
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120 #define DM_Tcwl_MASK 7
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121 #define DM_PchgPDModeSel (1<<23) /* DDR3 */
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122 #define DM_MPrLoc_SHIFT 24 /* DDR3 */
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123 #define DM_MPrLoc_MASK 3
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124 #define DM_MprEn (1<<26) /* DDR3 */
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126 #define DRAM_TIMING_LOW 0x88
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127 #define DTL_TCL_SHIFT 0
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128 #define DTL_TCL_MASK 0xf
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129 #define DTL_TCL_BASE 1 /* DDR3 =4 */
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130 #define DTL_TCL_MIN 3 /* DDR3 =4 */
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131 #define DTL_TCL_MAX 6 /* DDR3 =12 */
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132 #define DTL_TRCD_SHIFT 4
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133 #define DTL_TRCD_MASK 3 /* DDR3 =7 */
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134 #define DTL_TRCD_BASE 3 /* DDR3 =5 */
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135 #define DTL_TRCD_MIN 3 /* DDR3 =5 */
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136 #define DTL_TRCD_MAX 6 /* DDR3 =12 */
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137 #define DTL_TRP_SHIFT 8 /* DDR3 =7 */
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138 #define DTL_TRP_MASK 3 /* DDR3 =7 */
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139 #define DTL_TRP_BASE 3 /* DDR3 =5 */
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140 #define DTL_TRP_MIN 3 /* DDR3 =5 */
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141 #define DTL_TRP_MAX 6 /* DDR3 =12 */
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142 #define DTL_TRTP_SHIFT 11 /*DDR3 =10 */
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143 #define DTL_TRTP_MASK 1 /*DDR3 =3 */
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144 #define DTL_TRTP_BASE 2 /* DDR3 =4 */
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145 #define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/ /* DDR3 =4 for 32bytes or 64bytes */
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146 #define DTL_TRTP_MAX 3 /* 5 for 64 bytes */ /* DDR3 =7 for 32Bytes or 64bytes */
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147 #define DTL_TRAS_SHIFT 12
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148 #define DTL_TRAS_MASK 0xf
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149 #define DTL_TRAS_BASE 3 /* DDR3 =15 */
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150 #define DTL_TRAS_MIN 5 /* DDR3 =15 */
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151 #define DTL_TRAS_MAX 18 /*DDR3 =30 */
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152 #define DTL_TRC_SHIFT 16
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153 #define DTL_TRC_MASK 0xf /* DDR3 =0x1f */
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154 #define DTL_TRC_BASE 11
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155 #define DTL_TRC_MIN 11
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156 #define DTL_TRC_MAX 26 /* DDR3 =43 */
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157 #define DTL_TWR_SHIFT 20 /* only for DDR2, DDR3's is on DC */
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158 #define DTL_TWR_MASK 3
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159 #define DTL_TWR_BASE 3
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160 #define DTL_TWR_MIN 3
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161 #define DTL_TWR_MAX 6
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162 #define DTL_TRRD_SHIFT 22
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163 #define DTL_TRRD_MASK 3
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164 #define DTL_TRRD_BASE 2 /* DDR3 =4 */
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165 #define DTL_TRRD_MIN 2 /* DDR3 =4 */
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166 #define DTL_TRRD_MAX 5 /* DDR3 =7 */
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167 #define DTL_MemClkDis_SHIFT 24 /* Channel A */
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168 #define DTL_MemClkDis3 (1 << 26)
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169 #define DTL_MemClkDis2 (1 << 27)
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170 #define DTL_MemClkDis1 (1 << 28)
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171 #define DTL_MemClkDis0 (1 << 29)
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172 /* DTL_MemClkDis for m2 and s1g1 is different */
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174 #define DRAM_TIMING_HIGH 0x8c
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175 #define DTH_TRWTWB_SHIFT 0
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176 #define DTH_TRWTWB_MASK 3
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177 #define DTH_TRWTWB_BASE 3 /* DDR3 =4 */
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178 #define DTH_TRWTWB_MIN 3 /* DDR3 =5 */
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179 #define DTH_TRWTWB_MAX 10 /* DDR3 =11 */
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180 #define DTH_TRWTTO_SHIFT 4
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181 #define DTH_TRWTTO_MASK 7
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182 #define DTH_TRWTTO_BASE 2 /* DDR3 =3 */
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183 #define DTH_TRWTTO_MIN 2 /* DDR3 =3 */
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184 #define DTH_TRWTTO_MAX 9 /* DDR3 =10 */
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185 #define DTH_TWTR_SHIFT 8
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186 #define DTH_TWTR_MASK 3
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187 #define DTH_TWTR_BASE 0 /* DDR3 =4 */
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188 #define DTH_TWTR_MIN 1 /* DDR3 =4 */
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189 #define DTH_TWTR_MAX 3 /* DDR3 =7 */
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190 #define DTH_TWRRD_SHIFT 10
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191 #define DTH_TWRRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */
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192 #define DTH_TWRRD_BASE 0 /* DDR3 =0 */
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193 #define DTH_TWRRD_MIN 0 /* DDR3 =2 */
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194 #define DTH_TWRRD_MAX 3 /* DDR3 =12 */
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195 #define DTH_TWRWR_SHIFT 12
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196 #define DTH_TWRWR_MASK 3 /* For DDR3 3_2 is at 0x78 DC */
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197 #define DTH_TWRWR_BASE 1
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198 #define DTH_TWRWR_MIN 1 /* DDR3 =3 */
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199 #define DTH_TWRWR_MAX 3 /* DDR3 =12 */
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200 #define DTH_TRDRD_SHIFT 14
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201 #define DTH_TRDRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */
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202 #define DTH_TRDRD_BASE 2
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203 #define DTH_TRDRD_MIN 2
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204 #define DTH_TRDRD_MAX 5 /* DDR3 =10 */
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205 #define DTH_TREF_SHIFT 16
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206 #define DTH_TREF_MASK 3
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207 #define DTH_TREF_7_8_US 2
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208 #define DTH_TREF_3_9_US 3
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209 #define DTH_DisAutoRefresh (1<<18)
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210 #define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */
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211 #define DTH_TRFC_MASK 7
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212 #define DTH_TRFC_75_256M 0
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213 #define DTH_TRFC_105_512M 1
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214 #define DTH_TRFC_127_5_1G 2
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215 #define DTH_TRFC_195_2G 3
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216 #define DTH_TRFC_327_5_4G 4
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219 #define DTH_TRFC_90_512M 1
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220 #define DTH_TRFC_110_5_1G 2
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221 #define DTH_TRFC_160_2G 3
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222 #define DTH_TRFC_300_4G 4
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223 #define DTH_TRFC_UNDEFINED_8G 5
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225 #define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */
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226 #define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */
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227 #define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */
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229 #define DRAM_CONFIG_LOW 0x90
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230 #define DCL_InitDram (1<<0)
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231 #define DCL_ExitSelfRef (1<<1)
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232 #define DCL_PllLockTime_SHIFT 2
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233 #define DCL_PllLockTime_MASK 3
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234 #define DCL_PllLockTime_15US 0
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235 #define DCL_PllLockTime_6US 1
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236 #define DCL_DramTerm_SHIFT 4
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237 #define DCL_DramTerm_MASK 3
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238 #define DCL_DramTerm_No 0
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239 #define DCL_DramTerm_75_OH 1
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240 #define DCL_DramTerm_150_OH 2
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241 #define DCL_DramTerm_50_OH 3
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242 #define DCL_DisDqsBar (1<<6) /* only for DDR2 */
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243 #define DCL_DramDrvWeak (1<<7) /* only for DDR2 */
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244 #define DCL_ParEn (1<<8)
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245 #define DCL_SelfRefRateEn (1<<9) /* only for DDR2 */
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246 #define DCL_BurstLength32 (1<<10) /* only for DDR3 */
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247 #define DCL_Width128 (1<<11)
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248 #define DCL_X4Dimm_SHIFT 12
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249 #define DCL_X4Dimm_MASK 0xf
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250 #define DCL_UnBuffDimm (1<<16)
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251 #define DCL_EnPhyDqsRcvEnTr (1<<18)
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252 #define DCL_DimmEccEn (1<<19)
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253 #define DCL_DynPageCloseEn (1<<20)
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254 #define DCL_IdleCycInit_SHIFT 21
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255 #define DCL_IdleCycInit_MASK 3
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256 #define DCL_IdleCycInit_16CLK 0
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257 #define DCL_IdleCycInit_32CLK 1
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258 #define DCL_IdleCycInit_64CLK 2
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259 #define DCL_IdleCycInit_96CLK 3
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260 #define DCL_ForceAutoPchg (1<<23)
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262 #define DRAM_CONFIG_HIGH 0x94
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263 #define DCH_MemClkFreq_SHIFT 0
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264 #define DCH_MemClkFreq_MASK 7
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265 #define DCH_MemClkFreq_200MHz 0 /* DDR2 */
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266 #define DCH_MemClkFreq_266MHz 1 /* DDR2 */
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267 #define DCH_MemClkFreq_333MHz 2 /* DDR2 */
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268 #define DCH_MemClkFreq_400MHz 3 /* DDR2 and DDR 3*/
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269 #define DCH_MemClkFreq_533MHz 4 /* DDR 3 */
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270 #define DCH_MemClkFreq_667MHz 5 /* DDR 3 */
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271 #define DCH_MemClkFreq_800MHz 6 /* DDR 3 */
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272 #define DCH_MemClkFreqVal (1<<3)
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273 #define DCH_Ddr3Mode (1<<8)
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274 #define DCH_LegacyBiosMode (1<<9)
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275 #define DCH_ZqcsInterval_SHIFT 10
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276 #define DCH_ZqcsInterval_MASK 3
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277 #define DCH_ZqcsInterval_DIS 0
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278 #define DCH_ZqcsInterval_64MS 1
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279 #define DCH_ZqcsInterval_128MS 2
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280 #define DCH_ZqcsInterval_256MS 3
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281 #define DCH_RDqsEn (1<<12) /* only for DDR2 */
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282 #define DCH_DisSimulRdWr (1<<13)
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283 #define DCH_DisDramInterface (1<<14)
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284 #define DCH_PowerDownEn (1<<15)
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285 #define DCH_PowerDownMode_SHIFT 16
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286 #define DCH_PowerDownMode_MASK 1
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287 #define DCH_PowerDownMode_Channel_CKE 0
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288 #define DCH_PowerDownMode_ChipSelect_CKE 1
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289 #define DCH_FourRankSODimm (1<<17)
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290 #define DCH_FourRankRDimm (1<<18)
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291 #define DCH_SlowAccessMode (1<<20)
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292 #define DCH_BankSwizzleMode (1<<22)
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293 #define DCH_DcqBypassMax_SHIFT 24
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294 #define DCH_DcqBypassMax_MASK 0xf
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295 #define DCH_DcqBypassMax_BASE 0
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296 #define DCH_DcqBypassMax_MIN 0
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297 #define DCH_DcqBypassMax_MAX 15
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298 #define DCH_FourActWindow_SHIFT 28
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299 #define DCH_FourActWindow_MASK 0xf
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300 #define DCH_FourActWindow_BASE 7 /* DDR3 15 */
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301 #define DCH_FourActWindow_MIN 8 /* DDR3 16 */
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302 #define DCH_FourActWindow_MAX 20 /* DDR3 30 */
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305 // for 0x98 index and 0x9c data for DCT0
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306 // for 0x198 index and 0x19c data for DCT1
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307 // even at ganged mode, 0x198/0x19c will be used for channnel B
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309 #define DRAM_CTRL_ADDI_DATA_OFFSET 0x98
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310 #define DCAO_DctOffset_SHIFT 0
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311 #define DCAO_DctOffset_MASK 0x3fffffff
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312 #define DCAO_DctAccessWrite (1<<30)
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313 #define DCAO_DctAccessDone (1<<31)
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315 #define DRAM_CTRL_ADDI_DATA_PORT 0x9c
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317 #define DRAM_OUTPUT_DRV_COMP_CTRL 0x00
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318 #define DODCC_CkeDrvStren_SHIFT 0
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319 #define DODCC_CkeDrvStren_MASK 3
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320 #define DODCC_CkeDrvStren_1_0X 0
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321 #define DODCC_CkeDrvStren_1_25X 1
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322 #define DODCC_CkeDrvStren_1_5X 2
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323 #define DODCC_CkeDrvStren_2_0X 3
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324 #define DODCC_CsOdtDrvStren_SHIFT 4
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325 #define DODCC_CsOdtDrvStren_MASK 3
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326 #define DODCC_CsOdtDrvStren_1_0X 0
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327 #define DODCC_CsOdtDrvStren_1_25X 1
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328 #define DODCC_CsOdtDrvStren_1_5X 2
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329 #define DODCC_CsOdtDrvStren_2_0X 3
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330 #define DODCC_AddrCmdDrvStren_SHIFT 8
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331 #define DODCC_AddrCmdDrvStren_MASK 3
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332 #define DODCC_AddrCmdDrvStren_1_0X 0
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333 #define DODCC_AddrCmdDrvStren_1_25X 1
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334 #define DODCC_AddrCmdDrvStren_1_5X 2
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335 #define DODCC_AddrCmdDrvStren_2_0X 3
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336 #define DODCC_ClkDrvStren_SHIFT 12
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337 #define DODCC_ClkDrvStren_MASK 3
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338 #define DODCC_ClkDrvStren_0_75X 0
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339 #define DODCC_ClkDrvStren_1_0X 1
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340 #define DODCC_ClkDrvStren_1_25X 2
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341 #define DODCC_ClkDrvStren_1_5X 3
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342 #define DODCC_DataDrvStren_SHIFT 16
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343 #define DODCC_DataDrvStren_MASK 3
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344 #define DODCC_DataDrvStren_0_75X 0
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345 #define DODCC_DataDrvStren_1_0X 1
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346 #define DODCC_DataDrvStren_1_25X 2
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347 #define DODCC_DataDrvStren_1_5X 3
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348 #define DODCC_DqsDrvStren_SHIFT 20
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349 #define DODCC_DqsDrvStren_MASK 3
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350 #define DODCC_DqsDrvStren_0_75X 0
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351 #define DODCC_DqsDrvStren_1_0X 1
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352 #define DODCC_DqsDrvStren_1_25X 2
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353 #define DODCC_DqsDrvStren_1_5X 3
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354 #define DODCC_ProcOdt_SHIFT 28
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355 #define DODCC_ProcOdt_MASK 3
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356 #define DODCC_ProcOdt_300_OHMS 0
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357 #define DODCC_ProcOdt_150_OHMS 1
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358 #define DODCC_ProcOdt_75_OHMS 2
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361 #define DODCC_ProcOdt_240_OHMS 0
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362 #define DODCC_ProcOdt_120_OHMS 1
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363 #define DODCC_ProcOdt_60_OHMS 2
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367 for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of all DIMMs
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368 for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of DIMM0
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369 F2x[1,0]9C_x[102:101], [103], [106:105], [107] controll timing of DIMM1
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370 So Socket F with Four Logical DIMM will only support DDR2 800 ?
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372 /* there are index +100 ===> for DIMM1
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373 that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
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376 #define DRAM_WRITE_DATA_TIMING_CTRL_LOW 0x01
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377 #define DWDTC_WrDatFineDlyByte0_SHIFT 0
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378 #define DWDTC_WrDatFineDlyByte_MASK 0x1f
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379 #define DWDTC_WrDatFineDlyByte_BASE 0
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380 #define DWDTC_WrDatFineDlyByte_MIN 0
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381 #define DWDTC_WrDatFineDlyByte_MAX 31 // 1/64 MEMCLK
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382 #define DWDTC_WrDatGrossDlyByte0_SHIFT 5
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383 #define DWDTC_WrDatGrossDlyByte_MASK 0x3
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384 #define DWDTC_WrDatGrossDlyByte_NO_DELAY 0
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385 #define DWDTC_WrDatGrossDlyByte_0_5_ 1
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386 #define DWDTC_WrDatGrossDlyByte_1 2
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387 #define DWDTC_WrDatFineDlyByte1_SHIFT 8
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388 #define DWDTC_WrDatGrossDlyByte1_SHIFT 13
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389 #define DWDTC_WrDatFineDlyByte2_SHIFT 16
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390 #define DWDTC_WrDatGrossDlyByte2_SHIFT 21
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391 #define DWDTC_WrDatFineDlyByte3_SHIFT 24
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392 #define DWDTC_WrDatGrossDlyByte3_SHIFT 29
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394 #define DRAM_WRITE_DATA_TIMING_CTRL_HIGH 0x02
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395 #define DWDTC_WrDatFineDlyByte4_SHIFT 0
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396 #define DWDTC_WrDatGrossDlyByte4_SHIFT 5
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397 #define DWDTC_WrDatFineDlyByte5_SHIFT 8
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398 #define DWDTC_WrDatGrossDlyByte5_SHIFT 13
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399 #define DWDTC_WrDatFineDlyByte6_SHIFT 16
\r
400 #define DWDTC_WrDatGrossDlyByte6_SHIFT 21
\r
401 #define DWDTC_WrDatFineDlyByte7_SHIFT 24
\r
402 #define DWDTC_WrDatGrossDlyByte7_SHIFT 29
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404 #define DRAM_WRITE_ECC_TIMING_CTRL 0x03
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405 #define DWETC_WrChkFinDly_SHIFT 0
\r
406 #define DWETC_WrChkGrossDly_SHIFT 5
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408 #define DRAM_ADDR_CMD_TIMING_CTRL 0x04
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409 #define DACTC_CkeFineDelay_SHIFT 0
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410 #define DACTC_CkeFineDelay_MASK 0x1f
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411 #define DACTC_CkeFineDelay_BASE 0
\r
412 #define DACTC_CkeFineDelay_MIN 0
\r
413 #define DACTC_CkeFineDelay_MAX 31
\r
414 #define DACTC_CkeSetup (1<<5)
\r
415 #define DACTC_CsOdtFineDelay_SHIFT 8
\r
416 #define DACTC_CsOdtFineDelay_MASK 0x1f
\r
417 #define DACTC_CsOdtFineDelay_BASE 0
\r
418 #define DACTC_CsOdtFineDelay_MIN 0
\r
419 #define DACTC_CsOdtFineDelay_MAX 31
\r
420 #define DACTC_CsOdtSetup (1<<13)
\r
421 #define DACTC_AddrCmdFineDelay_SHIFT 16
\r
422 #define DACTC_AddrCmdFineDelay_MASK 0x1f
\r
423 #define DACTC_AddrCmdFineDelay_BASE 0
\r
424 #define DACTC_AddrCmdFineDelay_MIN 0
\r
425 #define DACTC_AddrCmdFineDelay_MAX 31
\r
426 #define DACTC_AddrCmdSetup (1<<21)
\r
428 #define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05
\r
429 #define DRDTC_RdDqsTimeByte0_SHIFT 0
\r
430 #define DRDTC_RdDqsTimeByte_MASK 0x3f
\r
431 #define DRDTC_RdDqsTimeByte_BASE 0
\r
432 #define DRDTC_RdDqsTimeByte_MIN 0
\r
433 #define DRDTC_RdDqsTimeByte_MAX 63 // 1/128 MEMCLK
\r
434 #define DRDTC_RdDqsTimeByte1_SHIFT 8
\r
435 #define DRDTC_RdDqsTimeByte2_SHIFT 16
\r
436 #define DRDTC_RdDqsTimeByte3_SHIFT 24
\r
438 #define DRAM_READ_DQS_TIMING_CTRL_HIGH 0x06
\r
439 #define DRDTC_RdDqsTimeByte4_SHIFT 0
\r
440 #define DRDTC_RdDqsTimeByte5_SHIFT 8
\r
441 #define DRDTC_RdDqsTimeByte6_SHIFT 16
\r
442 #define DRDTC_RdDqsTimeByte7_SHIFT 24
\r
444 #define DRAM_READ_DQS_ECC_TIMING_CTRL 0x07
\r
445 #define DRDETC_RdDqsTimeCheck_SHIFT 0
\r
447 #define DRAM_PHY_CTRL 0x08
\r
448 #define DPC_WrtLvTrEn (1<<0)
\r
449 #define DPC_WrtLvTrMode (1<<1)
\r
450 #define DPC_TrNibbleSel (1<<2)
\r
451 #define DPC_TrDimmSel_SHIFT 4
\r
452 #define DPC_TrDimmSel_MASK 3 /* 0-->dimm0, 1-->dimm1, 2--->dimm2, 3--->dimm3 */
\r
453 #define DPC_WrLvOdt_SHIFT 8
\r
454 #define DPC_WrLvOdt_MASK 0xf /* bit 0-->odt 0, ...*/
\r
455 #define DPC_WrLvODtEn (1<<12)
\r
456 #define DPC_DqsRcvTrEn (1<<13)
\r
457 #define DPC_DisAutoComp (1<<30)
\r
458 #define DPC_AsyncCompUpdate (1<<31)
\r
460 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_0 0x10 //DIMM0 Channel A
\r
461 #define DDRETC_DqsRcvEnFineDelayByte0_SHIFT 0
\r
462 #define DDRETC_DqsRcvEnFineDelayByte0_MASK 0x1f
\r
463 #define DDRETC_DqsRcvEnGrossDelayByte0_SHIFT 5
\r
464 #define DDRETC_DqsRcvEnGrossDelayByte0_MASK 0x3
\r
465 #define DDRETC_DqsRcvEnFineDelayByte1_SHIFT 8
\r
466 #define DDRETC_DqsRcvEnGrossDelayByte1_SHIFT 13
\r
467 #define DDRETC_DqsRcvEnFineDelayByte2_SHIFT 16
\r
468 #define DDRETC_DqsRcvEnGrossDelayByte2_SHIFT 21
\r
469 #define DDRETC_DqsRcvEnFineDelayByte3_SHIFT 24
\r
470 #define DDRETC_DqsRcvEnGrossDelayByte3_SHIFT 29
\r
472 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_1 0x11 //DIMM0 Channel A
\r
473 #define DDRETC_DqsRcvEnFineDelayByte4_SHIFT 0
\r
474 #define DDRETC_DqsRcvEnGrossDelayByte4_SHIFT 5
\r
475 #define DDRETC_DqsRcvEnFineDelayByte5_SHIFT 8
\r
476 #define DDRETC_DqsRcvEnGrossDelayByte5_SHIFT 13
\r
477 #define DDRETC_DqsRcvEnFineDelayByte6_SHIFT 16
\r
478 #define DDRETC_DqsRcvEnGrossDelayByte6_SHIFT 21
\r
479 #define DDRETC_DqsRcvEnFineDelayByte7_SHIFT 24
\r
480 #define DDRETC_DqsRcvEnGrossDelayByte7_SHIFT 29
\r
482 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_0_0 0x12
\r
483 #define DDRETCE_WrChkFineDlyByte0_SHIFT 0
\r
484 #define DDRETCE_WrChkGrossDlyByte0_SHIFT 5
\r
486 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_2 0x20 //DIMM0 channel B
\r
487 #define DDRETC_DqsRcvEnFineDelayByte8_SHIFT 0
\r
488 #define DDRETC_DqsRcvEnGrossDelayByte8_SHIFT 5
\r
489 #define DDRETC_DqsRcvEnFineDelayByte9_SHIFT 8
\r
490 #define DDRETC_DqsRcvEnGrossDelayByte9_SHIFT 13
\r
491 #define DDRETC_DqsRcvEnFineDelayByte10_SHIFT 16
\r
492 #define DDRETC_DqsRcvEnGrossDelayByte10_SHIFT 21
\r
493 #define DDRETC_DqsRcvEnFineDelayByte11_SHIFT 24
\r
494 #define DDRETC_DqsRcvEnGrossDelayByte11_SHIFT 29
\r
496 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_3 0x21 // DIMM0 Channel B
\r
497 #define DDRETC_DqsRcvEnFineDelayByte12_SHIFT 0
\r
498 #define DDRETC_DqsRcvEnGrossDelayByte12_SHIFT 5
\r
499 #define DDRETC_DqsRcvEnFineDelayByte13_SHIFT 8
\r
500 #define DDRETC_DqsRcvEnGrossDelayByte13_SHIFT 13
\r
501 #define DDRETC_DqsRcvEnFineDelayByte14_SHIFT 16
\r
502 #define DDRETC_DqsRcvEnGrossDelayByte14_SHIFT 21
\r
503 #define DDRETC_DqsRcvEnFineDelayByte15_SHIFT 24
\r
504 #define DDRETC_DqsRcvEnGrossDelayByte15_SHIFT 29
\r
506 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_0_1 0x22
\r
507 #define DDRETCE_WrChkFineDlyByte1_SHIFT 0
\r
508 #define DDRETCE_WrChkGrossDlyByte1_SHIFT 5
\r
510 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_0 0x13 //DIMM1
\r
511 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_1 0x14
\r
512 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_1_0 0x15
\r
513 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_2 0x23
\r
514 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_3 0x24
\r
515 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_1_1 0x25
\r
517 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_0 0x16 // DIMM2
\r
518 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_1 0x17
\r
519 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_2_0 0x18
\r
520 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_2 0x26
\r
521 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_3 0x27
\r
522 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_2_1 0x28
\r
524 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_0 0x19 // DIMM3
\r
525 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_1 0x1a
\r
526 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_3_0 0x1b
\r
527 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_2 0x29
\r
528 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_3 0x2a
\r
529 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_3_1 0x2b
\r
531 /* 04.06.2006 19:12 */
\r
535 #define DRAM_DQS_WRITE_TIME_CTRL_0_0 0x30 //DIMM0 Channel A
\r
536 #define DDWTC_WrDqsFineDlyByte0_SHIFT 0
\r
537 #define DDWTC_WrDqsFineDlyByte0_MASK 0x1f
\r
538 #define DDWTC_WrDqsGrossDlyByte0_SHIFT 5
\r
539 #define DDWTC_WrDqsGrossDlyByte0_MASK 0x3
\r
540 #define DDWTC_WrDqsFineDlyByte1_SHIFT 8
\r
541 #define DDWTC_WrDqsGrossDlyByte1_SHIFT 13
\r
542 #define DDWTC_WrDqsFineDlyByte2_SHIFT 16
\r
543 #define DDWTC_WrDqsGrossDlyByte2_SHIFT 21
\r
544 #define DDWTC_WrDqsFineDlyByte3_SHIFT 24
\r
545 #define DDWTC_WrDqsGrossDlyByte3_SHIFT 29
\r
547 #define DRAM_DQS_WRTIE_TIME_CTRL_0_1 0x31 //DIMM0 Channel A
\r
548 #define DDWTC_WrDqsFineDlyByte4_SHIFT 0
\r
549 #define DDWTC_WrDqsGrossDlyByte4_SHIFT 5
\r
550 #define DDWTC_WrDqsFineDlyByte5_SHIFT 8
\r
551 #define DDWTC_WrDqsGrossDlyByte5_SHIFT 13
\r
552 #define DDWTC_WrDqsFineDlyByte6_SHIFT 16
\r
553 #define DDWTC_WrDqsGrossDlyByte6_SHIFT 21
\r
554 #define DDWTC_WrDqsFineDlyByte7_SHIFT 24
\r
555 #define DDWTC_WrDqsGrossDlyByte7_SHIFT 29
\r
557 #define DRAM_DQS_WRITE_TIMING_CTRL_ECC_0_0 0x32
\r
558 #define DDWTCE_WrDqsChkFineDlyByte0_SHIFT 0
\r
559 #define DDWTCE_WrDqsChkGrossDlyByte0_SHIFT 5
\r
561 #define DRAM_DQS_WRITE_TIME_CTRL_0_2 0x40 //DIMM0 Channel B
\r
562 #define DDWTC_WrDqsFineDlyByte8_SHIFT 0
\r
563 #define DDWTC_WrDqsGrossDlyByte8_SHIFT 5
\r
564 #define DDWTC_WrDqsFineDlyByte9_SHIFT 8
\r
565 #define DDWTC_WrDqsGrossDlyByte9_SHIFT 13
\r
566 #define DDWTC_WrDqsFineDlyByte10_SHIFT 16
\r
567 #define DDWTC_WrDqsGrossDlyByte10_SHIFT 21
\r
568 #define DDWTC_WrDqsFineDlyByte11_SHIFT 24
\r
569 #define DDWTC_WrDqsGrossDlyByte11_SHIFT 29
\r
571 #define DRAM_DQS_WRTIE_TIME_CTRL_0_3 0x41 //DIMM0 Channel B
\r
572 #define DDWTC_WrDqsFineDlyByte12_SHIFT 0
\r
573 #define DDWTC_WrDqsGrossDlyByte12_SHIFT 5
\r
574 #define DDWTC_WrDqsFineDlyByte13_SHIFT 8
\r
575 #define DDWTC_WrDqsGrossDlyByte13_SHIFT 13
\r
576 #define DDWTC_WrDqsFineDlyByte14_SHIFT 16
\r
577 #define DDWTC_WrDqsGrossDlyByte14_SHIFT 21
\r
578 #define DDWTC_WrDqsFineDlyByte15_SHIFT 24
\r
579 #define DDWTC_WrDqsGrossDlyByte15_SHIFT 29
\r
581 #define DRAM_DQS_WRITE_TIMING_CTRL_ECC_0_1 0x42
\r
582 #define DDWTCE_WrDqsChkFineDlyByte1_SHIFT 0
\r
583 #define DDWTCE_WrDqsChkGrossDlyByte1_SHIFT 5
\r
585 #define DRAM_DQS_WRITE_TIME_CTRL_1_0 0x33 //DIMM1 Channel A
\r
586 #define DRAM_DQS_WRTIE_TIME_CTRL_1_1 0x34 //DIMM1 Channel A
\r
587 #define DRAM_DQS_WRITE_TIMING_CTRL_ECC_1_0 0x35
\r
588 #define DRAM_DQS_WRITE_TIME_CTRL_1_2 0x43 //DIMM1 Channel B
\r
589 #define DRAM_DQS_WRTIE_TIME_CTRL_1_3 0x44 //DIMM1 Channel B
\r
590 #define DRAM_DQS_WRITE_TIMING_CTRL_ECC_1_1 0x45
\r
593 #define DRAM_PHASE_RECOVERY_CTRL_0 0x50
\r
594 #define DPRC_PhRecFineDlyByte0_SHIFT 0
\r
595 #define DDWTC_PhRecFineDlyByte0_MASK 0x1f
\r
596 #define DDWTC_PhRecGrossDlyByte0_SHIFT 5
\r
597 #define DDWTC_PhRecGrossDlyByte0_MASK 0x3
\r
598 #define DDWTC_PhRecFineDlyByte1_SHIFT 8
\r
599 #define DDWTC_PhRecGrossDlyByte1_SHIFT 13
\r
600 #define DDWTC_PhRecFineDlyByte2_SHIFT 16
\r
601 #define DDWTC_PhRecGrossDlyByte2_SHIFT 21
\r
602 #define DDWTC_PhRecFineDlyByte3_SHIFT 24
\r
603 #define DDWTC_PhRecGrossDlyByte3_SHIFT 29
\r
605 #define DRAM_PHASE_RECOVERY_CTRL_1 0x51
\r
606 #define DPRC_PhRecFineDlyByte4_SHIFT 0
\r
607 #define DDWTC_PhRecGrossDlyByte4_SHIFT 5
\r
608 #define DDWTC_PhRecFineDlyByte5_SHIFT 8
\r
609 #define DDWTC_PhRecGrossDlyByte5_SHIFT 13
\r
610 #define DDWTC_PhRecFineDlyByte6_SHIFT 16
\r
611 #define DDWTC_PhRecGrossDlyByte6_SHIFT 21
\r
612 #define DDWTC_PhRecFineDlyByte7_SHIFT 24
\r
613 #define DDWTC_PhRecGrossDlyByte7_SHIFT 29
\r
615 #define DRAM_ECC_PHASE_RECOVERY_CTRL 0x52
\r
616 #define DEPRC_PhRecEccDlyByte0_SHIFT 0
\r
617 #define DEPRC_PhRecEccGrossDlyByte0_SHIFT 5
\r
619 #define DRAM_WRITE_LEVEL_ERROR 0x53 /* read only */
\r
620 #define DWLE_WrLvErr_SHIFT 0
\r
621 #define DWLE_WrLvErr_MASK 0xff
\r
623 #define DRAM_CTRL_MISC 0xa0
\r
624 #define DCM_MemCleared (1<<0) /* RD == F2x110 [MemCleared] */
\r
625 #define DCM_DramEnabled (1<<9) /* RD == F2x110 [DramEnabled] */
\r
627 #define NB_TIME_STAMP_COUNT_LOW 0xb0
\r
628 #define TscLow_SHIFT 0
\r
629 #define TscLow_MASK 0xffffffff
\r
631 #define NB_TIME_STAMP_COUNT_HIGH 0xb4
\r
632 #define TscHigh_SHIFT 0
\r
633 #define TscHigh_Mask 0xff
\r
635 #define DCT_DEBUG_CTRL 0xf0 /* 0xf0 for DCT0, 0x1f0 is for DCT1*/
\r
636 #define DDC_DllAdjust_SHIFT 0
\r
637 #define DDC_DllAdjust_MASK 0xff
\r
638 #define DDC_DllSlower (1<<8)
\r
639 #define DDC_DllFaster (1<<9)
\r
640 #define DDC_WrtDqsAdjust_SHIFT 16
\r
641 #define DDC_WrtDqsAdjust_MASK 0x7
\r
642 #define DDC_WrtDqsAdjustEn (1<<19)
\r
644 #define DRAM_CTRL_SEL_LOW 0x110
\r
645 #define DCSL_DctSelHiRngEn (1<<0)
\r
646 #define DCSL_DctSelHi (1<<1)
\r
647 #define DCSL_DctSelIntLvEn (1<<2)
\r
648 #define DCSL_MemClrInit (1<<3) /* WR only */
\r
649 #define DCSL_DctGangEn (1<<4)
\r
650 #define DCSL_DctDataIntLv (1<<5)
\r
651 #define DCSL_DctSelIntLvAddr_SHIFT
\r
652 #define DCSL_DctSelIntLvAddr_MASK 3
\r
653 #define DCSL_DramEnable (1<<8) /* RD only */
\r
654 #define DCSL_MemClrBusy (1<<9) /* RD only */
\r
655 #define DCSL_MemCleared (1<<10) /* RD only */
\r
656 #define DCSL_DctSelBaseAddr_47_27_SHIFT 11
\r
657 #define DCSL_DctSelBaseAddr_47_27_MASK 0x1fffff
\r
659 #define DRAM_CTRL_SEL_HIGH 0x114
\r
660 #define DCSH_DctSelBaseOffset_47_26_SHIFT 10
\r
661 #define DCSH_DctSelBaseOffset_47_26_MASK 0x3fffff
\r
663 #define MEM_CTRL_CONF_LOW 0x118
\r
664 #define MCCL_MctPriCpuRd (1<<0)
\r
665 #define MCCL_MctPriCpuWr (1<<1)
\r
666 #define MCCL_MctPriIsocRd_SHIFT 4
\r
667 #define MCCL_MctPriIsoc_MASK 0x3
\r
668 #define MCCL_MctPriIsocWr_SHIFT 6
\r
669 #define MCCL_MctPriIsocWe_MASK 0x3
\r
670 #define MCCL_MctPriDefault_SHIFT 8
\r
671 #define MCCL_MctPriDefault_MASK 0x3
\r
672 #define MCCL_MctPriWr_SHIFT 10
\r
673 #define MCCL_MctPriWr_MASK 0x3
\r
674 #define MCCL_MctPriIsoc_SHIFT 12
\r
675 #define MCCL_MctPriIsoc_MASK 0x3
\r
676 #define MCCL_MctPriTrace_SHIFT 14
\r
677 #define MCCL_MctPriTrace_MASK 0x3
\r
678 #define MCCL_MctPriScrub_SHIFT 16
\r
679 #define MCCL_MctPriScrub_MASK 0x3
\r
680 #define MCCL_McqMedPriByPassMax_SHIFT 20
\r
681 #define MCCL_McqMedPriByPassMax_MASK 0x7
\r
682 #define MCCL_McqHiPriByPassMax_SHIFT 24
\r
683 #define MCCL_McqHiPriByPassMax_MASK 0x7
\r
684 #define MCCL_MctVarPriCntLmt_SHIFT 28
\r
685 #define MCCL_MctVarPriCntLmt_MASK 0x7
\r
687 #define MEM_CTRL_CONF_HIGH 0x11c
\r
688 #define MCCH_DctWrLimit_SHIFT 0
\r
689 #define MCCH_DctWrLimit_MASK 0x3
\r
690 #define MCCH_MctWrLimit_SHIFT 2
\r
691 #define MCCH_MctWrLimit_MASK 0x1f
\r
692 #define MCCH_MctPrefReqLimit_SHIFT 7
\r
693 #define MCCH_MctPrefReqLimit_MASK 0x1f
\r
694 #define MCCH_PrefCpuDis (1<<12)
\r
695 #define MCCH_PrefIoDis (1<<13)
\r
696 #define MCCH_PrefIoFixStrideEn (1<<14)
\r
697 #define MCCH_PrefFixStrideEn (1<<15)
\r
698 #define MCCH_PrefFixDist_SHIFT 16
\r
699 #define MCCH_PrefFixDist_MASK 0x3
\r
700 #define MCCH_PrefConfSat_SHIFT 18
\r
701 #define MCCH_PrefConfSat_MASK 0x3
\r
702 #define MCCH_PrefOneConf_SHIFT 20
\r
703 #define MCCH_PrefOneConf_MASK 0x3
\r
704 #define MCCH_PrefTwoConf_SHIFT 22
\r
705 #define MCCH_PrefTwoConf_MASK 0x7
\r
706 #define MCCH_PrefThreeConf_SHIFT 25
\r
707 #define MCCH_prefThreeConf_MASK 0x7
\r
708 #define MCCH_PrefDramTrainMode (1<<28)
\r
709 #define MCCH_FlushWrOnStpGnt (1<<29)
\r
710 #define MCCH_FlushWr (1<<30)
\r
711 #define MCCH_MctScrubEn (1<<31)
\r
715 #define MCA_NB_CONTROL 0x40
\r
716 #define MNCT_CorrEccEn (1<<0)
\r
717 #define MNCT_UnCorrEccEn (1<<1)
\r
718 #define MNCT_CrcErr0En (1<<2) /* Link 0 */
\r
719 #define MNCT_CrcErr1En (1<<3)
\r
720 #define MNCT_CrcErr2En (1<<4)
\r
721 #define MBCT_SyncPkt0En (1<<5) /* Link 0 */
\r
722 #define MBCT_SyncPkt1En (1<<6)
\r
723 #define MBCT_SyncPkt2En (1<<7)
\r
724 #define MBCT_MstrAbrtEn (1<<8)
\r
725 #define MBCT_TgtAbrtEn (1<<9)
\r
726 #define MBCT_GartTblEkEn (1<<10)
\r
727 #define MBCT_AtomicRMWEn (1<<11)
\r
728 #define MBCT_WdogTmrRptEn (1<<12)
\r
729 #define MBCT_DevErrEn (1<<13)
\r
730 #define MBCT_L3ArrayCorEn (1<<14)
\r
731 #define MBCT_L3ArrayUncEn (1<<15)
\r
732 #define MBCT_HtProtEn (1<<16)
\r
733 #define MBCT_HtDataEn (1<<17)
\r
734 #define MBCT_DramParEn (1<<18)
\r
735 #define MBCT_RtryHt0En (1<<19) /* Link 0 */
\r
736 #define MBCT_RtryHt1En (1<<20)
\r
737 #define MBCT_RtryHt2En (1<<21)
\r
738 #define MBCT_RtryHt3En (1<<22)
\r
739 #define MBCT_CrcErr3En (1<<23) /* Link 3*/
\r
740 #define MBCT_SyncPkt3En (1<<24) /* Link 4 */
\r
741 #define MBCT_McaUsPwDatErrEn (1<<25)
\r
742 #define MBCT_NbArrayParEn (1<<26)
\r
743 #define MBCT_TblWlkDatErrEn (1<<27)
\r
744 #define MBCT_FbDimmCorErrEn (1<<28)
\r
745 #define MBCT_FbDimmUnCorErrEn (1<<29)
\r
749 #define MCA_NB_CONFIG 0x44
\r
750 #define MNC_CpuRdDatErrEn (1<<1)
\r
751 #define MNC_SyncOnUcEccEn (1<<2)
\r
752 #define MNC_SynvPktGenDis (1<<3)
\r
753 #define MNC_SyncPktPropDis (1<<4)
\r
754 #define MNC_IoMstAbortDis (1<<5)
\r
755 #define MNC_CpuErrDis (1<<6)
\r
756 #define MNC_IoErrDis (1<<7)
\r
757 #define MNC_WdogTmrDis (1<<8)
\r
758 #define MNC_WdogTmrCntSel_2_0_SHIFT 9 /* 3 is ar f3x180 */
\r
759 #define MNC_WdogTmrCntSel_2_0_MASK 0x3
\r
760 #define MNC_WdogTmrBaseSel_SHIFT 12
\r
761 #define MNC_WdogTmrBaseSel_MASK 0x3
\r
762 #define MNC_LdtLinkSel_SHIFT 14
\r
763 #define MNC_LdtLinkSel_MASK 0x3
\r
764 #define MNC_GenCrcErrByte0 (1<<16)
\r
765 #define MNC_GenCrcErrByte1 (1<<17)
\r
766 #define MNC_SubLinkSel_SHIFT 18
\r
767 #define MNC_SubLinkSel_MASK 0x3
\r
768 #define MNC_SyncOnWdogEn (1<<20)
\r
769 #define MNC_SyncOnAnyErrEn (1<<21)
\r
770 #define MNC_DramEccEn (1<<22)
\r
771 #define MNC_ChipKillEccEn (1<<23)
\r
772 #define MNC_IoRdDatErrEn (1<<24)
\r
773 #define MNC_DisPciCfgCpuErrRsp (1<<25)
\r
774 #define MNC_CorrMcaExcEn (1<<26)
\r
775 #define MNC_NbMcaToMstCpuEn (1<<27)
\r
776 #define MNC_DisTgtAbtCpuErrRsp (1<<28)
\r
777 #define MNC_DisMstAbtCpuErrRsp (1<<29)
\r
778 #define MNC_SyncOnDramAdrParErrEn (1<<30)
\r
779 #define MNC_NbMcaLogEn (1<<31)
\r
781 #define MCA_NB_STATUS_LOW 0x48
\r
782 #define MNSL_ErrorCode_SHIFT 0
\r
783 #define MNSL_ErrorCode_MASK 0xffff
\r
784 #define MNSL_ErrorCodeExt_SHIFT 16
\r
785 #define MNSL_ErrorCodeExt_MASK 0x1f
\r
786 #define MNSL_Syndrome_15_8_SHIFT 24
\r
787 #define MNSL_Syndrome_15_8_MASK 0xff
\r
789 #define MCA_NB_STATUS_HIGH 0x4c
\r
790 #define MNSH_ErrCPU_SHIFT 0
\r
791 #define MNSH_ErrCPU_MASK 0xf
\r
792 #define MNSH_LDTLink_SHIFT 4
\r
793 #define MNSH_LDTLink_MASK 0xf
\r
794 #define MNSH_ErrScrub (1<<8)
\r
795 #define MNSH_SubLink (1<<9)
\r
796 #define MNSH_McaStatusSubCache_SHIFT 10
\r
797 #define MNSH_McaStatusSubCache_MASK 0x3
\r
798 #define MNSH_Deffered (1<<12)
\r
799 #define MNSH_UnCorrECC (1<<13)
\r
800 #define MNSH_CorrECC (1<<14)
\r
801 #define MNSH_Syndrome_7_0_SHIFT 15
\r
802 #define MNSH_Syndrome_7_0_MASK 0xff
\r
803 #define MNSH_PCC (1<<25)
\r
804 #define MNSH_ErrAddrVal (1<<26)
\r
805 #define MNSH_ErrMiscVal (1<<27)
\r
806 #define MNSH_ErrEn (1<<28)
\r
807 #define MNSH_ErrUnCorr (1<<29)
\r
808 #define MNSH_ErrOver (1<<30)
\r
809 #define MNSH_ErrValid (1<<31)
\r
811 #define MCA_NB_ADDR_LOW 0x50
\r
812 #define MNAL_ErrAddr_31_1_SHIFT 1
\r
813 #define MNAL_ErrAddr_31_1_MASK 0x7fffffff
\r
815 #define MCA_NB_ADDR_HIGH 0x54
\r
816 #define MNAL_ErrAddr_47_32_SHIFT 0
\r
817 #define MNAL_ErrAddr_47_32_MASK 0xffff
\r
819 #define DRAM_SCRUB_RATE_CTRL 0x58
\r
820 #define SCRUB_NONE 0
\r
821 #define SCRUB_40ns 1
\r
822 #define SCRUB_80ns 2
\r
823 #define SCRUB_160ns 3
\r
824 #define SCRUB_320ns 4
\r
825 #define SCRUB_640ns 5
\r
826 #define SCRUB_1_28us 6
\r
827 #define SCRUB_2_56us 7
\r
828 #define SCRUB_5_12us 8
\r
829 #define SCRUB_10_2us 9
\r
830 #define SCRUB_20_5us 0xa
\r
831 #define SCRUB_41_0us 0xb
\r
832 #define SCRUB_81_9us 0xc
\r
833 #define SCRUB_163_8us 0xd
\r
834 #define SCRUB_327_7us 0xe
\r
835 #define SCRUB_655_4us 0xf
\r
836 #define SCRUB_1_31ms 0x10
\r
837 #define SCRUB_2_62ms 0x11
\r
838 #define SCRUB_5_24ms 0x12
\r
839 #define SCRUB_10_49ms 0x13
\r
840 #define SCRUB_20_97ms 0x14
\r
841 #define SCRUB_42ms 0x15
\r
842 #define SCRUB_84ms 0x16
\r
843 #define DSRC_DramScrub_SHFIT 0
\r
844 #define DSRC_DramScrub_MASK 0x1f
\r
845 #define DSRC_L2Scrub_SHIFT 8
\r
846 #define DSRC_L2Scrub_MASK 0x1f
\r
847 #define DSRC_DcacheScrub_SHIFT 16
\r
848 #define DSRC_DcacheScrub_MASK 0x1f
\r
849 #define DSRC_L3Scrub_SHIFT 24
\r
850 #define DSRC_L3Scrub_MASK 0x1f
\r
852 #define DRAM_SCRUB_ADDR_LOW 0x5C
\r
853 #define DSAL_ScrubReDirEn (1<<0)
\r
854 #define DSAL_ScrubAddrLo_SHIFT 6
\r
855 #define DSAL_ScrubAddrLo_MASK 0x3ffffff
\r
857 #define DRAM_SCRUB_ADDR_HIGH 0x60
\r
858 #define DSAH_ScrubAddrHi_SHIFT 0
\r
859 #define DSAH_ScrubAddrHi_MASK 0xffff
\r
861 #define HW_THERMAL_CTRL 0x64
\r
863 #define SW_THERMAL_CTRL 0x68
\r
865 #define DATA_BUF_CNT 0x6c
\r
867 #define SRI_XBAR_CMD_BUF_CNT 0x70
\r
869 #define XBAR_SRI_CMD_BUF_CNT 0x74
\r
871 #define MCT_XBAR_CMD_BUF_CNT 0x78
\r
873 #define ACPI_PWR_STATE_CTRL 0x80 /* till 0x84 */
\r
875 #define NB_CONFIG_LOW 0x88
\r
876 #define NB_CONFIG_HIGH 0x8c
\r
878 #define GART_APERTURE_CTRL 0x90
\r
880 #define GART_APERTURE_BASE 0x94
\r
882 #define GART_TBL_BASE 0x98
\r
884 #define GART_CACHE_CTRL 0x9c
\r
886 #define PWR_CTRL_MISC 0xa0
\r
888 #define RPT_TEMP_CTRL 0xa4
\r
890 #define ON_LINE_SPARE_CTRL 0xb0
\r
892 #define SBI_P_STATE_LIMIT 0xc4
\r
894 #define CLK_PWR_TIMING_CTRL0 0xd4
\r
895 #define CLK_PWR_TIMING_CTRL1 0xd8
\r
896 #define CLK_PWR_TIMING_CTRL2 0xdc
\r
898 #define THERMTRIP_STATUS 0xE4
\r
901 #define NORTHBRIDGE_CAP 0xE8
\r
902 #define NBCAP_TwoChanDRAMcap (1 << 0)
\r
903 #define NBCAP_DualNodeMPcap (1 << 1)
\r
904 #define NBCAP_EightNodeMPcap (1 << 2)
\r
905 #define NBCAP_ECCcap (1 << 3)
\r
906 #define NBCAP_ChipkillECCcap (1 << 4)
\r
907 #define NBCAP_DdrMaxRate_SHIFT 5
\r
908 #define NBCAP_DdrMaxRate_MASK 7
\r
909 #define NBCAP_DdrMaxRate_400 7
\r
910 #define NBCAP_DdrMaxRate_533 6
\r
911 #define NBCAP_DdrMaxRate_667 5
\r
912 #define NBCAP_DdrMaxRate_800 4
\r
913 #define NBCAP_DdrMaxRate_1067 3
\r
914 #define NBCAP_DdrMaxRate_1333 2
\r
915 #define NBCAP_DdrMaxRate_1600 1
\r
916 #define NBCAP_DdrMaxRate_3_2G 6
\r
917 #define NBCAP_DdrMaxRate_4_0G 5
\r
918 #define NBCAP_DdrMaxRate_4_8G 4
\r
919 #define NBCAP_DdrMaxRate_6_4G 3
\r
920 #define NBCAP_DdrMaxRate_8_0G 2
\r
921 #define NBCAP_DdrMaxRate_9_6G 1
\r
922 #define NBCAP_Mem_ctrl_cap (1 << 8)
\r
923 #define MBCAP_SVMCap (1<<9)
\r
924 #define NBCAP_HtcCap (1<<10)
\r
925 #define NBCAP_CmpCap_SHIFT 12
\r
926 #define NBCAP_CmpCap_MASK 3
\r
927 #define NBCAP_MpCap_SHIFT 16
\r
928 #define NBCAP_MpCap_MASK 7
\r
929 #define NBCAP_MpCap_1N 7
\r
930 #define NBCAP_MpCap_2N 6
\r
931 #define NBCAP_MpCap_4N 5
\r
932 #define NBCAP_MpCap_8N 4
\r
933 #define NBCAP_MpCap_32N 0
\r
934 #define NBCAP_UnGangEn_SHIFT 20
\r
935 #define NBCAP_UnGangEn_MASK 0xf
\r
936 #define NBCAP_L3Cap (1<<25)
\r
937 #define NBCAP_HtAcCap (1<<26)
\r
939 /* 04/04/2006 18:00 */
\r
941 #define EXT_NB_MCA_CTRL 0x180
\r
943 #define NB_EXT_CONF 0x188
\r
944 #define DOWNCORE_CTRL 0x190
\r
945 #define DWNCC_DisCore_SHIFT 0
\r
946 #define DWNCC_DisCore_MASK 0xf
\r
948 /* Function 5 for FBDIMM */
\r
949 #define FBD_DRAM_TIMING_LOW
\r
951 #define LinkConnected (1 << 0)
\r
952 #define InitComplete (1 << 1)
\r
953 #define NonCoherent (1 << 2)
\r
954 #define ConnectionPending (1 << 4)
\r
956 // Use the LAPIC timer count register to hold each core's init status
\r
957 // Format: byte 0 - state
\r
958 // byte 1 - fid_max
\r
959 // byte 2 - nb_cof_vid_update
\r
960 // byte 3 - apic id
\r
962 #define LAPIC_MSG_REG 0x380
\r
963 #define F10_APSTATE_STARTED 0x13 // start of AP execution
\r
964 #define F10_APSTATE_STOPPED 0x14 // allow AP to stop
\r
965 #define F10_APSTATE_RESET 0x01 // waiting for warm reset
\r
967 #include "amdfam10_nums.h"
\r
971 #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
\r
973 #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
\r
977 #include "raminit.h"
\r
979 #if CONFIG_AMDMCT == 0
\r
981 //struct definitions
\r
984 u8 per_rank; // it is rows + col + bank_lines + data lines */
\r
987 u8 bank; //1, 2, 3 mean 2, 4, 8
\r
989 } __attribute__((packed));
\r
991 struct mem_info { // pernode
\r
993 struct dimm_size sz[DIMM_SOCKETS*2]; // for ungang support
\r
996 u32 single_rank_mask;
\r
999 // u32 registered_mask;
\r
1001 u8 is_registered; //don't support mixing on the same channel or between channel
\r
1002 u8 is_ecc; //don't support mixing on the same channel or between channel
\r
1004 u8 memclk_set; // we need to use this to retrieve the mem param, all dimms need to work at same freq for one node
\r
1005 u8 is_cs_interleaved[2]; //cs
\r
1007 } __attribute__((packed));
\r
1009 #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
\r
1010 #include "../amdmct/mct_ddr3/mct_d.h"
\r
1012 #include "../amdmct/mct/mct_d.h"
\r
1016 struct link_pair_t {
\r
1027 } __attribute__((packed));
\r
1029 struct nodes_info_t {
\r
1030 u32 nodes_in_group; // could be 2, 3, 4, 5, 6, 7, 8
\r
1031 u32 groups_in_plane; // could be 1, 2, 3, 4, 5
\r
1032 u32 planes; // could be 1, 2
\r
1033 u32 up_planes; // down planes will be [up_planes, planes)
\r
1034 } __attribute__((packed));
\r
1036 /* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/
\r
1037 #if CONFIG_AMDMCT == 0
\r
1039 //#define MEM_CS_COPY 1
\r
1040 #define MEM_CS_COPY NODE_NUMS
\r
1042 #if CONFIG_MEM_TRAIN_SEQ == 0
\r
1043 #define DQS_DELAY_COPY NODE_NUMS
\r
1045 // #define DQS_DELAY_COPY 1
\r
1046 #define DQS_DELAY_COPY NODE_NUMS
\r
1052 int32_t needs_reset;
\r
1054 u8 ln[NODE_NUMS*NODE_NUMS];// [0, 3] link n, [4, 7] will be hop num
\r
1055 u16 ln_tn[NODE_NUMS*8]; // for 0x0zzz: bit [0,7] target node num, bit[8,11] respone link from target num; 0x80ff mean not inited, 0x4yyy mean non coherent and yyy is link pair index
\r
1056 struct nodes_info_t nodes_info;
\r
1059 u8 host_link_freq[NODE_NUMS*8]; // record freq for every link from cpu, 0x0f means don't need to touch it
\r
1060 u16 host_link_freq_cap[NODE_NUMS*8]; //cap
\r
1068 u32 ht_c_conf_bus[HC_NUMS]; // 4-->32
\r
1070 struct link_pair_t link_pair[HC_NUMS*4];// enough? only in_conherent, 32 chain and every chain have 4 HT device
\r
1071 u32 link_pair_num;
\r
1073 struct mem_controller ctrl[NODE_NUMS];
\r
1076 // sMCTStruct MCTData;
\r
1077 // sDCTStruct *DCTNodeData[NODE_NUMS];
\r
1078 // sDCTStruct DCTNodeData_a[NODE_NUMS];
\r
1079 struct MCTStatStruc MCTstat;
\r
1080 struct DCTStatStruc DCTstatA[NODE_NUMS];
\r
1083 u8 ctrl_present[NODE_NUMS];
\r
1084 struct mem_info meminfo[NODE_NUMS];
\r
1085 u8 mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail
\r
1089 //if we are getting tight of global space, may need to squesh following to one copy
\r
1090 u32 mem_base[MEM_CS_COPY][2]; // two dct
\r
1091 u32 cs_base[MEM_CS_COPY][2][8]; //8 cs_idx
\r
1092 u32 hole_startk; // 0 mean hole
\r
1094 u8 dqs_delay_a[DQS_DELAY_COPY*2*4*2*9]; //8 node, channel 2, dimm 4, direction 2 , bytelane *9
\r
1095 u8 dqs_rcvr_dly_a[DQS_DELAY_COPY*2*4*9]; //8 node, channel 2, dimm 4, bytelane *9
\r
1096 u8 dqs_rcvr_dly_a_1[9]; //8 node, channel 2, dimm 4, bytelane *9
\r
1099 } __attribute__((packed));
\r
1101 #ifndef __PRE_RAM__
\r
1102 device_t get_node_pci(u32 nodeid, u32 fn);
\r
1105 #if CONFIG_AMDMCT == 0
\r
1107 #ifdef __PRE_RAM__
\r
1108 static void soft_reset(void);
\r
1110 static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
\r
1115 unsigned needs_reset = 0;
\r
1117 if(sysinfo->nodes == 1) return; // in case only one cpu installed
\r
1118 for(i=1; i<sysinfo->nodes; i++) {
\r
1119 /* Skip everything if I don't have any memory on this controller */
\r
1120 if(sysinfo->mem_trained[i]==0x00) continue;
\r
1123 mask_lo |= (1<<i);
\r
1125 mask_hi |= (1<<(i-32));
\r
1132 if(mask_lo & (1<<i)) {
\r
1133 if(sysinfo->mem_trained[i] != 0x80) {
\r
1134 mask_lo &= ~(1<<i);
\r
1138 if(mask_hi & (1<<(i-32))) {
\r
1139 if(sysinfo->mem_trained[i] != 0x80) {
\r
1140 mask_hi &= ~(1<<(i-32));
\r
1145 if((!mask_lo) && (!mask_hi)) break;
\r
1148 i%=sysinfo->nodes;
\r
1151 for(i=0; i<sysinfo->nodes; i++) {
\r
1152 #ifdef __PRE_RAM__
\r
1153 print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
\r
1155 printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
\r
1157 switch(sysinfo->mem_trained[i]) {
\r
1158 case 0: //don't need train
\r
1161 case 0x81: //recv1: fail
\r
1162 case 0x82: //Pos :fail
\r
1163 case 0x83: //recv2: fail
\r
1169 #ifdef __PRE_RAM__
\r
1170 print_debug("mem trained failed\n");
\r
1173 printk(BIOS_DEBUG, "mem trained failed\n");
\r
1182 #ifdef __PRE_RAM__
\r
1183 void showallroutes(int level, device_t dev);
\r
1185 void setup_resource_map_offset(const u32 *register_values, u32 max, u32
\r
1186 offset_pci_dev, u32 offset_io_base);
\r
1188 void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32
\r
1189 offset_pci_dev, u32 offset_io_base);
\r
1191 void setup_resource_map_x(const u32 *register_values, u32 max);
\r
1193 /* reset_test.c */
\r
1194 u32 cpu_init_detected(u8 nodeid);
\r
1195 u32 bios_reset_detected(void);
\r
1196 u32 cold_reset_detected(void);
\r
1197 u32 other_reset_detected(void);
\r
1198 u32 get_sblk(void);
\r
1199 u8 get_sbbusn(u8 sblk);
\r
1202 #endif /* AMDFAM10_H */
\r
projects / coreboot.git / blob