2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <device/hypertransport.h>
33 #include <cpu/x86/lapic.h>
35 #include "agesawrapper.h"
37 #include "northbridge.h"
38 #if CONFIG_AMD_SB_CIMX
42 //#define FX_DEVS NODE_NUMS
45 static device_t __f0_dev[FX_DEVS];
46 static device_t __f1_dev[FX_DEVS];
47 static device_t __f2_dev[FX_DEVS];
48 static device_t __f4_dev[FX_DEVS];
49 static unsigned fx_devs = 0;
51 device_t get_node_pci(u32 nodeid, u32 fn)
53 return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
56 static void get_fx_devs(void)
59 for (i = 0; i < FX_DEVS; i++) {
60 __f0_dev[i] = get_node_pci(i, 0);
61 __f1_dev[i] = get_node_pci(i, 1);
62 __f2_dev[i] = get_node_pci(i, 2);
63 __f4_dev[i] = get_node_pci(i, 4);
64 if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
67 if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
68 die("Cannot find 0:0x18.[0|1]\n");
72 static u32 f1_read_config32(unsigned reg)
76 return pci_read_config32(__f1_dev[0], reg);
79 static void f1_write_config32(unsigned reg, u32 value)
84 for (i = 0; i < fx_devs; i++) {
87 if (dev && dev->enabled) {
88 pci_write_config32(dev, reg, value);
93 static u32 amdfam14_nodeid(device_t dev)
95 return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
98 #include "amdfam14_conf.c"
100 static void northbridge_init(device_t dev)
102 printk(BIOS_DEBUG, "Northbridge init\n");
105 static void set_vga_enable_reg(u32 nodeid, u32 linkn)
109 val = 1 | (nodeid << 4) | (linkn << 12);
110 /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb,
112 f1_write_config32(0xf4, val);
116 static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
119 struct resource *res;
120 unsigned nodeid, link = 0;
123 for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
125 dev = __f0_dev[nodeid];
128 for (link = 0; !res && (link < 8); link++) {
129 res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
135 if ((goal_link == (link - 1)) &&
136 (goal_nodeid == (nodeid - 1)) && (res->flags <= 1)) {
143 static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid,
146 struct resource *resource;
150 result = reg_useable(0xc0, dev, nodeid, link);
152 /* I have been allocated this one */
157 /* Because of Extend conf space, we will never run out of reg,
158 * but we need one index to differ them. So ,same node and same
159 * link can have multi range
161 u32 index = get_io_addr_index(nodeid, link);
162 reg = 0x110 + (index << 24) + (4 << 20); // index could be 0, 255
165 resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
170 static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid,
173 struct resource *resource;
177 for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
179 result = reg_useable(reg, dev, nodeid, link);
181 /* I have been allocated this one */
183 } else if (result > 1) {
184 /* I have a free register pair */
193 /* Because of Extend conf space, we will never run out of reg,
194 * but we need one index to differ them. So ,same node and same
195 * link can have multi range
197 u32 index = get_mmio_addr_index(nodeid, link);
198 reg = 0x110 + (index << 24) + (6 << 20); // index could be 0, 63
201 resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
205 static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link)
207 struct resource *resource;
209 /* Initialize the io space constraints on the current bus */
210 resource = amdfam14_find_iopair(dev, nodeid, link);
213 #if CONFIG_EXT_CONF_SUPPORT == 1
214 if ((resource->index & 0x1fff) == 0x1110) { // ext
218 align = log2(HT_IO_HOST_ALIGN);
221 resource->align = align;
222 resource->gran = align;
223 resource->limit = 0xffffUL;
224 resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
227 /* Initialize the prefetchable memory constraints on the current bus */
228 resource = amdfam14_find_mempair(dev, nodeid, link);
232 resource->align = log2(HT_MEM_HOST_ALIGN);
233 resource->gran = log2(HT_MEM_HOST_ALIGN);
234 resource->limit = 0xffffffffffULL;
235 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
236 resource->flags |= IORESOURCE_BRIDGE;
238 #if CONFIG_EXT_CONF_SUPPORT == 1
239 if ((resource->index & 0x1fff) == 0x1110) { // ext
240 normalize_resource(resource);
246 /* Initialize the memory constraints on the current bus */
247 resource = amdfam14_find_mempair(dev, nodeid, link);
251 resource->align = log2(HT_MEM_HOST_ALIGN);
252 resource->gran = log2(HT_MEM_HOST_ALIGN);
253 resource->limit = 0xffffffffffULL;
254 resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
255 #if CONFIG_EXT_CONF_SUPPORT == 1
256 if ((resource->index & 0x1fff) == 0x1110) { // ext
257 normalize_resource(resource);
263 static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
265 struct resource *min;
267 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
269 if (min && tolm > min->base) {
275 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
277 struct hw_mem_hole_info {
278 unsigned hole_startk;
282 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
284 struct hw_mem_hole_info mem_hole;
286 mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
287 mem_hole.node_id = -1;
289 struct dram_base_mask_t d;
291 d = get_dram_base_mask(0);
293 hole = pci_read_config32(__f1_dev[0], 0xf0);
294 if (hole & 1) { // we find the hole
295 mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
296 mem_hole.node_id = 0; // record the node No with hole
300 /* We need to double check if there is speical set on base reg and limit reg
301 * are not continous instead of hole, it will find out it's hole_startk
303 if (mem_hole.node_id == -1) {
304 resource_t limitk_pri = 0;
305 struct dram_base_mask_t d;
306 resource_t base_k, limit_k;
307 d = get_dram_base_mask(0);
309 base_k = ((resource_t) (d.base & 0x1fffff00)) << 9;
310 if (base_k <= 4 * 1024 * 1024) {
311 if (limitk_pri != base_k) { // we find the hole
312 mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G
313 mem_hole.node_id = 0;
318 ((resource_t) ((d.mask + 0x00000100) & 0x1fffff00))
320 limitk_pri = limit_k;
329 #if CONFIG_GFXUMA == 1
330 extern uint64_t uma_memory_base, uma_memory_size;
332 static void add_uma_resource(struct device *dev, int index)
334 struct resource *resource;
336 printk(BIOS_DEBUG, "\nFam14h - Adding UMA memory.\n");
338 resource = new_resource(dev, index);
339 resource->base = (resource_t) uma_memory_base;
340 resource->size = (resource_t) uma_memory_size;
341 resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
342 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
346 static void read_resources(device_t dev)
351 printk(BIOS_DEBUG, "\nFam14h - read_resources.\n");
353 nodeid = amdfam14_nodeid(dev);
354 for (link = dev->link_list; link; link = link->next) {
355 if (link->children) {
356 amdfam14_link_read_bases(dev, nodeid, link->link_num);
361 static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
363 resource_t rbase, rend;
364 unsigned reg, link_num;
367 printk(BIOS_DEBUG, "\nFam14h - set_resource.\n");
369 /* Make certain the resource has actually been set */
370 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
374 /* If I have already stored this resource don't worry about it */
375 if (resource->flags & IORESOURCE_STORED) {
379 /* Only handle PCI memory and IO resources */
380 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
383 /* Ensure I am actually looking at a resource of function 1 */
384 if ((resource->index & 0xffff) < 0x1000) {
387 /* Get the base address */
388 rbase = resource->base;
390 /* Get the limit (rounded up) */
391 rend = resource_end(resource);
393 /* Get the register and link */
394 reg = resource->index & 0xfff; // 4k
395 link_num = IOINDEX_LINK(resource->index);
397 if (resource->flags & IORESOURCE_IO) {
398 set_io_addr_reg(dev, nodeid, link_num, reg, rbase >> 8,
400 } else if (resource->flags & IORESOURCE_MEM) {
401 set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >> 24),
402 rbase >> 8, rend >> 8, 1); // [39:8]
404 resource->flags |= IORESOURCE_STORED;
405 sprintf(buf, " <node %x link %x>", nodeid, link_num);
406 report_resource_stored(dev, resource, buf);
409 #if CONFIG_CONSOLE_VGA_MULTI
410 extern device_t vga_pri; // the primary vga device, defined in device.c
413 static void create_vga_resource(device_t dev, unsigned nodeid)
417 printk(BIOS_DEBUG, "\nFam14h - create_vga_resource.\n");
419 /* find out which link the VGA card is connected,
420 * we only deal with the 'first' vga card */
421 for (link = dev->link_list; link; link = link->next) {
422 if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
423 #if CONFIG_CONSOLE_VGA_MULTI
425 "VGA: vga_pri bus num = %d bus range [%d,%d]\n",
426 vga_pri->bus->secondary, link->secondary,
428 /* We need to make sure the vga_pri is under the link */
429 if ((vga_pri->bus->secondary >= link->secondary) &&
430 (vga_pri->bus->secondary <= link->subordinate))
436 /* no VGA card installed */
440 printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n",
441 dev_path(dev), nodeid, link->link_num);
442 set_vga_enable_reg(nodeid, link->link_num);
445 static void set_resources(device_t dev)
449 struct resource *res;
451 printk(BIOS_DEBUG, "\nFam14h - set_resources.\n");
453 /* Find the nodeid */
454 nodeid = amdfam14_nodeid(dev);
456 create_vga_resource(dev, nodeid);
458 /* Set each resource we have found */
459 for (res = dev->resource_list; res; res = res->next) {
460 set_resource(dev, res, nodeid);
463 for (bus = dev->link_list; bus; bus = bus->next) {
465 assign_resources(bus);
470 /* Domain/Root Complex related code */
472 static void domain_read_resources(device_t dev)
476 printk(BIOS_DEBUG, "\nFam14h - domain_read_resources.\n");
478 /* Find the already assigned resource pairs */
480 for (reg = 0x80; reg <= 0xc0; reg += 0x08) {
482 base = f1_read_config32(reg);
483 limit = f1_read_config32(reg + 0x04);
484 /* Is this register allocated? */
485 if ((base & 3) != 0) {
486 unsigned nodeid, reg_link;
488 if (reg < 0xc0) { // mmio
489 nodeid = (limit & 0xf) + (base & 0x30);
491 nodeid = (limit & 0xf) + ((base >> 4) & 0x30);
493 reg_link = (limit >> 4) & 7;
494 reg_dev = __f0_dev[nodeid];
496 /* Reserve the resource */
497 struct resource *res;
499 new_resource(reg_dev,
500 IOINDEX(0x1000 + reg,
508 /* FIXME: do we need to check extend conf space?
509 I don't believe that much preset value */
511 #if CONFIG_PCI_64BIT_PREF_MEM == 0
512 pci_domain_read_resources(dev);
515 struct resource *resource;
516 for (link = dev->link_list; link; link = link->next) {
517 /* Initialize the system wide io space constraints */
518 resource = new_resource(dev, 0 | (link->link_num << 2));
519 resource->base = 0x400;
520 resource->limit = 0xffffUL;
521 resource->flags = IORESOURCE_IO;
523 /* Initialize the system wide prefetchable memory resources constraints */
524 resource = new_resource(dev, 1 | (link->link_num << 2));
525 resource->limit = 0xfcffffffffULL;
526 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
528 /* Initialize the system wide memory resources constraints */
529 resource = new_resource(dev, 2 | (link->link_num << 2));
530 resource->limit = 0xfcffffffffULL;
531 resource->flags = IORESOURCE_MEM;
536 static void domain_set_resources(device_t dev)
538 printk(BIOS_DEBUG, "\nFam14h - domain_set_resources.\n");
539 printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev);
541 #if CONFIG_PCI_64BIT_PREF_MEM == 1
542 struct resource *io, *mem1, *mem2;
543 struct resource *res;
545 unsigned long mmio_basek;
549 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
550 struct hw_mem_hole_info mem_hole;
551 u32 reset_memhole = 1;
554 #if CONFIG_PCI_64BIT_PREF_MEM == 1
556 printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
557 for (link = dev->link_list; link; link = link->next) {
558 /* Now reallocate the pci resources memory with the
559 * highest addresses I can manage.
561 mem1 = find_resource(dev, 1 | (link->link_num << 2));
562 mem2 = find_resource(dev, 2 | (link->link_num << 2));
565 "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
566 (u32) (mem1->base), (u32) (mem1->limit),
567 (u32) (mem1->size), u32) (mem1->align));
569 "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
570 (u32) (mem2->base), (u32) (mem2->limit),
571 (u32) (mem2->size), (u32) (mem2->align));
573 /* See if both resources have roughly the same limits */
574 if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff))
575 || ((mem1->limit > 0xffffffff)
576 && (mem2->limit > 0xffffffff))) {
577 /* If so place the one with the most stringent alignment first
579 if (mem2->align > mem1->align) {
580 struct resource *tmp;
585 /* Now place the memory as high up as it will go */
586 mem2->base = resource_max(mem2);
587 mem1->limit = mem2->base - 1;
588 mem1->base = resource_max(mem1);
590 /* Place the resources as high up as they will go */
591 mem2->base = resource_max(mem2);
592 mem1->base = resource_max(mem1);
596 "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
597 mem1->base, mem1->limit, mem1->size, mem1->align);
599 "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
600 mem2->base, mem2->limit, mem2->size, mem2->align);
603 for (res = &dev->resource_list; res; res = res->next) {
604 res->flags |= IORESOURCE_ASSIGNED;
605 res->flags |= IORESOURCE_STORED;
606 report_resource_stored(dev, res, "");
610 pci_tolm = 0xffffffffUL;
611 for (link = dev->link_list; link; link = link->next) {
612 pci_tolm = my_find_pci_tolm(link, pci_tolm);
615 // FIXME handle interleaved nodes. If you fix this here, please fix
617 mmio_basek = pci_tolm >> 10;
618 /* Round mmio_basek to something the processor can support */
619 mmio_basek &= ~((1 << 6) - 1);
621 // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
622 // MMIO hole. If you fix this here, please fix amdk8, too.
623 /* Round the mmio hole to 64M */
624 mmio_basek &= ~((64 * 1024) - 1);
626 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
627 /* if the hw mem hole is already set in raminit stage, here we will compare
628 * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
629 * use hole_basek as mmio_basek and we don't need to reset hole.
630 * otherwise We reset the hole to the mmio_basek
633 mem_hole = get_hw_mem_hole_info();
635 // Use hole_basek as mmio_basek, and we don't need to reset hole anymore
636 if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) {
637 mmio_basek = mem_hole.hole_startk;
644 struct dram_base_mask_t d;
645 resource_t basek, limitk, sizek; // 4 1T
647 d = get_dram_base_mask(0);
650 basek = ((resource_t) ((u64) d.base)) << 8;
651 limitk = (resource_t) (((u64) d.mask << 8) | 0xFFFFFF);
653 "adsr: (before) basek = %llx, limitk = %llx.\n", basek,
656 /* Convert these values to multiples of 1K for ease of math. */
659 sizek = limitk - basek + 1;
662 "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",
663 basek, limitk, sizek);
665 /* see if we need a hole from 0xa0000 to 0xbffff */
666 if ((basek < 640) && (sizek > 768)) {
667 printk(BIOS_DEBUG,"adsr - 0xa0000 to 0xbffff resource.\n");
668 ram_resource(dev, (idx | 0), basek, 640 - basek);
671 sizek = limitk - 768;
675 "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
676 mmio_basek, basek, limitk);
678 /* split the region to accomodate pci memory space */
679 if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) {
680 if (basek <= mmio_basek) {
682 pre_sizek = mmio_basek - basek;
684 ram_resource(dev, idx, basek,
688 #if CONFIG_WRITE_HIGH_TABLES==1
689 if (high_tables_base == 0) {
690 /* Leave some space for ACPI, PIRQ and MP tables */
691 #if CONFIG_GFXUMA == 1
692 high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
694 high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
696 high_tables_size = HIGH_MEMORY_SIZE;
697 printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
698 (u32)(high_tables_size / 1024), high_tables_base);
705 if ((basek + sizek) <= 4 * 1024 * 1024) {
708 basek = 4 * 1024 * 1024;
709 sizek -= (4 * 1024 * 1024 - mmio_basek);
713 ram_resource(dev, (idx | 0), basek, sizek);
715 #if CONFIG_WRITE_HIGH_TABLES==1
717 "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0,
718 mmio_basek, basek, limitk);
719 if (high_tables_base == 0) {
720 /* Leave some space for ACPI, PIRQ and MP tables */
721 #if CONFIG_GFXUMA == 1
722 high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
723 printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base);
725 high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
727 high_tables_size = HIGH_MEMORY_SIZE;
731 printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
732 printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",
735 #if CONFIG_GFXUMA == 1
736 printk(BIOS_DEBUG, "adsr - adding uma resource.\n");
737 add_uma_resource(dev, 7);
740 for (link = dev->link_list; link; link = link->next) {
741 if (link->children) {
742 assign_resources(link);
745 printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n");
748 static void domain_enable_resources(device_t dev) {
751 #if CONFIG_AMD_SB_CIMX
756 /* Must be called after PCI enumeration and resource allocation */
757 printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n");
758 val = agesawrapper_amdinitmid();
760 printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
763 printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
766 /* Bus related code */
768 static void cpu_bus_read_resources(device_t dev) {
769 printk(BIOS_DEBUG, "\nFam14h - cpu_bus_read_resources.\n");
771 #if CONFIG_MMCONF_SUPPORT
772 struct resource *resource = new_resource(dev, 0xc0010058);
773 resource->base = CONFIG_MMCONF_BASE_ADDRESS;
774 resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
775 resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
776 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
780 static void cpu_bus_set_resources(device_t dev) {
781 struct resource *resource = find_resource(dev, 0xc0010058);
783 printk(BIOS_DEBUG, "\nFam14h - cpu_bus_set_resources.\n");
786 report_resource_stored(dev, resource, " <mmconfig>");
788 pci_dev_set_resources(dev);
791 static void cpu_bus_init(device_t dev) {
792 struct device_path cpu_path;
796 initialize_cpus(dev->link_list);
798 /* Build the AP cpu device path(s) */
799 for (apic_id = 1; apic_id < CONFIG_MAX_CPUS; apic_id++) {
800 cpu_path.type = DEVICE_PATH_APIC;
801 cpu_path.apic.apic_id = apic_id;
802 cpu = alloc_dev(dev->link_list, &cpu_path);
806 cpu->path.apic.node_id = 0;
807 cpu->path.apic.core_id = apic_id;
811 /* North Bridge Structures */
813 static struct device_operations northbridge_operations = {
814 .read_resources = read_resources,
815 .set_resources = set_resources,
816 .enable_resources = pci_dev_enable_resources,
817 .init = northbridge_init,
818 .enable = 0,.ops_pci = 0,
821 static const struct pci_driver northbridge_driver __pci_driver = {
822 .ops = &northbridge_operations,
823 .vendor = PCI_VENDOR_ID_AMD,
827 struct chip_operations northbridge_amd_agesa_family14_ops = {
828 CHIP_NAME("AMD Family 14h Northbridge")
832 /* Root Complex Structures */
834 static struct device_operations pci_domain_ops = {
835 .read_resources = domain_read_resources,
836 .set_resources = domain_set_resources,
837 .enable_resources = domain_enable_resources,
839 .scan_bus = pci_domain_scan_bus,
842 static struct device_operations cpu_bus_ops = {
843 .read_resources = cpu_bus_read_resources,
844 .set_resources = cpu_bus_set_resources,
845 .enable_resources = NULL,
846 .init = cpu_bus_init,
850 static void root_complex_enable_dev(struct device *dev) {
851 /* Set the operations if it is a special bus type */
852 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
853 dev->ops = &pci_domain_ops;
854 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
855 dev->ops = &cpu_bus_ops;
859 struct chip_operations northbridge_amd_agesa_family14_root_complex_ops = {
860 CHIP_NAME("AMD Family 14h Root Complex")
861 .enable_dev = root_complex_enable_dev,