2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2010 Nils Jacobs
6 ## This program is free software; you can redistribute it and/or
7 ## modify it under the terms of the GNU General Public License as
8 ## published by the Free Software Foundation; version 2 of
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 chip northbridge/amd/gx2
23 register "irqmap" = "0xaa5b"
25 device lapic_cluster 0 on
26 chip cpu/amd/model_gx2
30 device pci_domain 0 on
31 subsystemid 102d 0 inherit
34 chip southbridge/amd/cs5536
35 register "enable_gpio_int_route" = "0x0D0C0700"
36 register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
37 register "enable_USBP4_device" = "0" #0: host, 1:device
38 register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
39 register "com1_enable" = "1"
40 register "com1_address" = "0x3F8"
41 register "com1_irq" = "4"
42 register "com2_enable" = "0"
43 register "com2_address" = "0x2F8"
44 register "com2_irq" = "3"
45 device pci e.0 on end # Realtek 8139 LAN
46 device pci f.0 on end # ISA Bridge
47 device pci f.2 on end # IDE Controller
48 device pci f.3 on end # Audio
49 device pci f.4 on end # OHCI
50 device pci f.5 on end # EHCI