2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 #include <device/pci_def.h>
24 #include <device/pci_ids.h>
26 #include <device/pnp_def.h>
27 #include <arch/romcc_io.h>
29 #include <console/console.h>
31 #include "northbridge/via/cx700/raminit.h"
32 #include "cpu/x86/bist.h"
35 #include "pc80/udelay_io.c"
36 #include "lib/delay.c"
37 #include "northbridge/via/cx700/cx700_early_smbus.c"
38 #include "lib/debug.c"
40 #include "northbridge/via/cx700/cx700_early_serial.c"
41 #include "northbridge/via/cx700/raminit.c"
44 static void enable_mainboard_devices(void)
48 dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0);
49 if (dev == PCI_DEV_INVALID) {
50 die("LPC bridge not found!!!\n");
53 pci_write_config8(dev, 0x98, 0x00);
56 pci_write_config8(dev, 0x50, 0x80);
58 // Disable internal KBC Configuration
59 pci_write_config8(dev, 0x51, 0x2d);
60 pci_write_config8(dev, 0x58, 0x42);
61 pci_write_config8(dev, 0x59, 0x80);
62 pci_write_config8(dev, 0x5b, 0x01);
64 // Enable P2P Bridge Header for External PCI BUS.
65 dev = pci_locate_device(PCI_ID(0x1106, 0x324e), 0);
66 if (dev == PCI_DEV_INVALID) {
67 die("P2P bridge not found!!!\n");
69 pci_write_config8(dev, 0x4f, 0x41);
71 // Switch SATA to non-RAID mode
72 dev = pci_locate_device(PCI_ID(0x1106, 0x0581), 0);
73 if (dev != PCI_DEV_INVALID) {
74 pci_write_config16(dev, 0xBA, 0x5324);
78 static void enable_shadow_ram(const struct mem_controller *ctrl)
82 pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a);
84 /* 0xf0000-0xfffff - ACPI tables */
85 shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
87 pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
90 void main(unsigned long bist)
92 /* Set statically so it should work with cx700 as well */
93 static const struct mem_controller cx700[] = {
95 .channel0 = {DIMM0, DIMM1},
101 enable_cx700_serial();
105 /* Halt if there was a built in self test failure */
106 report_bist_failure(bist);
108 enable_mainboard_devices();
110 /* Allows access to all northbridge devices */
111 pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
113 sdram_set_registers(cx700);
114 enable_shadow_ram(cx700);