2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <arch/smp/mpspec.h>
25 #include <arch/ioapic.h>
26 #include <cpu/x86/lapic.h>
27 #include <console/console.h>
31 static void *smp_write_config_table(void *v)
33 static const char sig[4] = MPC_SIGNATURE;
34 static const char oem[8] = "COREBOOT";
35 static const char productid[12] = "VIA VT8454C ";
36 struct mp_config_table *mc;
39 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
40 memset(mc, 0, sizeof(*mc));
42 memcpy(mc->mpc_signature, sig, sizeof(sig));
43 mc->mpc_length = sizeof(*mc); /* initially just the header */
45 mc->mpc_checksum = 0; /* not yet computed */
46 memcpy(mc->mpc_oem, oem, sizeof(oem));
47 memcpy(mc->mpc_productid, productid, sizeof(productid));
50 mc->mpc_entry_count = 0; /* No entries yet... */
51 mc->mpc_lapic = LAPIC_ADDR;
56 smp_write_processors(mc);
57 mptable_write_buses(mc, NULL, &isa_bus);
59 /* I/O APICs: APIC ID Version State Address */
60 smp_write_ioapic(mc, 2, 17, IO_APIC_ADDR);
62 mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
64 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
65 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x14);
66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x16);
67 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x2, 0x15);
68 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x43, 0x2, 0x17);
69 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x80, 0x4, 0x2, 0x11);
70 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x11);
71 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x2, 0x10, 0x2, 0x11);
73 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
74 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
75 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
77 /* Compute the checksums */
78 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
79 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
80 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
81 return smp_next_mpe_entry(mc);
84 unsigned long write_smp_table(unsigned long addr)
87 v = smp_write_floating_table(addr);
88 return (unsigned long)smp_write_config_table(v);