2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
8 * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #include <console/console.h>
26 #include <arch/smp/mpspec.h>
27 #include <device/pci.h>
30 #include <../../../southbridge/via/vt8237r/vt8237r.h>
35 void *smp_write_config_table(void *v)
37 static const char sig[4] = "PCMP";
38 static const char oem[8] = "VIA ";
39 static const char productid[12] = "PC2500 ";
40 struct mp_config_table *mc;
45 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
46 memset(mc, 0, sizeof(*mc));
48 memcpy(mc->mpc_signature, sig, sizeof(sig));
49 mc->mpc_length = sizeof(*mc); /* initially just the header */
51 mc->mpc_checksum = 0; /* not yet computed */
52 memcpy(mc->mpc_oem, oem, sizeof(oem));
53 memcpy(mc->mpc_productid, productid, sizeof(productid));
56 mc->mpc_entry_count = 0; /* No entries yet... */
57 mc->mpc_lapic = LAPIC_ADDR;
62 smp_write_processors(mc);
66 /* define numbers for pci and isa bus */
67 for (bus_num = 0; bus_num < bus_isa; bus_num++) {
68 smp_write_bus(mc, bus_num, "PCI ");
70 smp_write_bus(mc, bus_isa, "ISA ");
73 /* I/O APICs: APIC ID Version State Address*/
74 smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VT8237R_APIC_BASE);
76 /* Now, assemble the table. */
78 smp_write_intsrc(mc, mp_ExtINT,
79 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
80 bus_isa, 0x0, VT8237R_APIC_ID, 0x0);
82 #define ISA_INT(intr, pin) \
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, \
84 bus_isa, (intr), VT8237R_APIC_ID, (pin))
101 #define PCI_INT(bus, dev, fn, pin) \
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \
103 bus, (((dev)<<2)|(fn)), VT8237R_APIC_ID, (pin))
106 PCI_INT(0, 8, 0, 16);
107 PCI_INT(0, 8, 1, 17);
108 PCI_INT(0, 8, 2, 18);
109 PCI_INT(0, 8, 3, 19);
112 PCI_INT(0, 9, 0, 17);
113 PCI_INT(0, 9, 1, 18);
114 PCI_INT(0, 9, 2, 19);
115 PCI_INT(0, 9, 3, 16);
118 PCI_INT(0, 15, 1, 20);
121 PCI_INT(0, 16, 0, 21);
122 PCI_INT(0, 16, 1, 21);
123 PCI_INT(0, 16, 2, 21);
124 PCI_INT(0, 16, 3, 21);
127 PCI_INT(0, 17, 2, 22);
130 PCI_INT(0, 18, 0, 23);
133 PCI_INT(1, 0, 0, 16);
135 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
136 smp_write_lintsrc(mc, mp_ExtINT,
137 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
138 0, 0x0, MP_APIC_ALL, 0x0);
139 smp_write_lintsrc(mc, mp_NMI,
140 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
141 0, 0x0, MP_APIC_ALL, 0x1);
143 /* There is no extension information... */
145 /* Compute the checksums */
147 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
148 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
149 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
150 mc, smp_next_mpe_entry(mc));
151 return smp_next_mpe_entry(mc);
154 unsigned long write_smp_table(unsigned long addr)
157 v = smp_write_floating_table(addr);
158 return (unsigned long)smp_write_config_table(v);