1 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
3 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
4 uses CONFIG_CONSOLE_SERIAL8250
8 uses CONFIG_HAVE_MP_TABLE
9 uses CONFIG_HAVE_PIRQ_TABLE
10 uses CONFIG_USE_FALLBACK_IMAGE
11 uses CONFIG_HAVE_FALLBACK_BOOT
12 uses CONFIG_HAVE_HARD_RESET
14 uses CONFIG_UDELAY_TSC
15 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
16 uses CONFIG_HAVE_OPTION_TABLE
17 uses CONFIG_USE_OPTION_TABLE
18 uses CONFIG_ROM_PAYLOAD
19 uses CONFIG_IRQ_SLOT_COUNT
21 uses CONFIG_MAINBOARD_VENDOR
22 uses CONFIG_MAINBOARD_PART_NUMBER
23 uses COREBOOT_EXTRA_VERSION
25 uses CONFIG_FALLBACK_SIZE
26 uses CONFIG_STACK_SIZE
29 uses CONFIG_ROM_SECTION_SIZE
30 uses CONFIG_ROM_IMAGE_SIZE
31 uses CONFIG_ROM_SECTION_SIZE
32 uses CONFIG_ROM_SECTION_OFFSET
33 uses CONFIG_ROM_PAYLOAD_START
34 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
35 uses CONFIG_PRECOMPRESSED_PAYLOAD
36 uses CONFIG_PAYLOAD_SIZE
39 uses CONFIG_XIP_ROM_SIZE
40 uses CONFIG_XIP_ROM_BASE
41 uses CONFIG_HAVE_MP_TABLE
42 uses CONFIG_CROSS_COMPILE
48 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
49 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
52 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
53 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
55 default CONFIG_CONSOLE_SERIAL8250=1
56 ## Select the serial console baud rate
57 default CONFIG_TTYS0_BAUD=115200
59 # Select the serial console base port
60 default CONFIG_TTYS0_BASE=0x3f8
62 # Select the serial protocol
63 # This defaults to 8 data bits, 1 stop bit, and no parity
64 default CONFIG_TTYS0_LCS=0x3
66 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
67 default CONFIG_ROM_SIZE = 256*1024
74 ## Build code for the fallback boot
76 default CONFIG_HAVE_FALLBACK_BOOT=1
81 default CONFIG_HAVE_MP_TABLE=0
84 ## Build code to reset the motherboard from coreboot
86 default CONFIG_HAVE_HARD_RESET=0
89 ## use io based udelay function
90 ## disable IO and enable TSC on Nehemiah boards
92 default CONFIG_UDELAY_IO=1
93 default CONFIG_UDELAY_TSC=0
94 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
97 ## Build code to export a programmable irq routing table
99 default CONFIG_HAVE_PIRQ_TABLE=1
100 default CONFIG_IRQ_SLOT_COUNT=5
104 ## Build code to export a CMOS option table
106 default CONFIG_HAVE_OPTION_TABLE=1
109 ### coreboot layout values
112 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
113 default CONFIG_ROM_IMAGE_SIZE = 65536
114 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
117 ## Use a small 8K stack
119 default CONFIG_STACK_SIZE=0x2000
122 ## Use a small 16K heap
124 default CONFIG_HEAP_SIZE=0x4000
127 ## Only use the option table in a normal image
129 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
130 default CONFIG_USE_OPTION_TABLE = 0
132 default CONFIG_RAMBASE = 0x00004000
134 default CONFIG_ROM_PAYLOAD = 1
137 ## The default compiler
139 default CONFIG_CROSS_COMPILE=""
140 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
149 default CONFIG_CBFS=1