1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
6 ## Set all of the defaults for an x86 architecture
12 ## Build the objects we have code for in this directory.
16 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
22 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
23 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
26 makerule ./failover.inc
27 depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
28 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
32 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
33 action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
36 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
37 action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
41 ## Build our 16 bit and 32 bit coreboot entry code
43 mainboardinit cpu/x86/16bit/entry16.inc
44 mainboardinit cpu/x86/32bit/entry32.inc
45 ldscript /cpu/x86/16bit/entry16.lds
46 ldscript /cpu/x86/32bit/entry32.lds
49 ## Build our reset vector (This is where coreboot is entered)
51 if CONFIG_USE_FALLBACK_IMAGE
52 mainboardinit cpu/x86/16bit/reset16.inc
53 ldscript /cpu/x86/16bit/reset16.lds
55 mainboardinit cpu/x86/32bit/reset32.inc
56 ldscript /cpu/x86/32bit/reset32.lds
59 ### Should this be in the northbridge code?
60 mainboardinit arch/i386/lib/cpu_reset.inc
63 ## Include an id string (For safe flashing)
65 mainboardinit arch/i386/lib/id.inc
66 ldscript /arch/i386/lib/id.lds
69 ### This is the early phase of coreboot startup
70 ### Things are delicate and we test to see if we should
71 ### failover to another image.
73 if CONFIG_USE_FALLBACK_IMAGE
74 ldscript /arch/i386/lib/failover.lds
75 mainboardinit ./failover.inc
79 ### O.k. We aren't just an intermediary anymore!
85 mainboardinit cpu/x86/fpu_enable.inc
86 mainboardinit ./auto.inc
87 mainboardinit cpu/x86/mmx_disable.inc
90 ## Include the secondary Configuration files
95 chip northbridge/via/vt8601
96 device pci_domain 0 on
97 device pci 0.0 on end # Northbridge
98 # device pci 0.1 on # AGP bridge
99 # device pci 0.0 on end # Integrated VGA
101 chip southbridge/via/vt8231
102 register "enable_native_ide" = "0"
103 register "enable_com_ports" = "1"
104 register "enable_keyboard" = "0"
105 device pci 11.0 on # Southbrdge
106 chip superio/winbond/w83627hf
107 device pnp 2e.0 on # Floppy
112 device pnp 2e.1 off # Parallel Port
116 device pnp 2e.2 on # Com1
120 device pnp 2e.3 off # Com2
124 device pnp 2e.5 on # Keyboard
130 register "com1" = "{CONFIG_TTYS0_BAUD}"
132 device pnp 2e.6 off end # CIR
133 device pnp 2e.7 off end # GAME_MIDI_GIPO1
134 device pnp 2e.8 off end # GPIO2
135 device pnp 2e.9 off end # GPIO3
136 device pnp 2e.a off end # ACPI
137 device pnp 2e.b on # HW Monitor
141 device pci 11.1 on end # Ide
142 device pci 11.2 off end # Usb port 0-1
143 device pci 11.3 off end # Usb port 2-3
144 device pci 11.4 off end # ACPI
145 device pci 11.5 off end # AC97 Audio
146 device pci 11.6 on end # AC97 Modem
147 device pci 12.0 on end # Ethernet
151 device apic_cluster 0 on
152 chip cpu/via/model_c3