2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 VIA Technologies, Inc.
5 * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <device/pci_def.h>
24 #include <device/pci_ids.h>
26 #include <device/pnp_def.h>
27 #include <arch/romcc_io.h>
29 #include <console/console.h>
30 #include "lib/ramtest.c"
31 #include "northbridge/via/cn400/raminit.h"
32 #include "cpu/x86/mtrr/earlymtrr.c"
33 #include "cpu/x86/bist.h"
34 #include "pc80/udelay_io.c"
35 #include "lib/delay.c"
36 #include "cpu/x86/lapic/boot_cpu.c"
37 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
38 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
41 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
43 static const struct mem_controller ctrl = {
50 .channel0 = { DIMM0 },
53 static inline int spd_read_byte(unsigned device, unsigned address)
55 return smbus_read_byte(device, address);
58 #include "northbridge/via/cn400/raminit.c"
60 static void enable_mainboard_devices(void)
65 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
66 if (dev == PCI_DEV_INVALID)
67 die("Southbridge not found!!!\n");
69 /* bit=0 means enable function (per VT8237R datasheet)
74 * 3 15.0 SATA and PATA
78 pci_write_config8(dev, 0x50, 0xC0);
80 /*bit=0 means enable internal function (per VT8237R datasheet)
82 *bit=1 means enable internal function (per VT8237R datasheet)
84 * 5 LAN Controller Clock Gating
87 * 2 Internal PS2 Mouse
88 * 1 Internal KBC Configuration
89 * 0 Internal Keyboard Controller
91 pci_write_config8(dev, 0x51, 0x9d);
94 static void enable_shadow_ram(void)
96 unsigned char shadowreg;
98 shadowreg = pci_read_config8(ctrl.d0f3, 0x82);
99 /* 0xf0000-0xfffff Read/Write*/
101 pci_write_config8(ctrl.d0f3, 0x82, shadowreg);
104 static void main(unsigned long bist)
109 /* Enable multifunction for northbridge. */
110 pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
112 w83697hf_set_clksel_48(SERIAL_DEV);
114 w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
119 print_spew("In romstage.c:main()\n");
124 /* Halt if there was a built-in self test failure. */
125 report_bist_failure(bist);
127 print_debug("Enabling mainboard devices\n");
128 enable_mainboard_devices();
130 print_debug("Enable F-ROM Shadow RAM\n");
134 print_debug("Setup CPU Interface\n");
135 c3_cpu_setup(ctrl.d0f2);
140 print_debug("doing early_mtrr\n");
144 //ram_check(0, 640 * 1024);
146 print_spew("Leaving romstage.c:main()\n");