1 /* generated by MPTable, version 2.0.15*/
2 /* as modified by RGM for coreboot */
3 #include <console/console.h>
4 #include <arch/smp/mpspec.h>
5 #include <device/pci.h>
9 void *smp_write_config_table(void *v)
11 static const char sig[4] = "PCMP";
12 static const char oem[8] = "LNXI ";
13 static const char productid[12] = "P4DPE ";
14 struct mp_config_table *mc;
16 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
17 memset(mc, 0, sizeof(*mc));
19 memcpy(mc->mpc_signature, sig, sizeof(sig));
20 mc->mpc_length = sizeof(*mc); /* initially just the header */
22 mc->mpc_checksum = 0; /* not yet computed */
23 memcpy(mc->mpc_oem, oem, sizeof(oem));
24 memcpy(mc->mpc_productid, productid, sizeof(productid));
27 mc->mpc_entry_count = 0; /* No entries yet... */
28 mc->mpc_lapic = LAPIC_ADDR;
33 smp_write_processors(mc);
37 smp_write_bus(mc, 0, "PCI ");
38 smp_write_bus(mc, 1, "PCI ");
39 smp_write_bus(mc, 2, "ISA ");
40 /*I/O APICs: APIC ID Version State Address*/
41 smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
45 dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
47 res = find_resource(dev, PCI_BASE_ADDRESS_0);
49 smp_write_ioapic(mc, 3, 0x20, res->base);
52 dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
54 res = find_resource(dev, PCI_BASE_ADDRESS_0);
56 smp_write_ioapic(mc, 4, 0x20, res->base);
59 dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));
61 res = find_resource(dev, PCI_BASE_ADDRESS_0);
63 smp_write_ioapic(mc, 5, 0x20, res->base);
66 dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));
68 res = find_resource(dev, PCI_BASE_ADDRESS_0);
70 smp_write_ioapic(mc, 8, 0x20, res->base);
74 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
75 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15);
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15);
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15);
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15);
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x2, 0x15);
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x46, 0x2, 0x16);
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x2, 0x17);
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x2, 0x14);
84 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x0, 0x2, 0x0);
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x1, 0x2, 0x1);
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x0, 0x2, 0x2);
87 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x3, 0x2, 0x3);
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x4, 0x2, 0x4);
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x5, 0x2, 0x5);
90 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x6, 0x2, 0x6);
91 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x7, 0x2, 0x7);
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x2, 0x8, 0x2, 0x8);
93 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x9, 0x2, 0x9);
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xd, 0x2, 0xd);
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xe, 0x2, 0xe);
96 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xf, 0x2, 0xf);
97 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
98 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
99 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
100 /* There is no extension information... */
102 /* Compute the checksums */
103 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
104 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
105 printk_debug("Wrote the mp table end at: %p - %p\n",
106 mc, smp_next_mpe_entry(mc));
107 return smp_next_mpe_entry(mc);
110 unsigned long write_smp_table(unsigned long addr)
113 v = smp_write_floating_table(addr);
114 return (unsigned long)smp_write_config_table(v);