1 /* generated by MPTable, version 2.0.15*/
2 /* as modified by RGM for coreboot */
3 #include <console/console.h>
4 #include <arch/smp/mpspec.h>
5 #include <arch/ioapic.h>
6 #include <device/pci.h>
10 static void *smp_write_config_table(void *v)
12 struct mp_config_table *mc;
15 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
17 mptable_init(mc, LAPIC_ADDR);
19 smp_write_processors(mc);
20 mptable_write_buses(mc, NULL, &isa_bus);
22 /*I/O APICs: APIC ID Version State Address*/
23 smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
25 mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
27 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
28 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15);
29 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15);
30 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15);
31 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15);
32 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x2, 0x15);
33 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x46, 0x2, 0x16);
34 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
35 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x2, 0x17);
36 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x2, 0x14);
37 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
38 mptable_lintsrc(mc, 0x0);
39 /* There is no extension information... */
41 /* Compute the checksums */
42 return mptable_finalize(mc);
45 unsigned long write_smp_table(unsigned long addr)
48 v = smp_write_floating_table(addr, 0);
49 return (unsigned long)smp_write_config_table(v);