2 #include <device/pci_def.h>
3 #include <device/pci_ids.h>
5 #include <device/pnp_def.h>
6 #include <arch/romcc_io.h>
9 #include <console/console.h>
10 #include "lib/ramtest.c"
11 #include "northbridge/via/vt8623/raminit.h"
12 #include "cpu/x86/mtrr/earlymtrr.c"
13 #include "cpu/x86/bist.h"
14 #include "pc80/udelay_io.c"
15 #include "lib/delay.c"
16 #include "cpu/x86/lapic/boot_cpu.c"
17 #include "lib/debug.c"
18 #include "southbridge/via/vt8235/vt8235_early_smbus.c"
19 #include "southbridge/via/vt8235/vt8235_early_serial.c"
21 static inline int spd_read_byte(unsigned device, unsigned address)
23 return smbus_read_byte(device, address);
26 #include "northbridge/via/vt8623/raminit.c"
28 static void enable_mainboard_devices(void)
32 dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
33 PCI_DEVICE_ID_VIA_8235), 0);
35 if (dev == PCI_DEV_INVALID) {
36 die("Southbridge not found!!!\n");
38 pci_write_config8(dev, 0x50, 0x80);
39 pci_write_config8(dev, 0x51, 0x1f);
41 // This early setup switches IDE into compatibility mode before PCI gets
42 // a chance to assign I/Os
43 // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
46 // PCI_WRITE_CONFIG_BYTE
48 /* we do this here as in V2, we can not yet do raw operations
51 dev += 0x100; /* ICKY */
53 pci_write_config8(dev, 0x04, 7);
54 pci_write_config8(dev, 0x40, 3);
55 pci_write_config8(dev, 0x42, 0);
56 pci_write_config8(dev, 0x3c, 0xe);
57 pci_write_config8(dev, 0x3d, 0);
60 static void enable_shadow_ram(void)
62 device_t dev = 0; /* no need to look up 0:0.0 */
63 unsigned char shadowreg;
64 /* dev 0 for southbridge */
65 shadowreg = pci_read_config8(dev, 0x63);
68 pci_write_config8(dev, 0x63, shadowreg);
71 static void main(unsigned long bist)
76 * Enable VGA; 32MB buffer.
78 pci_write_config8(0, 0xe1, 0xdd);
81 * Disable the firewire stuff, which apparently steps on IO 0+ on
84 dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
85 PCI_DEVICE_ID_VIA_6305), 0);
86 if (dev != PCI_DEV_INVALID) {
87 pci_write_config8(dev, 0x15, 0x1c);
90 enable_vt8235_serial();
96 /* Halt if there was a built in self test failure */
97 report_bist_failure(bist);
103 print_debug(" Enabling mainboard devices\n");
104 enable_mainboard_devices();
106 print_debug(" Enabling shadow ram\n");
109 ddr_ram_setup((const struct mem_controller *)0);
111 /* Check all of memory */
113 static const struct {
114 unsigned long lo, hi;
116 /* Check 16MB of memory @ 0*/
117 { 0x00000000, 0x01000000 },
120 for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
121 ram_check(check_addrs[i].lo, check_addrs[i].hi);
126 print_debug(" Doing MTRR init.\n");
130 //dump_pci_devices();
132 print_spew("Leaving romstage.c:main()\n");