src/mainboard/via/epia-m/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <device/pci_ids.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <arch/hlt.h>
   8 #include <stdlib.h>
   9 #include "pc80/serial.c"
  10 #include "console/console.c"
  11 #include "lib/ramtest.c"
  12 #include "northbridge/via/vt8623/raminit.h"
  13 #include "cpu/x86/mtrr/earlymtrr.c"
  14 #include "cpu/x86/bist.h"
  15 #include "pc80/udelay_io.c"
  16 #include "lib/delay.c"
  17 #include "cpu/x86/lapic/boot_cpu.c"
  18 #include "lib/debug.c"
  19 #include "southbridge/via/vt8235/vt8235_early_smbus.c"
  20 #include "southbridge/via/vt8235/vt8235_early_serial.c"
  21
  22 static inline int spd_read_byte(unsigned device, unsigned address)
  23 {
  24         return smbus_read_byte(device, address);
  25 }
  26
  27 #include "northbridge/via/vt8623/raminit.c"
  28
  29 static void enable_mainboard_devices(void)
  30 {
  31         device_t dev;
  32
  33         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
  34                                 PCI_DEVICE_ID_VIA_8235), 0);
  35
  36         if (dev == PCI_DEV_INVALID) {
  37                 die("Southbridge not found!!!\n");
  38         }
  39         pci_write_config8(dev, 0x50, 0x80);
  40         pci_write_config8(dev, 0x51, 0x1f);
  41 #if 0
  42         // This early setup switches IDE into compatibility mode before PCI gets
  43         // a chance to assign I/Os
  44         // movl    $CONFIG_ADDR(0, 0x89, 0x42), %eax
  45         // //      movb    $0x09, %dl
  46         // movb    $0x00, %dl
  47         // PCI_WRITE_CONFIG_BYTE
  48 #endif
  49         /* we do this here as in V2, we can not yet do raw operations
  50          * to pci!
  51          */
  52         dev += 0x100; /* ICKY */
  53
  54         pci_write_config8(dev, 0x04, 7);
  55         pci_write_config8(dev, 0x40, 3);
  56         pci_write_config8(dev, 0x42, 0);
  57         pci_write_config8(dev, 0x3c, 0xe);
  58         pci_write_config8(dev, 0x3d, 0);
  59 }
  60
  61 static void enable_shadow_ram(void)
  62 {
  63         device_t dev = 0; /* no need to look up 0:0.0 */
  64         unsigned char shadowreg;
  65         /* dev 0 for southbridge */
  66         shadowreg = pci_read_config8(dev, 0x63);
  67         /* 0xf0000-0xfffff */
  68         shadowreg |= 0x30;
  69         pci_write_config8(dev, 0x63, shadowreg);
  70 }
  71
  72 static void main(unsigned long bist)
  73 {
  74         device_t dev;
  75
  76         /*
  77          * Enable VGA; 32MB buffer.
  78          */
  79         pci_write_config8(0, 0xe1, 0xdd);
  80
  81         /*
  82          * Disable the firewire stuff, which apparently steps on IO 0+ on
  83          * reset. Doh!
  84          */
  85         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
  86                                 PCI_DEVICE_ID_VIA_6305), 0);
  87         if (dev != PCI_DEV_INVALID) {
  88                 pci_write_config8(dev, 0x15, 0x1c);
  89         }
  90
  91         enable_vt8235_serial();
  92         uart_init();
  93         console_init();
  94
  95         enable_smbus();
  96
  97         /* Halt if there was a built in self test failure */
  98         report_bist_failure(bist);
  99
 100         // init_timer();
 101
 102         post_code(0x05);
 103
 104         print_debug(" Enabling mainboard devices\n");
 105         enable_mainboard_devices();
 106
 107         print_debug(" Enabling shadow ram\n");
 108         enable_shadow_ram();
 109
 110         ddr_ram_setup((const struct mem_controller *)0);
 111
 112         /* Check all of memory */
 113 #if 0
 114         static const struct {
 115                 unsigned long lo, hi;
 116         } check_addrs[] = {
 117                 /* Check 16MB of memory @ 0*/
 118                 { 0x00000000, 0x01000000 },
 119         };
 120         int i;
 121         for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
 122                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
 123         }
 124 #endif
 125
 126         if (bist == 0) {
 127                 print_debug(" Doing MTRR init.\n");
 128                 early_mtrr_init();
 129         }
 130
 131         //dump_pci_devices();
 132
 133         print_spew("Leaving romstage.c:main()\n");
 134 }
 135