src/mainboard/via/epia-m/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <device/pci_ids.h>
   6 #if 0
   7 #include <cpu/x86/lapic.h>
   8 #endif
   9 #include <arch/io.h>
  10 #include <device/pnp_def.h>
  11 #include <arch/romcc_io.h>
  12 #include <arch/hlt.h>
  13 #include <stdlib.h>
  14 #include "pc80/serial.c"
  15 #include "arch/i386/lib/console.c"
  16 #include "lib/ramtest.c"
  17 #include "northbridge/via/vt8623/raminit.h"
  18 #include "cpu/x86/mtrr/earlymtrr.c"
  19 #include "cpu/x86/bist.h"
  20
  21 /*
  22  */
  23 void udelay(int usecs)
  24 {
  25         int i;
  26         for(i = 0; i < usecs; i++)
  27                 outb(i&0xff, 0x80);
  28 }
  29
  30 #include "lib/delay.c"
  31 #include "cpu/x86/lapic/boot_cpu.c"
  32 #include "lib/debug.c"
  33
  34 #include "southbridge/via/vt8235/vt8235_early_smbus.c"
  35
  36 #include "southbridge/via/vt8235/vt8235_early_serial.c"
  37 static void memreset_setup(void)
  38 {
  39 }
  40
  41 static inline int spd_read_byte(unsigned device, unsigned address)
  42 {
  43         return smbus_read_byte(device, address);
  44 }
  45
  46 #include "northbridge/via/vt8623/raminit.c"
  47
  48 static void enable_mainboard_devices(void)
  49 {
  50         device_t dev;
  51
  52         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
  53                                 PCI_DEVICE_ID_VIA_8235), 0);
  54
  55         if (dev == PCI_DEV_INVALID) {
  56                 die("Southbridge not found!!!\n");
  57         }
  58         pci_write_config8(dev, 0x50, 0x80);
  59         pci_write_config8(dev, 0x51, 0x1f);
  60 #if 0
  61         // This early setup switches IDE into compatibility mode before PCI gets
  62         // a chance to assign I/Os
  63         // movl    $CONFIG_ADDR(0, 0x89, 0x42), %eax
  64         // //      movb    $0x09, %dl
  65         // movb    $0x00, %dl
  66         // PCI_WRITE_CONFIG_BYTE
  67 #endif
  68         /* we do this here as in V2, we can not yet do raw operations
  69          * to pci!
  70          */
  71         dev += 0x100; /* ICKY */
  72
  73         pci_write_config8(dev, 0x04, 7);
  74         pci_write_config8(dev, 0x40, 3);
  75         pci_write_config8(dev, 0x42, 0);
  76         pci_write_config8(dev, 0x3c, 0xe);
  77         pci_write_config8(dev, 0x3d, 0);
  78 }
  79
  80 static void enable_shadow_ram(void)
  81 {
  82         device_t dev = 0; /* no need to look up 0:0.0 */
  83         unsigned char shadowreg;
  84         /* dev 0 for southbridge */
  85         shadowreg = pci_read_config8(dev, 0x63);
  86         /* 0xf0000-0xfffff */
  87         shadowreg |= 0x30;
  88         pci_write_config8(dev, 0x63, shadowreg);
  89 }
  90
  91 static void main(unsigned long bist)
  92 {
  93         unsigned long x;
  94         device_t dev;
  95
  96         /*
  97          * Enable VGA; 32MB buffer.
  98          */
  99         pci_write_config8(0, 0xe1, 0xdd);
 100
 101         /*
 102          * Disable the firewire stuff, which apparently steps on IO 0+ on
 103          * reset. Doh!
 104          */
 105         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
 106                                 PCI_DEVICE_ID_VIA_6305), 0);
 107         if (dev != PCI_DEV_INVALID) {
 108                 pci_write_config8(dev, 0x15, 0x1c);
 109         }
 110
 111         enable_vt8235_serial();
 112         uart_init();
 113         console_init();
 114
 115         enable_smbus();
 116
 117         print_spew("In auto.c:main()\r\n");
 118
 119         /* Halt if there was a built in self test failure */
 120         report_bist_failure(bist);
 121
 122         // init_timer();
 123
 124         outb(5, 0x80);
 125
 126         print_debug(" Enabling mainboard devices\r\n");
 127         enable_mainboard_devices();
 128
 129         print_debug(" Enabling shadow ram\r\n");
 130         enable_shadow_ram();
 131
 132         ddr_ram_setup((const struct mem_controller *)0);
 133
 134         /* Check all of memory */
 135 #if 0
 136         ram_check(0x00000000, msr.lo);
 137 #endif
 138 #if 0
 139         static const struct {
 140                 unsigned long lo, hi;
 141         } check_addrs[] = {
 142                 /* Check 16MB of memory @ 0*/
 143                 { 0x00000000, 0x01000000 },
 144 #if TOTAL_CPUS > 1
 145                 /* Check 16MB of memory @ 2GB */
 146                 { 0x80000000, 0x81000000 },
 147 #endif
 148         };
 149         int i;
 150         for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
 151                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
 152         }
 153 #endif
 154
 155         if (bist == 0) {
 156                 print_debug(" Doing MTRR init.\r\n");
 157                 early_mtrr_init();
 158         }
 159
 160         //dump_pci_devices();
 161
 162         print_spew("Leaving auto.c:main()\r\n");
 163 }