1 uses CONFIG_HAVE_MP_TABLE
3 uses CONFIG_HAVE_PIRQ_TABLE
4 uses CONFIG_USE_FALLBACK_IMAGE
5 uses CONFIG_HAVE_FALLBACK_BOOT
6 uses CONFIG_HAVE_HARD_RESET
7 uses CONFIG_HAVE_OPTION_TABLE
8 uses CONFIG_USE_OPTION_TABLE
9 uses CONFIG_ROM_PAYLOAD
10 uses CONFIG_IRQ_SLOT_COUNT
12 uses CONFIG_MAINBOARD_VENDOR
13 uses CONFIG_MAINBOARD_PART_NUMBER
14 uses COREBOOT_EXTRA_VERSION
16 uses CONFIG_FALLBACK_SIZE
17 uses CONFIG_STACK_SIZE
20 uses CONFIG_ROM_SECTION_SIZE
21 uses CONFIG_ROM_IMAGE_SIZE
22 uses CONFIG_ROM_SECTION_SIZE
23 uses CONFIG_ROM_SECTION_OFFSET
24 uses CONFIG_ROM_PAYLOAD_START
25 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
26 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
27 uses CONFIG_PRECOMPRESSED_PAYLOAD
28 uses CONFIG_PAYLOAD_SIZE
31 uses CONFIG_XIP_ROM_SIZE
32 uses CONFIG_XIP_ROM_BASE
33 uses CONFIG_HAVE_MP_TABLE
34 uses CONFIG_HAVE_ACPI_TABLES
35 uses CONFIG_HAVE_ACPI_RESUME
36 uses CONFIG_CROSS_COMPILE
40 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
41 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
42 uses CONFIG_CONSOLE_SERIAL8250
43 uses CONFIG_UDELAY_TSC
44 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
45 uses CONFIG_PCI_ROM_RUN
46 uses CONFIG_CONSOLE_VGA
47 uses CONFIG_MAX_PCI_BUSES
48 uses CONFIG_TTYS0_BAUD
50 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
51 default CONFIG_ROM_SIZE = 256*1024
56 default CONFIG_PCI_ROM_RUN=0
57 default CONFIG_CONSOLE_VGA=0
60 ## Build code for the fallback boot
62 default CONFIG_HAVE_FALLBACK_BOOT=1
67 default CONFIG_HAVE_MP_TABLE=0
70 ## Use TSC for udelay.
72 default CONFIG_UDELAY_TSC=1
73 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
76 ## Build code to reset the motherboard from coreboot
78 default CONFIG_HAVE_HARD_RESET=0
81 ## Build code to export a programmable irq routing table
83 default CONFIG_HAVE_PIRQ_TABLE=1
84 default CONFIG_IRQ_SLOT_COUNT=5
88 ## Build code to load acpi tables
90 default CONFIG_HAVE_ACPI_TABLES=1
94 ## Build code to export a CMOS option table
96 default CONFIG_HAVE_OPTION_TABLE=1
99 ### coreboot layout values
102 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
103 default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
104 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
107 ## Use a small 8K stack
109 default CONFIG_STACK_SIZE=0x2000
112 ## Use a small 16K heap
114 default CONFIG_HEAP_SIZE=0x4000
117 ## Only use the option table in a normal image
119 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
120 default CONFIG_USE_OPTION_TABLE = 0
122 default CONFIG_RAMBASE = 0x00004000
124 default CONFIG_ROM_PAYLOAD = 1
127 ## The default compiler
129 default CONFIG_CROSS_COMPILE=""
130 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
134 ## Set this to the max PCI bus number you
135 ## would ever use for PCI config IO.
136 ## Setting this number very high will make
137 ## pci_locate_device take a long time when
138 ## it can't find a device.
140 default CONFIG_MAX_PCI_BUSES = 5
142 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
143 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
144 default CONFIG_CONSOLE_SERIAL8250=1
151 default CONFIG_CBFS=1