1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 128 * 1024
3 include /config/nofailovercalculation.lb
4 default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
7 ## Set all of the defaults for an x86 architecture
13 ## Build the objects we have code for in this directory.
17 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
20 if CONFIG_GENERATE_ACPI_TABLES
30 depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
31 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
34 makerule ./failover.inc
35 depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
36 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
40 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
41 action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
44 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
45 action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
49 ## Build our 16 bit and 32 bit coreboot entry code
51 mainboardinit cpu/x86/16bit/entry16.inc
52 mainboardinit cpu/x86/32bit/entry32.inc
53 ldscript /cpu/x86/16bit/entry16.lds
54 ldscript /cpu/x86/32bit/entry32.lds
57 ## Build our reset vector (This is where coreboot is entered)
59 if CONFIG_USE_FALLBACK_IMAGE
60 mainboardinit cpu/x86/16bit/reset16.inc
61 ldscript /cpu/x86/16bit/reset16.lds
63 mainboardinit cpu/x86/32bit/reset32.inc
64 ldscript /cpu/x86/32bit/reset32.lds
67 ### Should this be in the northbridge code?
68 mainboardinit arch/i386/lib/cpu_reset.inc
71 ## Include an id string (For safe flashing)
73 mainboardinit arch/i386/lib/id.inc
74 ldscript /arch/i386/lib/id.lds
77 ### This is the early phase of coreboot startup
78 ### Things are delicate and we test to see if we should
79 ### failover to another image.
81 if CONFIG_USE_FALLBACK_IMAGE
82 ldscript /arch/i386/lib/failover.lds
83 mainboardinit ./failover.inc
87 ### O.k. We aren't just an intermediary anymore!
93 mainboardinit cpu/x86/fpu_enable.inc
94 mainboardinit ./auto.inc
95 mainboardinit cpu/x86/mmx_disable.inc
98 ## Include the secondary Configuration files
103 chip northbridge/via/vt8623
105 device apic_cluster 0 on
106 chip cpu/via/model_c3
111 device pci_domain 0 on
112 chip southbridge/via/vt8235
114 device pci 10.0 on end # USB 1.1
115 device pci 10.1 on end # USB 1.1
116 device pci 10.2 on end # USB 1.1
117 device pci 10.3 on end # USB 2
119 device pci 11.0 on # Southbridge
120 chip superio/via/vt1211
121 device pnp 2e.0 on # Floppy
126 device pnp 2e.1 on # Parallel Port
131 device pnp 2e.2 on # COM1
135 device pnp 2e.3 on # COM2
139 device pnp 2e.b on # HWM
146 device pci 11.1 on end # IDE
148 device pci 11.5 on end # AC97 Audio
149 device pci 11.6 off end # AC97 Modem
150 device pci 12.0 on end # Ethernet
152 # This is on the EPIA MII, not the M.
153 chip southbridge/ricoh/rl5c476
154 register "enable_cf" = "1"
155 device pci 0a.0 on end
156 device pci 0a.1 on end