src/mainboard/tyan/s4882/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <cpu/amd/model_fxx_rev.h>
  12 #include "northbridge/amd/amdk8/incoherent_ht.c"
  13 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  14 #include "northbridge/amd/amdk8/raminit.h"
  15 #include "cpu/amd/model_fxx/apic_timer.c"
  16 #include "lib/delay.c"
  17 #include "cpu/x86/lapic/boot_cpu.c"
  18 #include "northbridge/amd/amdk8/reset_test.c"
  19 #include "northbridge/amd/amdk8/debug.c"
  20 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  21 #include "cpu/x86/mtrr/earlymtrr.c"
  22 #include "cpu/x86/bist.h"
  23 #include "northbridge/amd/amdk8/setup_resource_map.c"
  24 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  25
  26 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  27
  28 static void memreset_setup(void)
  29 {
  30    if (is_cpu_pre_c0())
  31         outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  32    else
  33         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  34    outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  35 }
  36
  37 static void memreset(int controllers, const struct mem_controller *ctrl)
  38 {
  39    if (is_cpu_pre_c0()) {
  40         udelay(800);
  41         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  42         udelay(90);
  43    }
  44 }
  45
  46 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  47 {
  48 #define SMBUS_HUB 0x18
  49         int ret,i;
  50         unsigned device=(ctrl->channel0[0])>>8;
  51         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  52         i=2;
  53         do {
  54                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  55         } while ((ret!=0) && (i-->0));
  56
  57         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  58 }
  59
  60 #if 0
  61 static inline void change_i2c_mux(unsigned device)
  62 {
  63 #define SMBUS_HUB 0x18
  64         int ret, i;
  65         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  66         i=2;
  67         do {
  68                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  69                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  70         } while ((ret!=0) && (i-->0));
  71         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  72         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  73 }
  74 #endif
  75
  76 static inline int spd_read_byte(unsigned device, unsigned address)
  77 {
  78         return smbus_read_byte(device, address);
  79 }
  80
  81 #include "northbridge/amd/amdk8/raminit.c"
  82 #include "northbridge/amd/amdk8/coherent_ht.c"
  83 #include "lib/generic_sdram.c"
  84 #include "resourcemap.c"
  85 #include "cpu/amd/dualcore/dualcore.c"
  86 #include <spd.h>
  87 #include "cpu/amd/car/post_cache_as_ram.c"
  88 #include "cpu/amd/model_fxx/init_cpus.c"
  89 #include "northbridge/amd/amdk8/early_ht.c"
  90
  91 #define RC0 ((1<<2)<<8)
  92 #define RC1 ((1<<1)<<8)
  93 #define RC2 ((1<<4)<<8)
  94 #define RC3 ((1<<3)<<8)
  95
  96 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  97 {
  98         static const uint16_t spd_addr [] = {
  99                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 100                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 101 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 102                         RC1|DIMM0, RC1|DIMM2, 0, 0,
 103                         RC1|DIMM1, RC1|DIMM3, 0, 0,
 104 #endif
 105 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 106                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 107                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 108                         RC3|DIMM0, RC3|DIMM2, 0, 0,
 109                         RC3|DIMM1, RC3|DIMM3, 0, 0,
 110 #endif
 111         };
 112
 113         int needs_reset;
 114         unsigned bsp_apicid = 0, nodes;
 115         struct mem_controller ctrl[8];
 116
 117         if (!cpu_init_detectedx && boot_cpu()) {
 118                 /* Nothing special needs to be done to find bus 0 */
 119                 /* Allow the HT devices to be found */
 120                 enumerate_ht_chain();
 121         }
 122
 123         if (bist == 0)
 124                 bsp_apicid = init_cpus(cpu_init_detectedx);
 125
 126         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 127         uart_init();
 128         console_init();
 129
 130         /* Halt if there was a built in self test failure */
 131         report_bist_failure(bist);
 132
 133         setup_s4882_resource_map();
 134
 135         needs_reset = setup_coherent_ht_domain();
 136
 137         wait_all_core0_started();
 138 #if CONFIG_LOGICAL_CPUS==1
 139         // It is said that we should start core1 after all core0 launched
 140         start_other_cores();
 141         wait_all_other_cores_started(bsp_apicid);
 142 #endif
 143
 144         // automatically set that for you, but you might meet tight space
 145         needs_reset |= ht_setup_chains_x();
 146
 147         if (needs_reset) {
 148                 print_info("ht reset -\n");
 149                 soft_reset();
 150         }
 151
 152         allow_all_aps_stop(bsp_apicid);
 153
 154         nodes = get_nodes();
 155         //It's the time to set ctrl now;
 156         fill_mem_ctrl(nodes, ctrl, spd_addr);
 157
 158         enable_smbus();
 159
 160         memreset_setup();
 161         sdram_initialize(nodes, ctrl);
 162
 163         post_cache_as_ram();
 164 }