src/mainboard/tyan/s4882/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "console/console.c"
  13 #include "lib/ramtest.c"
  14
  15 #include <cpu/amd/model_fxx_rev.h>
  16 #include "northbridge/amd/amdk8/incoherent_ht.c"
  17 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  18 #include "northbridge/amd/amdk8/raminit.h"
  19 #include "cpu/amd/model_fxx/apic_timer.c"
  20 #include "lib/delay.c"
  21
  22 #include "cpu/x86/lapic/boot_cpu.c"
  23 #include "northbridge/amd/amdk8/reset_test.c"
  24 #include "northbridge/amd/amdk8/debug.c"
  25 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  26
  27 #include "cpu/x86/mtrr/earlymtrr.c"
  28 #include "cpu/x86/bist.h"
  29
  30 #include "northbridge/amd/amdk8/setup_resource_map.c"
  31
  32 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  33
  34 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  35
  36 static void memreset_setup(void)
  37 {
  38    if (is_cpu_pre_c0()) {
  39         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  40    }
  41    else {
  42         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  43    }
  44         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  45 }
  46
  47 static void memreset(int controllers, const struct mem_controller *ctrl)
  48 {
  49    if (is_cpu_pre_c0()) {
  50         udelay(800);
  51         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  52         udelay(90);
  53    }
  54 }
  55 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  56 {
  57 #define SMBUS_HUB 0x18
  58         int ret,i;
  59         unsigned device=(ctrl->channel0[0])>>8;
  60         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  61         i=2;
  62         do {
  63                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  64         } while ((ret!=0) && (i-->0));
  65
  66         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  67 }
  68 #if 0
  69 static inline void change_i2c_mux(unsigned device)
  70 {
  71 #define SMBUS_HUB 0x18
  72         int ret, i;
  73         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  74         i=2;
  75         do {
  76                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  77                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  78         } while ((ret!=0) && (i-->0));
  79         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  80         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  81 }
  82 #endif
  83
  84 static inline int spd_read_byte(unsigned device, unsigned address)
  85 {
  86         return smbus_read_byte(device, address);
  87 }
  88
  89 #define QRANK_DIMM_SUPPORT 1
  90
  91 #include "northbridge/amd/amdk8/raminit.c"
  92 #include "northbridge/amd/amdk8/coherent_ht.c"
  93 #include "lib/generic_sdram.c"
  94
  95  /* tyan does not want the default */
  96 #include "resourcemap.c"
  97
  98 #if CONFIG_LOGICAL_CPUS==1
  99 #define SET_NB_CFG_54 1
 100 #endif
 101 #include "cpu/amd/dualcore/dualcore.c"
 102
 103 #define RC0 ((1<<2)<<8)
 104 #define RC1 ((1<<1)<<8)
 105 #define RC2 ((1<<4)<<8)
 106 #define RC3 ((1<<3)<<8)
 107
 108 #define DIMM0 0x50
 109 #define DIMM1 0x51
 110 #define DIMM2 0x52
 111 #define DIMM3 0x53
 112
 113
 114
 115 #include "cpu/amd/car/post_cache_as_ram.c"
 116
 117 #include "cpu/amd/model_fxx/init_cpus.c"
 118
 119 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 120 #include "northbridge/amd/amdk8/early_ht.c"
 121
 122 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 123 {
 124         static const uint16_t spd_addr [] = {
 125                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 126                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 127 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 128                         RC1|DIMM0, RC1|DIMM2, 0, 0,
 129                         RC1|DIMM1, RC1|DIMM3, 0, 0,
 130 #endif
 131 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 132                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 133                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 134                         RC3|DIMM0, RC3|DIMM2, 0, 0,
 135                         RC3|DIMM1, RC3|DIMM3, 0, 0,
 136 #endif
 137         };
 138
 139         int needs_reset;
 140         unsigned bsp_apicid = 0;
 141
 142         struct mem_controller ctrl[8];
 143         unsigned nodes;
 144
 145         if (!cpu_init_detectedx && boot_cpu()) {
 146                 /* Nothing special needs to be done to find bus 0 */
 147                 /* Allow the HT devices to be found */
 148
 149                 enumerate_ht_chain();
 150
 151                 amd8111_enable_rom();
 152         }
 153
 154         if (bist == 0) {
 155                 bsp_apicid = init_cpus(cpu_init_detectedx);
 156         }
 157
 158
 159         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 160         uart_init();
 161         console_init();
 162
 163         /* Halt if there was a built in self test failure */
 164         report_bist_failure(bist);
 165
 166         setup_s4882_resource_map();
 167
 168         needs_reset = setup_coherent_ht_domain();
 169
 170         wait_all_core0_started();
 171 #if CONFIG_LOGICAL_CPUS==1
 172         // It is said that we should start core1 after all core0 launched
 173         start_other_cores();
 174         wait_all_other_cores_started(bsp_apicid);
 175 #endif
 176
 177         // automatically set that for you, but you might meet tight space
 178         needs_reset |= ht_setup_chains_x();
 179
 180         if (needs_reset) {
 181                 print_info("ht reset -\n");
 182                 soft_reset();
 183         }
 184
 185         allow_all_aps_stop(bsp_apicid);
 186
 187         nodes = get_nodes();
 188         //It's the time to set ctrl now;
 189         fill_mem_ctrl(nodes, ctrl, spd_addr);
 190
 191         enable_smbus();
 192
 193         memreset_setup();
 194         sdram_initialize(nodes, ctrl);
 195
 196         post_cache_as_ram();
 197
 198 }
 199