src/mainboard/tyan/s4880/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <stdlib.h>
   9 #include <pc80/mc146818rtc.h>
  10 #include <console/console.h>
  11 #include <lib.h>
  12
  13 #include <cpu/amd/model_fxx_rev.h>
  14 #include "northbridge/amd/amdk8/incoherent_ht.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "lib/delay.c"
  19
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  24
  25 #include "cpu/x86/mtrr/earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #include "northbridge/amd/amdk8/setup_resource_map.c"
  29
  30 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  31
  32 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  33
  34 static void memreset_setup(void)
  35 {
  36    if (is_cpu_pre_c0()) {
  37         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  38    }
  39    else {
  40         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  41    }
  42         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  43 }
  44
  45 static void memreset(int controllers, const struct mem_controller *ctrl)
  46 {
  47    if (is_cpu_pre_c0()) {
  48         udelay(800);
  49         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  50         udelay(90);
  51    }
  52 }
  53 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  54 {
  55 #define SMBUS_HUB 0x18
  56         unsigned device=(ctrl->channel0[0])>>8;
  57         smbus_write_byte(SMBUS_HUB, 0x01, device);
  58         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  59 }
  60 #if 0
  61 static inline void change_i2c_mux(unsigned device)
  62 {
  63 #define SMBUS_HUB 0x18
  64         int ret;
  65         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  66         ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  67         print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  68         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  69         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  70 }
  71 #endif
  72
  73 static inline int spd_read_byte(unsigned device, unsigned address)
  74 {
  75         return smbus_read_byte(device, address);
  76 }
  77
  78
  79 #include "northbridge/amd/amdk8/raminit.c"
  80 #include "northbridge/amd/amdk8/coherent_ht.c"
  81 #include "lib/generic_sdram.c"
  82
  83  /* tyan does not want the default */
  84 #include "resourcemap.c"
  85
  86 #include "cpu/amd/dualcore/dualcore.c"
  87 #include <spd.h>
  88
  89 #define RC0 ((1<<2)<<8)
  90 #define RC1 ((1<<1)<<8)
  91 #define RC2 ((1<<4)<<8)
  92 #define RC3 ((1<<3)<<8)
  93
  94 #include "cpu/amd/car/post_cache_as_ram.c"
  95
  96 #include "cpu/amd/model_fxx/init_cpus.c"
  97
  98 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  99 #include "northbridge/amd/amdk8/early_ht.c"
 100
 101 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 102 {
 103         static const struct mem_controller cpu[] = {
 104                 {
 105                         .node_id = 0,
 106                         .f0 = PCI_DEV(0, 0x18, 0),
 107                         .f1 = PCI_DEV(0, 0x18, 1),
 108                         .f2 = PCI_DEV(0, 0x18, 2),
 109                         .f3 = PCI_DEV(0, 0x18, 3),
 110                         .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
 111                         .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
 112                 },
 113 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 114                 {
 115                         .node_id = 1,
 116                         .f0 = PCI_DEV(0, 0x19, 0),
 117                         .f1 = PCI_DEV(0, 0x19, 1),
 118                         .f2 = PCI_DEV(0, 0x19, 2),
 119                         .f3 = PCI_DEV(0, 0x19, 3),
 120                         .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
 121                         .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
 122
 123                 },
 124 #endif
 125
 126 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 127                 {
 128                         .node_id = 2,
 129                         .f0 = PCI_DEV(0, 0x1a, 0),
 130                         .f1 = PCI_DEV(0, 0x1a, 1),
 131                         .f2 = PCI_DEV(0, 0x1a, 2),
 132                         .f3 = PCI_DEV(0, 0x1a, 3),
 133                         .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
 134                         .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
 135
 136                 },
 137                 {
 138                         .node_id = 3,
 139                         .f0 = PCI_DEV(0, 0x1b, 0),
 140                         .f1 = PCI_DEV(0, 0x1b, 1),
 141                         .f2 = PCI_DEV(0, 0x1b, 2),
 142                         .f3 = PCI_DEV(0, 0x1b, 3),
 143                         .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
 144                         .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
 145
 146                 },
 147 #endif
 148         };
 149
 150         int needs_reset;
 151
 152         if (!cpu_init_detectedx && boot_cpu()) {
 153                 /* Nothing special needs to be done to find bus 0 */
 154                 /* Allow the HT devices to be found */
 155
 156                 enumerate_ht_chain();
 157
 158                 amd8111_enable_rom();
 159         }
 160
 161         if (bist == 0) {
 162                 init_cpus(cpu_init_detectedx);
 163         }
 164
 165         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 166         uart_init();
 167         console_init();
 168
 169         /* Halt if there was a built in self test failure */
 170         report_bist_failure(bist);
 171
 172         setup_s4880_resource_map();
 173
 174         needs_reset = setup_coherent_ht_domain();
 175
 176 #if CONFIG_LOGICAL_CPUS==1
 177         // It is said that we should start core1 after all core0 launched
 178         start_other_cores();
 179 #endif
 180         // automatically set that for you, but you might meet tight space
 181         needs_reset |= ht_setup_chains_x();
 182
 183         if (needs_reset) {
 184                 print_info("ht reset -\n");
 185                 soft_reset();
 186         }
 187
 188         enable_smbus();
 189
 190         memreset_setup();
 191         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 192
 193         post_cache_as_ram();
 194 }
 195