1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
7 #if CONFIG_LOGICAL_CPUS==1
8 #include <cpu/amd/multicore.h>
11 static unsigned node_link_to_bus(unsigned node, unsigned link)
16 dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
20 for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
25 config_map = pci_read_config32(dev, reg);
26 if ((config_map & 3) != 3) {
29 dst_node = (config_map >> 4) & 7;
30 dst_link = (config_map >> 8) & 3;
31 bus_base = (config_map >> 16) & 0xff;
33 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
34 dst_node, dst_link, bus_base,
37 if ((dst_node == node) && (dst_link == link))
45 static void *smp_write_config_table(void *v)
47 struct mp_config_table *mc;
49 unsigned char bus_chain_0;
50 unsigned char bus_8131_1;
51 unsigned char bus_8131_2;
52 unsigned char bus_8111_1;
55 unsigned apicid_8131_1;
56 unsigned apicid_8131_2;
58 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
60 mptable_init(mc, LOCAL_APIC_ADDR);
62 smp_write_processors(mc);
68 bus_chain_0 = node_link_to_bus(0, 2);
69 if (bus_chain_0 == 0) {
70 printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
75 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
77 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
80 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
85 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
87 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
91 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
96 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
98 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
102 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
109 mptable_write_buses(mc, NULL, &bus_isa);
111 /*I/O APICs: APIC ID Version State Address*/
112 #if CONFIG_LOGICAL_CPUS==1
113 apicid_base = get_apicid_base(3);
115 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
117 apicid_8111 = apicid_base+0;
118 apicid_8131_1 = apicid_base+1;
119 apicid_8131_2 = apicid_base+2;
121 smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
124 struct resource *res;
125 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
127 res = find_resource(dev, PCI_BASE_ADDRESS_0);
129 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
132 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
134 res = find_resource(dev, PCI_BASE_ADDRESS_0);
136 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
142 mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
144 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
145 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13);
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
151 //On Board Via USB 1.1 and 2
152 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|0, apicid_8111, 0x11); //1.1
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|1, apicid_8111, 0x10); //1.1
154 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|2, apicid_8111, 0x12); //2
157 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10);
158 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11);
159 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); //
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
163 //On Board SI Serial ATA
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13);
165 //On Board ATI Display Adapter
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
170 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3);
171 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0);
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);//
173 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);//
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2);
177 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);//
178 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);//
179 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);//
181 //On Board LSI scsi and NIC
182 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0);
183 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, apicid_8131_1, 0x1);
184 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
185 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
187 //Slot 2 PCI-X 133/100/66
188 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
189 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1);
190 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); //
191 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
193 //Slot 1 PCI-X 133/100/66
194 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1);
195 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2);
196 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);//
197 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
199 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
200 mptable_lintsrc(mc, bus_isa);
201 /* There is no extension information... */
203 /* Compute the checksums */
204 return mptable_finalize(mc);
207 unsigned long write_smp_table(unsigned long addr)
210 v = smp_write_floating_table(addr, 0);
211 return (unsigned long)smp_write_config_table(v);