2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #define RAMINIT_SYSINFO 1
27 #define FAM10_SCAN_PCI_BUS 0
28 #define FAM10_ALLOCATE_IO_RANGE 1
30 #define QRANK_DIMM_SUPPORT 1
32 #if CONFIG_LOGICAL_CPUS==1
33 #define SET_NB_CFG_54 1
36 #define FAM10_SET_FIDVID 1
37 #define FAM10_SET_FIDVID_CORE_RANGE 0
39 #define DBGP_DEFAULT 7
43 #include <device/pci_def.h>
44 #include <device/pci_ids.h>
46 #include <device/pnp_def.h>
47 #include <arch/romcc_io.h>
48 #include <cpu/x86/lapic.h>
49 #include "option_table.h"
50 #include "pc80/mc146818rtc_early.c"
52 static void post_code(u8 value) {
56 #include "pc80/serial.c"
57 #include "arch/i386/lib/console.c"
58 #if CONFIG_USBDEBUG_DIRECT
59 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
60 #include "pc80/usbdebug_direct_serial.c"
62 #include "lib/ramtest.c"
64 #include <cpu/amd/model_10xxx_rev.h>
66 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
67 #include "northbridge/amd/amdfam10/raminit.h"
68 #include "northbridge/amd/amdfam10/amdfam10.h"
70 #include "cpu/x86/lapic/boot_cpu.c"
71 #include "northbridge/amd/amdfam10/reset_test.c"
72 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
73 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
75 #include "cpu/x86/bist.h"
77 #include "northbridge/amd/amdfam10/debug.c"
79 #include "cpu/amd/mtrr/amd_earlymtrr.c"
81 #include "northbridge/amd/amdfam10/setup_resource_map.c"
83 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
85 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
87 static void memreset_setup(void)
91 static void memreset(int controllers, const struct mem_controller *ctrl)
95 static inline void activate_spd_rom(const struct mem_controller *ctrl)
100 static inline int spd_read_byte(unsigned device, unsigned address)
102 return smbus_read_byte(device, address);
105 #include "northbridge/amd/amdfam10/amdfam10.h"
106 #include "northbridge/amd/amdht/ht_wrapper.c"
108 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
109 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
110 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
112 #include "resourcemap.c"
114 #include "cpu/amd/quadcore/quadcore.c"
117 #define MCP55_USE_NIC 1
119 #define MCP55_PCI_E_X_0 1
121 #define MCP55_MB_SETUP \
122 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
123 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
124 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
125 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
126 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
127 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
129 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
130 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
132 #include "cpu/amd/car/copy_and_run.c"
134 #include "cpu/amd/car/post_cache_as_ram.c"
136 #include "cpu/amd/model_10xxx/init_cpus.c"
138 #include "cpu/amd/model_10xxx/fidvid.c"
140 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
141 #include "northbridge/amd/amdfam10/early_ht.c"
143 static void sio_setup(void)
149 byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
151 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
153 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
156 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
158 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
160 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
164 #include "spd_addr.h"
165 #include "cpu/amd/microcode/microcode.c"
166 #include "cpu/amd/model_10xxx/update_microcode.c"
168 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
170 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
177 if (!cpu_init_detectedx && boot_cpu()) {
178 /* Nothing special needs to be done to find bus 0 */
179 /* Allow the HT devices to be found */
181 set_bsp_node_CHtExtNodeCfgEn();
182 enumerate_ht_chain();
186 /* Setup the mcp55 */
193 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
198 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
203 /* Halt if there was a built in self test failure */
204 report_bist_failure(bist);
206 #if CONFIG_USBDEBUG_DIRECT
207 mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
208 early_usbdebug_direct_init();
212 printk_debug("BSP Family_Model: %08x\n", val);
213 printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
214 printk_debug("bsp_apicid = %02x\n", bsp_apicid);
215 printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx);
217 /* Setup sysinfo defaults */
218 set_sysinfo_in_ram(0);
220 update_microcode(val);
226 amd_ht_init(sysinfo);
229 /* Setup nodes PCI space and start core 0 AP init. */
230 finalize_node_setup(sysinfo);
232 /* Setup any mainboard PCI settings etc. */
233 setup_mb_resource_map();
236 /* wait for all the APs core0 started by finalize_node_setup. */
237 /* FIXME: A bunch of cores are going to start output to serial at once.
238 * It would be nice to fixup prink spinlocks for ROM XIP mode.
239 * I think it could be done by putting the spinlock flag in the cache
240 * of the BSP located right after sysinfo.
242 wait_all_core0_started();
244 #if CONFIG_LOGICAL_CPUS==1
245 /* Core0 on each node is configured. Now setup any additional cores. */
246 printk_debug("start_other_cores()\n");
249 wait_all_other_cores_started(bsp_apicid);
254 #if FAM10_SET_FIDVID == 1
255 msr = rdmsr(0xc0010071);
256 printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
258 /* FIXME: The sb fid change may survive the warm reset and only
259 * need to be done once.*/
260 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
264 if (!warm_reset_detect(0)) { // BSP is node 0
265 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
267 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
272 /* show final fid and vid */
273 msr=rdmsr(0xc0010071);
274 printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
277 wants_reset = mcp55_early_setup_x();
279 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
280 if (!warm_reset_detect(0)) {
281 print_info("...WARM RESET...\n\n\n");
283 die("After soft_reset_x - shouldn't see this message!!!\n");
287 printk_debug("mcp55_early_setup_x wanted additional reset!\n");
291 /* It's the time to set ctrl in sysinfo now; */
292 printk_debug("fill_mem_ctrl()\n");
293 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
296 printk_debug("enable_smbus()\n");
303 printk_debug("raminit_amdmct()\n");
304 raminit_amdmct(sysinfo);
307 printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
308 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
309 post_code(0x43); // Should never see this post code.