2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 ## XIP_ROM_SIZE must be a power of 2.
23 default XIP_ROM_SIZE = 64 * 1024
24 include /config/failovercalculation.lb
29 ## Build the objects we have code for in this directory.
33 #needed by irq_tables and mptable and acpi_tables
36 if HAVE_MP_TABLE object mptable.o end
37 if HAVE_PIRQ_TABLE object irq_tables.o end
41 makerule ./cache_as_ram_auto.o
42 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
43 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
46 makerule ./cache_as_ram_auto.inc
47 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
48 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
49 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
50 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
56 if CONFIG_AP_CODE_IN_CAR
58 depends "$(MAINBOARD)/apc_auto.c option_table.h"
59 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
61 ldscript /arch/i386/init/ldscript_apc.lb
67 ## Build our 16 bit and 32 bit coreboot entry code
71 mainboardinit cpu/x86/16bit/entry16.inc
72 ldscript /cpu/x86/16bit/entry16.lds
76 mainboardinit cpu/x86/16bit/entry16.inc
77 ldscript /cpu/x86/16bit/entry16.lds
81 mainboardinit cpu/x86/32bit/entry32.inc
84 ldscript /cpu/x86/32bit/entry32.lds
88 ldscript /cpu/amd/car/cache_as_ram.lds
92 ## Build our reset vector (This is where coreboot is entered)
96 mainboardinit cpu/x86/16bit/reset16.inc
97 ldscript /cpu/x86/16bit/reset16.lds
99 mainboardinit cpu/x86/32bit/reset32.inc
100 ldscript /cpu/x86/32bit/reset32.lds
103 if USE_FALLBACK_IMAGE
104 mainboardinit cpu/x86/16bit/reset16.inc
105 ldscript /cpu/x86/16bit/reset16.lds
107 mainboardinit cpu/x86/32bit/reset32.inc
108 ldscript /cpu/x86/32bit/reset32.lds
113 ## Include an id string (For safe flashing)
115 mainboardinit southbridge/nvidia/mcp55/id.inc
116 ldscript /southbridge/nvidia/mcp55/id.lds
119 ## ROMSTRAP table for MCP55
121 if HAVE_FAILOVER_BOOT
122 if USE_FAILOVER_IMAGE
123 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
124 ldscript /southbridge/nvidia/mcp55/romstrap.lds
127 if USE_FALLBACK_IMAGE
128 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
129 ldscript /southbridge/nvidia/mcp55/romstrap.lds
134 ## Setup Cache-As-Ram
136 mainboardinit cpu/amd/car/cache_as_ram.inc
139 ### This is the early phase of coreboot startup
140 ### Things are delicate and we test to see if we should
141 ### failover to another image.
143 if HAVE_FAILOVER_BOOT
144 if USE_FAILOVER_IMAGE
145 ldscript /arch/i386/lib/failover_failover.lds
148 if USE_FALLBACK_IMAGE
149 ldscript /arch/i386/lib/failover.lds
157 initobject cache_as_ram_auto.o
159 mainboardinit ./cache_as_ram_auto.inc
163 ## Include the secondary Configuration files
167 dir /southbridge/nvidia/mcp55
169 chip northbridge/amd/amdfam10/root_complex
170 device apic_cluster 0 on
171 chip cpu/amd/socket_F_1207
175 device pci_domain 0 on
176 chip northbridge/amd/amdfam10 #mc0
177 device pci 18.0 on end
178 device pci 18.0 on end
181 chip southbridge/nvidia/mcp55
182 device pci 0.0 on end # HT
183 device pci 1.0 on # LPC
184 chip superio/winbond/w83627hf
185 device pnp 2e.0 off # Floppy
190 device pnp 2e.1 off # Parallel Port
194 device pnp 2e.2 on # Com1
198 device pnp 2e.3 on # Com2
202 device pnp 2e.5 on # Keyboard
208 device pnp 2e.6 off # SFI
211 device pnp 2e.7 off # GPIO_GAME_MIDI
216 device pnp 2e.8 off end # WDTO_PLED
217 device pnp 2e.9 off end # GPIO_SUSLED
218 device pnp 2e.a off end # ACPI
219 device pnp 2e.b on # HW Monitor
225 device pci 1.1 on # SM 0
226 chip drivers/generic/generic #dimm 0-0-0
229 chip drivers/generic/generic #dimm 0-0-1
232 chip drivers/generic/generic #dimm 0-1-0
235 chip drivers/generic/generic #dimm 0-1-1
238 chip drivers/generic/generic #dimm 1-0-0
241 chip drivers/generic/generic #dimm 1-0-1
244 chip drivers/generic/generic #dimm 1-1-0
247 chip drivers/generic/generic #dimm 1-1-1
251 device pci 1.1 on # SM 1
252 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
253 # chip drivers/generic/generic #PCIXA Slot1
254 # device i2c 50 on end
256 # chip drivers/generic/generic #PCIXB Slot1
257 # device i2c 51 on end
259 # chip drivers/generic/generic #PCIXB Slot2
260 # device i2c 52 on end
262 # chip drivers/generic/generic #PCI Slot1
263 # device i2c 53 on end
265 # chip drivers/generic/generic #Master MCP55 PCI-E
266 # device i2c 54 on end
268 # chip drivers/generic/generic #Slave MCP55 PCI-E
269 # device i2c 55 on end
271 chip drivers/generic/generic #MAC EEPROM
276 device pci 2.0 on end # USB 1.1
277 device pci 2.1 on end # USB 2
278 device pci 4.0 on end # IDE
279 device pci 5.0 on end # SATA 0
280 device pci 5.1 on end # SATA 1
281 device pci 5.2 on end # SATA 2
283 chip drivers/pci/onboard
284 device pci 4.0 on end
285 register "rom_address" = "0xfff00000"
288 device pci 6.1 off end # AZA
289 device pci 8.0 on end # NIC
290 device pci 9.0 on end # NIC
291 device pci a.0 on end # PCI E 5
292 device pci b.0 off end # PCI E 4
293 device pci c.0 off end # PCI E 3
294 device pci d.0 on end # PCI E 2
295 device pci e.0 off end # PCI E 1
296 device pci f.0 on end # PCI E 0
297 register "ide0_enable" = "1"
298 register "sata0_enable" = "1"
299 register "sata1_enable" = "1"
300 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
301 register "mac_eeprom_addr" = "0x51"
303 end # device pci 18.0
304 device pci 18.1 on end
305 device pci 18.2 on end
306 device pci 18.3 on end
307 device pci 18.4 on end
312 # chip drivers/generic/debug
313 # device pnp 0.0 off end # chip name
314 # device pnp 0.1 on end # pci_regs_all
315 # device pnp 0.2 on end # mem
316 # device pnp 0.3 off end # cpuid
317 # device pnp 0.4 on end # smbus_regs_all
318 # device pnp 0.5 off end # dual core msr
319 # device pnp 0.6 off end # cache size
320 # device pnp 0.7 off end # tsc
321 # device pnp 0.8 off end # io
322 # device pnp 0.9 off end # io