2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 uses CONFIG_HAVE_MP_TABLE
24 uses CONFIG_HAVE_PIRQ_TABLE
25 uses CONFIG_HAVE_ACPI_TABLES
26 uses CONFIG_HAVE_ACPI_RESUME
27 uses CONFIG_ACPI_SSDTX_NUM
28 uses CONFIG_USE_FALLBACK_IMAGE
29 uses CONFIG_USE_FAILOVER_IMAGE
30 uses CONFIG_HAVE_FALLBACK_BOOT
31 uses CONFIG_HAVE_FAILOVER_BOOT
32 uses CONFIG_HAVE_HARD_RESET
33 uses CONFIG_IRQ_SLOT_COUNT
34 uses CONFIG_HAVE_OPTION_TABLE
36 uses CONFIG_MAX_PHYSICAL_CPUS
37 uses CONFIG_LOGICAL_CPUS
40 uses CONFIG_FALLBACK_SIZE
41 uses CONFIG_FAILOVER_SIZE
43 uses CONFIG_ROM_SECTION_SIZE
44 uses CONFIG_ROM_IMAGE_SIZE
45 uses CONFIG_ROM_SECTION_SIZE
46 uses CONFIG_ROM_SECTION_OFFSET
47 uses CONFIG_ROM_PAYLOAD
48 uses CONFIG_ROM_PAYLOAD_START
49 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
50 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
51 uses CONFIG_PRECOMPRESSED_PAYLOAD
52 uses CONFIG_PAYLOAD_SIZE
54 uses CONFIG_XIP_ROM_SIZE
55 uses CONFIG_XIP_ROM_BASE
56 uses CONFIG_STACK_SIZE
58 uses CONFIG_USE_OPTION_TABLE
59 uses CONFIG_LB_CKS_RANGE_START
60 uses CONFIG_LB_CKS_RANGE_END
61 uses CONFIG_LB_CKS_LOC
62 uses CONFIG_MAINBOARD_PART_NUMBER
63 uses CONFIG_MAINBOARD_VENDOR
65 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
66 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
67 uses COREBOOT_EXTRA_VERSION
69 uses CONFIG_TTYS0_BAUD
70 uses CONFIG_TTYS0_BASE
72 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
73 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
74 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
75 uses CONFIG_CONSOLE_SERIAL8250
76 uses CONFIG_HAVE_INIT_TIMER
79 uses CONFIG_CROSS_COMPILE
83 uses CONFIG_CONSOLE_VGA
84 uses CONFIG_USBDEBUG_DIRECT
85 uses CONFIG_PCI_ROM_RUN
86 uses CONFIG_HW_MEM_HOLE_SIZEK
87 uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
88 uses CONFIG_K8_HT_FREQ_1G_SUPPORT
90 uses CONFIG_HT_CHAIN_UNITID_BASE
91 uses CONFIG_HT_CHAIN_END_UNITID_BASE
92 uses CONFIG_SB_HT_CHAIN_ON_BUS0
93 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
95 uses CONFIG_USE_DCACHE_RAM
96 uses CONFIG_DCACHE_RAM_BASE
97 uses CONFIG_DCACHE_RAM_SIZE
98 uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
101 uses CONFIG_SERIAL_CPU_INIT
103 uses CONFIG_ENABLE_APIC_EXT_ID
104 uses CONFIG_APIC_ID_OFFSET
105 uses CONFIG_LIFT_BSP_APIC_ID
107 uses CONFIG_PCI_64BIT_PREF_MEM
109 uses CONFIG_LB_MEM_TOPK
111 uses CONFIG_AP_CODE_IN_CAR
113 uses CONFIG_MEM_TRAIN_SEQ
115 uses CONFIG_WAIT_BEFORE_CPUS_INIT
117 uses CONFIG_USE_PRINTK_IN_CAR
124 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
126 default CONFIG_ROM_SIZE=524288
127 #default CONFIG_ROM_SIZE=0x100000
130 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
132 #default CONFIG_FALLBACK_SIZE=131072
133 #default CONFIG_FALLBACK_SIZE=0x40000
136 default CONFIG_FALLBACK_SIZE=0x3f000
138 default CONFIG_FAILOVER_SIZE=0x01000
141 default CONFIG_LB_MEM_TOPK=2048
144 ## Build code for the fallback boot
146 default CONFIG_HAVE_FALLBACK_BOOT=1
147 default CONFIG_HAVE_FAILOVER_BOOT=1
150 ## Build code to reset the motherboard from coreboot
152 default CONFIG_HAVE_HARD_RESET=1
155 ## Build code to export a programmable irq routing table
157 default CONFIG_HAVE_PIRQ_TABLE=1
158 default CONFIG_IRQ_SLOT_COUNT=11
161 ## Build code to export an x86 MP table
162 ## Useful for specifying IRQ routing values
164 default CONFIG_HAVE_MP_TABLE=1
166 ## ACPI tables will be included
167 default CONFIG_HAVE_ACPI_TABLES=0
169 default CONFIG_ACPI_SSDTX_NUM=3
172 ## Build code to export a CMOS option table
174 default CONFIG_HAVE_OPTION_TABLE=1
177 ## Move the default coreboot cmos range off of AMD RTC registers
179 default CONFIG_LB_CKS_RANGE_START=49
180 default CONFIG_LB_CKS_RANGE_END=122
181 default CONFIG_LB_CKS_LOC=123
184 ## Build code for SMP support
185 ## Only worry about 2 micro processors
188 default CONFIG_MAX_CPUS=4
189 default CONFIG_MAX_PHYSICAL_CPUS=2
190 default CONFIG_LOGICAL_CPUS=1
192 #default CONFIG_SERIAL_CPU_INIT=0
194 default CONFIG_ENABLE_APIC_EXT_ID=0
195 default CONFIG_APIC_ID_OFFSET=0x10
196 default CONFIG_LIFT_BSP_APIC_ID=1
198 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
200 #default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
202 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
204 #default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
206 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
207 #default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
209 #Opteron K8 1G HT Support
210 default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
213 default CONFIG_CONSOLE_VGA=1
214 default CONFIG_PCI_ROM_RUN=1
216 #default CONFIG_USBDEBUG_DIRECT=1
218 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
219 default CONFIG_HT_CHAIN_UNITID_BASE=0
221 #real SB Unit ID, default is 0x20, mean dont touch it at last
222 #default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
224 #make the SB HT chain on bus 0, default is not (0)
225 default CONFIG_SB_HT_CHAIN_ON_BUS0=2
227 #only offset for SB chain?, default is yes(1)
228 default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
230 #allow capable device use that above 4G
231 #default CONFIG_PCI_64BIT_PREF_MEM=1
234 ## enable CACHE_AS_RAM specifics
236 default CONFIG_USE_DCACHE_RAM=1
237 default CONFIG_DCACHE_RAM_BASE=0xc8000
238 default CONFIG_DCACHE_RAM_SIZE=0x08000
239 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
240 default CONFIG_USE_INIT=0
242 default CONFIG_AP_CODE_IN_CAR=0
243 default CONFIG_MEM_TRAIN_SEQ=1
244 default CONFIG_WAIT_BEFORE_CPUS_INIT=1
247 ## Build code to setup a generic IOAPIC
249 default CONFIG_IOAPIC=1
252 ## Clean up the motherboard id strings
254 default CONFIG_MAINBOARD_PART_NUMBER="S2912"
255 default CONFIG_MAINBOARD_VENDOR="Tyan"
256 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
257 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912
260 ### coreboot layout values
263 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
264 default CONFIG_ROM_IMAGE_SIZE = 65536
267 ## Use a small 8K stack
269 default CONFIG_STACK_SIZE=0x2000
272 ## Use a small 32K heap
274 default CONFIG_HEAP_SIZE=0x8000
277 ## Only use the option table in a normal image
279 default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
282 ## Coreboot C code runs at this location in RAM
284 default CONFIG_RAMBASE=0x00100000
287 ## Load the payload from the ROM
289 default CONFIG_ROM_PAYLOAD = 1
291 #default CONFIG_COMPRESSED_PAYLOAD = 1
294 ### Defaults of options that you may want to override in the target config file
298 ## The default compiler
300 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
304 ## Disable the gdb stub by default
306 default CONFIG_GDB_STUB=0
309 ## The Serial Console
311 default CONFIG_USE_PRINTK_IN_CAR=1
313 # To Enable the Serial Console
314 default CONFIG_CONSOLE_SERIAL8250=1
316 ## Select the serial console baud rate
317 default CONFIG_TTYS0_BAUD=115200
318 #default CONFIG_TTYS0_BAUD=57600
319 #default CONFIG_TTYS0_BAUD=38400
320 #default CONFIG_TTYS0_BAUD=19200
321 #default CONFIG_TTYS0_BAUD=9600
322 #default CONFIG_TTYS0_BAUD=4800
323 #default CONFIG_TTYS0_BAUD=2400
324 #default CONFIG_TTYS0_BAUD=1200
326 # Select the serial console base port
327 default CONFIG_TTYS0_BASE=0x3f8
329 # Select the serial protocol
330 # This defaults to 8 data bits, 1 stop bit, and no parity
331 default CONFIG_TTYS0_LCS=0x3
334 ### Select the coreboot loglevel
336 ## EMERG 1 system is unusable
337 ## ALERT 2 action must be taken immediately
338 ## CRIT 3 critical conditions
339 ## ERR 4 error conditions
340 ## WARNING 5 warning conditions
341 ## NOTICE 6 normal but significant condition
342 ## INFO 7 informational
343 ## CONFIG_DEBUG 8 debug-level messages
344 ## SPEW 9 Way too many details
346 ## Request this level of debugging output
347 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
348 ## At a maximum only compile in this level of debugging
349 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
352 ## Select power on after power fail setting
353 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
360 default CONFIG_CBFS=0