src/mainboard/tyan/s2912/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; either version 2 of the License, or
  10 ## (at your option) any later version.
  11 ##
  12 ## This program is distributed in the hope that it will be useful,
  13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ## GNU General Public License for more details.
  16 ##
  17 ## You should have received a copy of the GNU General Public License
  18 ## along with this program; if not, write to the Free Software
  19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 ##
  21
  22 ##
  23 ## Compute the location and size of where this firmware image
  24 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
  25 ##
  26 if USE_FAILOVER_IMAGE
  27         default ROM_SECTION_SIZE   = FAILOVER_SIZE
  28         default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
  29 else
  30     if USE_FALLBACK_IMAGE
  31         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  32         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  33     else
  34         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  35         default ROM_SECTION_OFFSET = 0
  36     end
  37 end
  38
  39 ##
  40 ## Compute the start location and size size of
  41 ## The linuxBIOS bootloader.
  42 ##
  43 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  44 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  45
  46 ##
  47 ## Compute where this copy of linuxBIOS will start in the boot rom
  48 ##
  49 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  50
  51 ##
  52 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  53 ## execution speed.
  54 ##
  55 ## XIP_ROM_SIZE must be a power of 2.
  56 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  57 ##
  58 default XIP_ROM_SIZE=65536
  59
  60 if USE_FAILOVER_IMAGE
  61         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  62 else
  63     if USE_FALLBACK_IMAGE
  64         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
  65     else
  66         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  67     end
  68 end
  69
  70 arch i386 end
  71
  72 ##
  73 ## Build the objects we have code for in this directory.
  74 ##
  75
  76 driver mainboard.o
  77 #needed by irq_tables and mptable and acpi_tables
  78 object get_bus_conf.o
  79
  80 if HAVE_MP_TABLE object mptable.o end
  81 if HAVE_PIRQ_TABLE object irq_tables.o end
  82 #object reset.o
  83
  84 if USE_DCACHE_RAM
  85
  86         if CONFIG_USE_INIT
  87                 makerule ./cache_as_ram_auto.o
  88                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  89                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
  90                 end
  91         else
  92                 makerule ./cache_as_ram_auto.inc
  93                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  94                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
  95                         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
  96                         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
  97                 end
  98         end
  99
 100 end
 101
 102 if USE_FAILOVER_IMAGE
 103 else
 104     if CONFIG_AP_CODE_IN_CAR
 105         makerule ./apc_auto.o
 106                 depends "$(MAINBOARD)/apc_auto.c option_table.h"
 107                 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
 108         end
 109         ldscript /arch/i386/init/ldscript_apc.lb
 110     end
 111 end
 112
 113
 114 ##
 115 ## Build our 16 bit and 32 bit linuxBIOS entry code
 116 ##
 117 if HAVE_FAILOVER_BOOT
 118     if USE_FAILOVER_IMAGE
 119         mainboardinit cpu/x86/16bit/entry16.inc
 120         ldscript /cpu/x86/16bit/entry16.lds
 121     end
 122 else
 123     if USE_FALLBACK_IMAGE
 124         mainboardinit cpu/x86/16bit/entry16.inc
 125         ldscript /cpu/x86/16bit/entry16.lds
 126     end
 127 end
 128
 129 mainboardinit cpu/x86/32bit/entry32.inc
 130
 131 if USE_DCACHE_RAM
 132         if CONFIG_USE_INIT
 133                 ldscript /cpu/x86/32bit/entry32.lds
 134         end
 135
 136         if CONFIG_USE_INIT
 137                 ldscript /cpu/amd/car/cache_as_ram.lds
 138         end
 139 end
 140
 141
 142 ##
 143 ## Build our reset vector (This is where linuxBIOS is entered)
 144 ##
 145 if HAVE_FAILOVER_BOOT
 146     if USE_FAILOVER_IMAGE
 147         mainboardinit cpu/x86/16bit/reset16.inc
 148         ldscript /cpu/x86/16bit/reset16.lds
 149     else
 150         mainboardinit cpu/x86/32bit/reset32.inc
 151         ldscript /cpu/x86/32bit/reset32.lds
 152     end
 153 else
 154     if USE_FALLBACK_IMAGE
 155         mainboardinit cpu/x86/16bit/reset16.inc
 156         ldscript /cpu/x86/16bit/reset16.lds
 157     else
 158         mainboardinit cpu/x86/32bit/reset32.inc
 159         ldscript /cpu/x86/32bit/reset32.lds
 160     end
 161 end
 162
 163 ##
 164 ## Include an id string (For safe flashing)
 165 ##
 166 mainboardinit southbridge/nvidia/mcp55/id.inc
 167 ldscript /southbridge/nvidia/mcp55/id.lds
 168
 169 ##
 170 ## ROMSTRAP table for MCP55
 171 ##
 172 if HAVE_FAILOVER_BOOT
 173     if USE_FAILOVER_IMAGE
 174         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 175         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 176     end
 177 else
 178     if USE_FALLBACK_IMAGE
 179         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 180         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 181     end
 182 end
 183
 184 if USE_DCACHE_RAM
 185         ##
 186         ## Setup Cache-As-Ram
 187         ##
 188         mainboardinit cpu/amd/car/cache_as_ram.inc
 189 end
 190
 191 ###
 192 ### This is the early phase of linuxBIOS startup
 193 ### Things are delicate and we test to see if we should
 194 ### failover to another image.
 195 ###
 196 if HAVE_FAILOVER_BOOT
 197     if USE_FAILOVER_IMAGE
 198         if USE_DCACHE_RAM
 199                 ldscript /arch/i386/lib/failover_failover.lds
 200         end
 201     end
 202 else
 203     if USE_FALLBACK_IMAGE
 204         if USE_DCACHE_RAM
 205                 ldscript /arch/i386/lib/failover.lds
 206         end
 207     end
 208 end
 209
 210 ##
 211 ## Setup RAM
 212 ##
 213 if USE_DCACHE_RAM
 214
 215         if CONFIG_USE_INIT
 216                 initobject cache_as_ram_auto.o
 217         else
 218                 mainboardinit ./cache_as_ram_auto.inc
 219         end
 220 end
 221
 222 ##
 223 ## Include the secondary Configuration files
 224 ##
 225 if CONFIG_CHIP_NAME
 226         config chip.h
 227 end
 228
 229 chip northbridge/amd/amdk8/root_complex
 230         device apic_cluster 0 on
 231                 chip cpu/amd/socket_F
 232                         device apic 0 on end
 233                 end
 234         end
 235         device pci_domain 0 on
 236                 chip northbridge/amd/amdk8 #mc0
 237                         device pci 18.0 on end
 238                         device pci 18.0 on end
 239                         device pci 18.0 on
 240                                 #  devices on link 0, link 0 == LDT 0
 241                                 chip southbridge/nvidia/mcp55
 242                                         device pci 0.0 on end   # HT
 243                                         device pci 1.0 on # LPC
 244                                                 chip superio/winbond/w83627hf
 245                                                         device pnp 2e.0 off #  Floppy
 246                                                                 io 0x60 = 0x3f0
 247                                                                 irq 0x70 = 6
 248                                                                 drq 0x74 = 2
 249                                                         end
 250                                                         device pnp 2e.1 off #  Parallel Port
 251                                                                 io 0x60 = 0x378
 252                                                                 irq 0x70 = 7
 253                                                         end
 254                                                         device pnp 2e.2 on #  Com1
 255                                                                 io 0x60 = 0x3f8
 256                                                                 irq 0x70 = 4
 257                                                         end
 258                                                         device pnp 2e.3 on #  Com2
 259                                                                 io 0x60 = 0x2f8
 260                                                                 irq 0x70 = 3
 261                                                         end
 262                                                         device pnp 2e.5 on #  Keyboard
 263                                                                 io 0x60 = 0x60
 264                                                                 io 0x62 = 0x64
 265                                                                 irq 0x70 = 1
 266                                                                 irq 0x72 = 12
 267                                                         end
 268                                                         device pnp 2e.6 off  # SFI
 269                                                                 io 0x62 = 0x100
 270                                                         end
 271                                                         device pnp 2e.7 off #  GPIO_GAME_MIDI
 272                                                                 io 0x60 = 0x220
 273                                                                 io 0x62 = 0x300
 274                                                                 irq 0x70 = 9
 275                                                         end
 276                                                         device pnp 2e.8 off end #  WDTO_PLED
 277                                                         device pnp 2e.9 off end #  GPIO_SUSLED
 278                                                         device pnp 2e.a off end #  ACPI
 279                                                         device pnp 2e.b on #  HW Monitor
 280                                                                 io 0x60 = 0x290
 281                                                                 irq 0x70 = 5
 282                                                         end
 283                                                 end
 284                                         end
 285                                         device pci 1.1 on # SM 0
 286                                                 chip drivers/generic/generic #dimm 0-0-0
 287                                                         device i2c 50 on end
 288                                                 end
 289                                                 chip drivers/generic/generic #dimm 0-0-1
 290                                                         device i2c 51 on end
 291                                                 end
 292                                                 chip drivers/generic/generic #dimm 0-1-0
 293                                                         device i2c 52 on end
 294                                                 end
 295                                                 chip drivers/generic/generic #dimm 0-1-1
 296                                                         device i2c 53 on end
 297                                                 end
 298                                                 chip drivers/generic/generic #dimm 1-0-0
 299                                                         device i2c 54 on end
 300                                                 end
 301                                                 chip drivers/generic/generic #dimm 1-0-1
 302                                                         device i2c 55 on end
 303                                                 end
 304                                                 chip drivers/generic/generic #dimm 1-1-0
 305                                                         device i2c 56 on end
 306                                                 end
 307                                                 chip drivers/generic/generic #dimm 1-1-1
 308                                                         device i2c 57 on end
 309                                                 end
 310                                         end # SM
 311                                         device pci 1.1 on # SM 1
 312 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 313 #                                                chip drivers/generic/generic #PCIXA Slot1
 314 #                                                        device i2c 50 on end
 315 #                                                end
 316 #                                                chip drivers/generic/generic #PCIXB Slot1
 317 #                                                        device i2c 51 on end
 318 #                                                end
 319 #                                                chip drivers/generic/generic #PCIXB Slot2
 320 #                                                        device i2c 52 on end
 321 #                                                end
 322 #                                                chip drivers/generic/generic #PCI Slot1
 323 #                                                        device i2c 53 on end
 324 #                                                end
 325 #                                                chip drivers/generic/generic #Master MCP55 PCI-E
 326 #                                                        device i2c 54 on end
 327 #                                                end
 328 #                                                chip drivers/generic/generic #Slave MCP55 PCI-E
 329 #                                                        device i2c 55 on end
 330 #                                                end
 331                                                 chip drivers/generic/generic #MAC EEPROM
 332                                                         device i2c 51 on end
 333                                                 end
 334
 335                                         end # SM
 336                                         device pci 2.0 on end # USB 1.1
 337                                         device pci 2.1 on end # USB 2
 338                                         device pci 4.0 on end # IDE
 339                                         device pci 5.0 on end # SATA 0
 340                                         device pci 5.1 on end # SATA 1
 341                                         device pci 5.2 on end # SATA 2
 342                                         device pci 6.0 on end # PCI
 343                                         device pci 6.1 off end # AZA
 344                                         device pci 8.0 on end # NIC
 345                                         device pci 9.0 on end # NIC
 346                                         device pci a.0 on end # PCI E 5
 347                                         device pci b.0 off end # PCI E 4
 348                                         device pci c.0 off end # PCI E 3
 349                                         device pci d.0 on end # PCI E 2
 350                                         device pci e.0 off end # PCI E 1
 351                                         device pci f.0 on end # PCI E 0
 352                                         register "ide0_enable" = "1"
 353                                         register "sata0_enable" = "1"
 354                                         register "sata1_enable" = "1"
 355                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 356                                         register "mac_eeprom_addr" = "0x51"
 357                                 end
 358                         end #  device pci 18.0
 359                         device pci 18.1 on end
 360                         device pci 18.2 on end
 361                         device pci 18.3 on end
 362                 end # mc0
 363
 364         end # PCI domain
 365
 366 #       chip drivers/generic/debug
 367 #               device pnp 0.0 off end # chip name
 368 #                device pnp 0.1 on end # pci_regs_all
 369 #                device pnp 0.2 on end # mem
 370 #                device pnp 0.3 off end # cpuid
 371 #                device pnp 0.4 on end # smbus_regs_all
 372 #                device pnp 0.5 off end # dual core msr
 373 #                device pnp 0.6 off end # cache size
 374 #               device pnp 0.7 off end # tsc
 375 #                device pnp 0.8 off  end # io
 376 #                device pnp 0.9 off end # io
 377 #       end
 378 end #root_complex