src/mainboard/tyan/s2912/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; either version 2 of the License, or
  10 ## (at your option) any later version.
  11 ##
  12 ## This program is distributed in the hope that it will be useful,
  13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ## GNU General Public License for more details.
  16 ##
  17 ## You should have received a copy of the GNU General Public License
  18 ## along with this program; if not, write to the Free Software
  19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 ##
  21
  22 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
  23 default CONFIG_XIP_ROM_SIZE = 64 * 1024
  24 include /config/failovercalculation.lb
  25
  26 arch i386 end
  27
  28 ##
  29 ## Build the objects we have code for in this directory.
  30 ##
  31
  32 driver mainboard.o
  33 #needed by irq_tables and mptable and acpi_tables
  34 object get_bus_conf.o
  35
  36 if CONFIG_GENERATE_MP_TABLE object mptable.o end
  37 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
  38
  39         if CONFIG_USE_INIT
  40                 makerule ./cache_as_ram_auto.o
  41                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  42                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  43                 end
  44         else
  45                 makerule ./cache_as_ram_auto.inc
  46                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  47                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  48                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  49                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  50                 end
  51         end
  52
  53 if CONFIG_USE_FAILOVER_IMAGE
  54 else
  55     if CONFIG_AP_CODE_IN_CAR
  56         makerule ./apc_auto.o
  57                 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
  58                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
  59         end
  60         ldscript /arch/i386/init/ldscript_apc.lb
  61     end
  62 end
  63
  64
  65 ##
  66 ## Build our 16 bit and 32 bit coreboot entry code
  67 ##
  68 if CONFIG_HAVE_FAILOVER_BOOT
  69     if CONFIG_USE_FAILOVER_IMAGE
  70         mainboardinit cpu/x86/16bit/entry16.inc
  71         ldscript /cpu/x86/16bit/entry16.lds
  72     end
  73 else
  74     if CONFIG_USE_FALLBACK_IMAGE
  75         mainboardinit cpu/x86/16bit/entry16.inc
  76         ldscript /cpu/x86/16bit/entry16.lds
  77     end
  78 end
  79
  80 mainboardinit cpu/x86/32bit/entry32.inc
  81
  82         if CONFIG_USE_INIT
  83                 ldscript /cpu/x86/32bit/entry32.lds
  84         end
  85
  86         if CONFIG_USE_INIT
  87                 ldscript /cpu/amd/car/cache_as_ram.lds
  88         end
  89
  90 ##
  91 ## Build our reset vector (This is where coreboot is entered)
  92 ##
  93 if CONFIG_HAVE_FAILOVER_BOOT
  94     if CONFIG_USE_FAILOVER_IMAGE
  95         mainboardinit cpu/x86/16bit/reset16.inc
  96         ldscript /cpu/x86/16bit/reset16.lds
  97     else
  98         mainboardinit cpu/x86/32bit/reset32.inc
  99         ldscript /cpu/x86/32bit/reset32.lds
 100     end
 101 else
 102     if CONFIG_USE_FALLBACK_IMAGE
 103         mainboardinit cpu/x86/16bit/reset16.inc
 104         ldscript /cpu/x86/16bit/reset16.lds
 105     else
 106         mainboardinit cpu/x86/32bit/reset32.inc
 107         ldscript /cpu/x86/32bit/reset32.lds
 108     end
 109 end
 110
 111 ##
 112 ## Include an id string (For safe flashing)
 113 ##
 114 mainboardinit arch/i386/lib/id.inc
 115 ldscript /arch/i386/lib/id.lds
 116
 117 ##
 118 ## ROMSTRAP table for MCP55
 119 ##
 120 if CONFIG_HAVE_FAILOVER_BOOT
 121     if CONFIG_USE_FAILOVER_IMAGE
 122         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 123         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 124     end
 125 else
 126     if CONFIG_USE_FALLBACK_IMAGE
 127         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 128         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 129     end
 130 end
 131
 132         ##
 133         ## Setup Cache-As-Ram
 134         ##
 135         mainboardinit cpu/amd/car/cache_as_ram.inc
 136
 137 ###
 138 ### This is the early phase of coreboot startup
 139 ### Things are delicate and we test to see if we should
 140 ### failover to another image.
 141 ###
 142 if CONFIG_HAVE_FAILOVER_BOOT
 143     if CONFIG_USE_FAILOVER_IMAGE
 144                 ldscript /arch/i386/lib/failover_failover.lds
 145     end
 146 else
 147     if CONFIG_USE_FALLBACK_IMAGE
 148                 ldscript /arch/i386/lib/failover.lds
 149     end
 150 end
 151
 152 ##
 153 ## Setup RAM
 154 ##
 155         if CONFIG_USE_INIT
 156                 initobject cache_as_ram_auto.o
 157         else
 158                 mainboardinit ./cache_as_ram_auto.inc
 159         end
 160
 161 ##
 162 ## Include the secondary Configuration files
 163 ##
 164 config chip.h
 165
 166 chip northbridge/amd/amdk8/root_complex
 167         device apic_cluster 0 on
 168                 chip cpu/amd/socket_F
 169                         device apic 0 on end
 170                 end
 171         end
 172         device pci_domain 0 on
 173                 chip northbridge/amd/amdk8 #mc0
 174                         device pci 18.0 on end
 175                         device pci 18.0 on end
 176                         device pci 18.0 on
 177                                 #  devices on link 0, link 0 == LDT 0
 178                                 chip southbridge/nvidia/mcp55
 179                                         device pci 0.0 on end   # HT
 180                                         device pci 1.0 on # LPC
 181                                                 chip superio/winbond/w83627hf
 182                                                         device pnp 2e.0 off #  Floppy
 183                                                                 io 0x60 = 0x3f0
 184                                                                 irq 0x70 = 6
 185                                                                 drq 0x74 = 2
 186                                                         end
 187                                                         device pnp 2e.1 off #  Parallel Port
 188                                                                 io 0x60 = 0x378
 189                                                                 irq 0x70 = 7
 190                                                         end
 191                                                         device pnp 2e.2 on #  Com1
 192                                                                 io 0x60 = 0x3f8
 193                                                                 irq 0x70 = 4
 194                                                         end
 195                                                         device pnp 2e.3 on #  Com2
 196                                                                 io 0x60 = 0x2f8
 197                                                                 irq 0x70 = 3
 198                                                         end
 199                                                         device pnp 2e.5 on #  Keyboard
 200                                                                 io 0x60 = 0x60
 201                                                                 io 0x62 = 0x64
 202                                                                 irq 0x70 = 1
 203                                                                 irq 0x72 = 12
 204                                                         end
 205                                                         device pnp 2e.6 off  # SFI
 206                                                                 io 0x62 = 0x100
 207                                                         end
 208                                                         device pnp 2e.7 off #  GPIO_GAME_MIDI
 209                                                                 io 0x60 = 0x220
 210                                                                 io 0x62 = 0x300
 211                                                                 irq 0x70 = 9
 212                                                         end
 213                                                         device pnp 2e.8 off end #  WDTO_PLED
 214                                                         device pnp 2e.9 off end #  GPIO_SUSLED
 215                                                         device pnp 2e.a off end #  ACPI
 216                                                         device pnp 2e.b on #  HW Monitor
 217                                                                 io 0x60 = 0x290
 218                                                                 irq 0x70 = 5
 219                                                         end
 220                                                 end
 221                                         end
 222                                         device pci 1.1 on # SM 0
 223                                                 chip drivers/generic/generic #dimm 0-0-0
 224                                                         device i2c 50 on end
 225                                                 end
 226                                                 chip drivers/generic/generic #dimm 0-0-1
 227                                                         device i2c 51 on end
 228                                                 end
 229                                                 chip drivers/generic/generic #dimm 0-1-0
 230                                                         device i2c 52 on end
 231                                                 end
 232                                                 chip drivers/generic/generic #dimm 0-1-1
 233                                                         device i2c 53 on end
 234                                                 end
 235                                                 chip drivers/generic/generic #dimm 1-0-0
 236                                                         device i2c 54 on end
 237                                                 end
 238                                                 chip drivers/generic/generic #dimm 1-0-1
 239                                                         device i2c 55 on end
 240                                                 end
 241                                                 chip drivers/generic/generic #dimm 1-1-0
 242                                                         device i2c 56 on end
 243                                                 end
 244                                                 chip drivers/generic/generic #dimm 1-1-1
 245                                                         device i2c 57 on end
 246                                                 end
 247                                         end # SM
 248                                         device pci 1.1 on # SM 1
 249 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 250 #                                               chip drivers/generic/generic #PCIXA Slot1
 251 #                                                       device i2c 50 on end
 252 #                                               end
 253 #                                               chip drivers/generic/generic #PCIXB Slot1
 254 #                                                       device i2c 51 on end
 255 #                                               end
 256 #                                               chip drivers/generic/generic #PCIXB Slot2
 257 #                                                       device i2c 52 on end
 258 #                                               end
 259 #                                               chip drivers/generic/generic #PCI Slot1
 260 #                                                       device i2c 53 on end
 261 #                                               end
 262 #                                               chip drivers/generic/generic #Master MCP55 PCI-E
 263 #                                                       device i2c 54 on end
 264 #                                               end
 265 #                                               chip drivers/generic/generic #Slave MCP55 PCI-E
 266 #                                                       device i2c 55 on end
 267 #                                               end
 268                                                 chip drivers/generic/generic #MAC EEPROM
 269                                                         device i2c 51 on end
 270                                                 end
 271
 272                                         end # SM
 273                                         device pci 2.0 on end # USB 1.1
 274                                         device pci 2.1 on end # USB 2
 275                                         device pci 4.0 on end # IDE
 276                                         device pci 5.0 on end # SATA 0
 277                                         device pci 5.1 on end # SATA 1
 278                                         device pci 5.2 on end # SATA 2
 279                                         device pci 6.0 on end # PCI
 280                                         device pci 6.1 off end # AZA
 281                                         device pci 8.0 on end # NIC
 282                                         device pci 9.0 on end # NIC
 283                                         device pci a.0 on end # PCI E 5
 284                                         device pci b.0 off end # PCI E 4
 285                                         device pci c.0 off end # PCI E 3
 286                                         device pci d.0 on end # PCI E 2
 287                                         device pci e.0 off end # PCI E 1
 288                                         device pci f.0 on end # PCI E 0
 289                                         register "ide0_enable" = "1"
 290                                         register "sata0_enable" = "1"
 291                                         register "sata1_enable" = "1"
 292                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 293                                         register "mac_eeprom_addr" = "0x51"
 294                                 end
 295                         end #  device pci 18.0
 296                         device pci 18.1 on end
 297                         device pci 18.2 on end
 298                         device pci 18.3 on end
 299                 end # mc0
 300
 301         end # PCI domain
 302
 303 #       chip drivers/generic/debug
 304 #               device pnp 0.0 off end # chip name
 305 #               device pnp 0.1 on end # pci_regs_all
 306 #               device pnp 0.2 on end # mem
 307 #               device pnp 0.3 off end # cpuid
 308 #               device pnp 0.4 on end # smbus_regs_all
 309 #               device pnp 0.5 off end # dual core msr
 310 #               device pnp 0.6 off end # cache size
 311 #               device pnp 0.7 off end # tsc
 312 #               device pnp 0.8 off  end # io
 313 #               device pnp 0.9 off end # io
 314 #       end
 315 end #root_complex